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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Daniel Boulby95fb1aa2022-01-19 11:20:05 +00002 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
Achin Gupta4f6ad662013-10-25 09:08:21 +01009#include <arch.h>
Dan Handley714a0d22014-04-09 13:13:04 +010010#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <bl31/ea_handle.h>
12#include <bl31/interrupt_mgmt.h>
13#include <common/runtime_svc.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010014#include <context.h>
Manish V Badarkhee07e8082020-07-23 12:43:25 +010015#include <el3_common_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <lib/el3_runtime/cpu_data.h>
17#include <lib/smccc.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010018
19 .globl runtime_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010020
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000021 .globl sync_exception_sp_el0
22 .globl irq_sp_el0
23 .globl fiq_sp_el0
24 .globl serror_sp_el0
25
26 .globl sync_exception_sp_elx
27 .globl irq_sp_elx
28 .globl fiq_sp_elx
29 .globl serror_sp_elx
30
31 .globl sync_exception_aarch64
32 .globl irq_aarch64
33 .globl fiq_aarch64
34 .globl serror_aarch64
35
36 .globl sync_exception_aarch32
37 .globl irq_aarch32
38 .globl fiq_aarch32
39 .globl serror_aarch32
40
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +000041 /*
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010042 * Macro that prepares entry to EL3 upon taking an exception.
43 *
44 * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB
45 * instruction. When an error is thus synchronized, the handling is
46 * delegated to platform EA handler.
47 *
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050048 * Without RAS_EXTENSION, this macro synchronizes pending errors using
49 * a DSB, unmasks Asynchronous External Aborts and saves X30 before
50 * setting the flag CTX_IS_IN_EL3.
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010051 */
52 .macro check_and_unmask_ea
53#if RAS_EXTENSION
54 /* Synchronize pending External Aborts */
55 esb
56
57 /* Unmask the SError interrupt */
58 msr daifclr, #DAIF_ABT_BIT
59
60 /*
61 * Explicitly save x30 so as to free up a register and to enable
62 * branching
63 */
64 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
65
66 /* Check for SErrors synchronized by the ESB instruction */
67 mrs x30, DISR_EL1
68 tbz x30, #DISR_A_BIT, 1f
69
Alexei Fedorov503bbf32019-08-13 15:17:53 +010070 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +010071 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
72 * If Secure Cycle Counter is not disabled in MDCR_EL3 when
73 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
Daniel Boulby928747f2021-05-25 18:09:34 +010074 * Also set the PSTATE to a known state.
Alexei Fedorov503bbf32019-08-13 15:17:53 +010075 */
Daniel Boulby95fb1aa2022-01-19 11:20:05 +000076 bl prepare_el3_entry
Alexei Fedorov503bbf32019-08-13 15:17:53 +010077
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010078 bl handle_lower_el_ea_esb
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010079
Alexei Fedorovf41355c2019-09-13 14:11:59 +010080 /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */
81 bl restore_gp_pmcr_pauth_regs
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100821:
83#else
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050084 /*
85 * For SoCs which do not implement RAS, use DSB as a barrier to
86 * synchronize pending external aborts.
87 */
88 dsb sy
89
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010090 /* Unmask the SError interrupt */
91 msr daifclr, #DAIF_ABT_BIT
92
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050093 /* Use ISB for the above unmask operation to take effect immediately */
94 isb
95
96 /*
97 * Refer Note 1. No need to restore X30 as both handle_sync_exception
98 * and handle_interrupt_exception macro which follow this macro modify
99 * X30 anyway.
100 */
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100101 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500102 mov x30, #1
103 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
104 dmb sy
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100105#endif
106 .endm
107
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500108#if !RAS_EXTENSION
109 /*
110 * Note 1: The explicit DSB at the entry of various exception vectors
111 * for handling exceptions from lower ELs can inadvertently trigger an
112 * SError exception in EL3 due to pending asynchronous aborts in lower
113 * ELs. This will end up being handled by serror_sp_elx which will
114 * ultimately panic and die.
115 * The way to workaround is to update a flag to indicate if the exception
116 * truly came from EL3. This flag is allocated in the cpu_context
117 * structure and located at offset "CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3"
118 * This is not a bullet proof solution to the problem at hand because
119 * we assume the instructions following "isb" that help to update the
120 * flag execute without causing further exceptions.
121 */
122
123 /* ---------------------------------------------------------------------
124 * This macro handles Asynchronous External Aborts.
125 * ---------------------------------------------------------------------
126 */
127 .macro handle_async_ea
128 /*
129 * Use a barrier to synchronize pending external aborts.
130 */
131 dsb sy
132
133 /* Unmask the SError interrupt */
134 msr daifclr, #DAIF_ABT_BIT
135
136 /* Use ISB for the above unmask operation to take effect immediately */
137 isb
138
139 /* Refer Note 1 */
140 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
141 mov x30, #1
142 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
143 dmb sy
144
145 b handle_lower_el_async_ea
146 .endm
147
148 /*
149 * This macro checks if the exception was taken due to SError in EL3 or
150 * because of pending asynchronous external aborts from lower EL that got
151 * triggered due to explicit synchronization in EL3. Refer Note 1.
152 */
153 .macro check_if_serror_from_EL3
154 /* Assumes SP_EL3 on entry */
155 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
156 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
157 cbnz x30, exp_from_EL3
158
159 /* Handle asynchronous external abort from lower EL */
160 b handle_lower_el_async_ea
161
162exp_from_EL3:
163 /* Jump to plat_handle_el3_ea which does not return */
164 .endm
165#endif
166
Douglas Raillard0980eed2016-11-09 17:48:27 +0000167 /* ---------------------------------------------------------------------
168 * This macro handles Synchronous exceptions.
169 * Only SMC exceptions are supported.
170 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100171 */
172 .macro handle_sync_exception
dp-arm3cac7862016-09-19 11:18:44 +0100173#if ENABLE_RUNTIME_INSTRUMENTATION
dp-arm3cac7862016-09-19 11:18:44 +0100174 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000175 * Read the timestamp value and store it in per-cpu data. The value
176 * will be extracted from per-cpu data by the C level SMC handler and
177 * saved to the PMF timestamp region.
dp-arm3cac7862016-09-19 11:18:44 +0100178 */
179 mrs x30, cntpct_el0
180 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
181 mrs x29, tpidr_el3
182 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
183 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
184#endif
185
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100186 mrs x30, esr_el3
187 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
188
Douglas Raillard0980eed2016-11-09 17:48:27 +0000189 /* Handle SMC exceptions separately from other synchronous exceptions */
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100190 cmp x30, #EC_AARCH32_SMC
191 b.eq smc_handler32
192
193 cmp x30, #EC_AARCH64_SMC
194 b.eq smc_handler64
195
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100196 /* Synchronous exceptions other than the above are assumed to be EA */
Julius Werner67ebde72017-07-27 14:59:34 -0700197 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100198 b enter_lower_el_sync_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100199 .endm
200
201
Douglas Raillard0980eed2016-11-09 17:48:27 +0000202 /* ---------------------------------------------------------------------
203 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
204 * interrupts.
205 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100206 */
207 .macro handle_interrupt_exception label
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000208
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100209 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100210 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
211 * If Secure Cycle Counter is not disabled in MDCR_EL3 when
212 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
Daniel Boulby928747f2021-05-25 18:09:34 +0100213 * Also set the PSTATE to a known state.
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100214 */
Daniel Boulby95fb1aa2022-01-19 11:20:05 +0000215 bl prepare_el3_entry
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100216
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000217#if ENABLE_PAUTH
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100218 /* Load and program APIAKey firmware key */
219 bl pauth_load_bl31_apiakey
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000220#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000221
Douglas Raillard0980eed2016-11-09 17:48:27 +0000222 /* Save the EL3 system registers needed to return from this exception */
Achin Gupta979992e2015-05-13 17:57:18 +0100223 mrs x0, spsr_el3
224 mrs x1, elr_el3
225 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
226
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100227 /* Switch to the runtime stack i.e. SP_EL0 */
228 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
229 mov x20, sp
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100230 msr spsel, #MODE_SP_EL0
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100231 mov sp, x2
232
233 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000234 * Find out whether this is a valid interrupt type.
235 * If the interrupt controller reports a spurious interrupt then return
236 * to where we came from.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100237 */
Dan Handley701fea72014-05-27 16:17:21 +0100238 bl plat_ic_get_pending_interrupt_type
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100239 cmp x0, #INTR_TYPE_INVAL
240 b.eq interrupt_exit_\label
241
242 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000243 * Get the registered handler for this interrupt type.
244 * A NULL return value could be 'cause of the following conditions:
Achin Gupta979992e2015-05-13 17:57:18 +0100245 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000246 * a. An interrupt of a type was routed correctly but a handler for its
247 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100248 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000249 * b. An interrupt of a type was not routed correctly so a handler for
250 * its type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100251 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000252 * c. An interrupt of a type was routed correctly to EL3, but was
253 * deasserted before its pending state could be read. Another
254 * interrupt of a different type pended at the same time and its
255 * type was reported as pending instead. However, a handler for this
256 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100257 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000258 * a. and b. can only happen due to a programming error. The
259 * occurrence of c. could be beyond the control of Trusted Firmware.
260 * It makes sense to return from this exception instead of reporting an
261 * error.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100262 */
263 bl get_interrupt_type_handler
Achin Gupta979992e2015-05-13 17:57:18 +0100264 cbz x0, interrupt_exit_\label
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100265 mov x21, x0
266
267 mov x0, #INTR_ID_UNAVAILABLE
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100268
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100269 /* Set the current security state in the 'flags' parameter */
270 mrs x2, scr_el3
271 ubfx x1, x2, #0, #1
272
273 /* Restore the reference to the 'handle' i.e. SP_EL3 */
274 mov x2, x20
275
Douglas Raillard0980eed2016-11-09 17:48:27 +0000276 /* x3 will point to a cookie (not used now) */
Soby Mathew799f0ab2014-05-27 16:54:31 +0100277 mov x3, xzr
278
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100279 /* Call the interrupt type handler */
280 blr x21
281
282interrupt_exit_\label:
283 /* Return from exception, possibly in a different security state */
284 b el3_exit
285
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100286 .endm
287
288
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100289vector_base runtime_exceptions
290
Douglas Raillard0980eed2016-11-09 17:48:27 +0000291 /* ---------------------------------------------------------------------
292 * Current EL with SP_EL0 : 0x0 - 0x200
293 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100294 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100295vector_entry sync_exception_sp_el0
Justin Chadwell83e04882019-08-20 11:01:52 +0100296#ifdef MONITOR_TRAPS
297 stp x29, x30, [sp, #-16]!
298
299 mrs x30, esr_el3
300 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
301
302 /* Check for BRK */
303 cmp x30, #EC_BRK
304 b.eq brk_handler
305
306 ldp x29, x30, [sp], #16
307#endif /* MONITOR_TRAPS */
308
Douglas Raillard0980eed2016-11-09 17:48:27 +0000309 /* We don't expect any synchronous exceptions from EL3 */
Julius Werner67ebde72017-07-27 14:59:34 -0700310 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100311end_vector_entry sync_exception_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100312
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100313vector_entry irq_sp_el0
Douglas Raillard0980eed2016-11-09 17:48:27 +0000314 /*
315 * EL3 code is non-reentrant. Any asynchronous exception is a serious
316 * error. Loop infinitely.
317 */
Julius Werner67ebde72017-07-27 14:59:34 -0700318 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100319end_vector_entry irq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100320
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100321
322vector_entry fiq_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -0700323 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100324end_vector_entry fiq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100325
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100326
327vector_entry serror_sp_el0
Jeenu Viswambharan911fcc92018-07-06 16:50:06 +0100328 no_ret plat_handle_el3_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100329end_vector_entry serror_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100330
Douglas Raillard0980eed2016-11-09 17:48:27 +0000331 /* ---------------------------------------------------------------------
332 * Current EL with SP_ELx: 0x200 - 0x400
333 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100334 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100335vector_entry sync_exception_sp_elx
Douglas Raillard0980eed2016-11-09 17:48:27 +0000336 /*
337 * This exception will trigger if anything went wrong during a previous
338 * exception entry or exit or while handling an earlier unexpected
339 * synchronous exception. There is a high probability that SP_EL3 is
340 * corrupted.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000341 */
Julius Werner67ebde72017-07-27 14:59:34 -0700342 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100343end_vector_entry sync_exception_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100344
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100345vector_entry irq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700346 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100347end_vector_entry irq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000348
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100349vector_entry fiq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700350 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100351end_vector_entry fiq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000352
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100353vector_entry serror_sp_elx
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500354#if !RAS_EXTENSION
355 check_if_serror_from_EL3
356#endif
Jeenu Viswambharan911fcc92018-07-06 16:50:06 +0100357 no_ret plat_handle_el3_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100358end_vector_entry serror_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100359
Douglas Raillard0980eed2016-11-09 17:48:27 +0000360 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100361 * Lower EL using AArch64 : 0x400 - 0x600
Douglas Raillard0980eed2016-11-09 17:48:27 +0000362 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100363 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100364vector_entry sync_exception_aarch64
Douglas Raillard0980eed2016-11-09 17:48:27 +0000365 /*
366 * This exception vector will be the entry point for SMCs and traps
367 * that are unhandled at lower ELs most commonly. SP_EL3 should point
368 * to a valid cpu context where the general purpose and system register
369 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000370 */
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100371 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100372 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000373 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100374end_vector_entry sync_exception_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100375
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100376vector_entry irq_aarch64
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100377 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100378 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100379 handle_interrupt_exception irq_aarch64
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100380end_vector_entry irq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100381
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100382vector_entry fiq_aarch64
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100383 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100384 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100385 handle_interrupt_exception fiq_aarch64
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100386end_vector_entry fiq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100387
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100388vector_entry serror_aarch64
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100389 apply_at_speculative_wa
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500390#if RAS_EXTENSION
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000391 msr daifclr, #DAIF_ABT_BIT
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100392 b enter_lower_el_async_ea
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500393#else
394 handle_async_ea
395#endif
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100396end_vector_entry serror_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100397
Douglas Raillard0980eed2016-11-09 17:48:27 +0000398 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100399 * Lower EL using AArch32 : 0x600 - 0x800
Douglas Raillard0980eed2016-11-09 17:48:27 +0000400 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100401 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100402vector_entry sync_exception_aarch32
Douglas Raillard0980eed2016-11-09 17:48:27 +0000403 /*
404 * This exception vector will be the entry point for SMCs and traps
405 * that are unhandled at lower ELs most commonly. SP_EL3 should point
406 * to a valid cpu context where the general purpose and system register
407 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000408 */
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100409 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100410 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000411 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100412end_vector_entry sync_exception_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100413
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100414vector_entry irq_aarch32
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100415 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100416 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100417 handle_interrupt_exception irq_aarch32
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100418end_vector_entry irq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100419
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100420vector_entry fiq_aarch32
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100421 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100422 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100423 handle_interrupt_exception fiq_aarch32
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100424end_vector_entry fiq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100425
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100426vector_entry serror_aarch32
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100427 apply_at_speculative_wa
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500428#if RAS_EXTENSION
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000429 msr daifclr, #DAIF_ABT_BIT
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100430 b enter_lower_el_async_ea
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500431#else
432 handle_async_ea
433#endif
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100434end_vector_entry serror_aarch32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000435
Justin Chadwell83e04882019-08-20 11:01:52 +0100436#ifdef MONITOR_TRAPS
437 .section .rodata.brk_string, "aS"
438brk_location:
439 .asciz "Error at instruction 0x"
440brk_message:
441 .asciz "Unexpected BRK instruction with value 0x"
442#endif /* MONITOR_TRAPS */
443
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100444 /* ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000445 * The following code handles secure monitor calls.
Douglas Raillard0980eed2016-11-09 17:48:27 +0000446 * Depending upon the execution state from where the SMC has been
447 * invoked, it frees some general purpose registers to perform the
448 * remaining tasks. They involve finding the runtime service handler
449 * that is the target of the SMC & switching to runtime stacks (SP_EL0)
450 * before calling the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000451 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000452 * Note that x30 has been explicitly saved and can be used here
453 * ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000454 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000455func smc_handler
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000456smc_handler32:
457 /* Check whether aarch32 issued an SMC64 */
458 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
459
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000460smc_handler64:
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000461 /* NOTE: The code below must preserve x0-x4 */
462
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100463 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100464 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
465 * If Secure Cycle Counter is not disabled in MDCR_EL3 when
466 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
Daniel Boulby928747f2021-05-25 18:09:34 +0100467 * Also set the PSTATE to a known state.
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100468 */
Daniel Boulby95fb1aa2022-01-19 11:20:05 +0000469 bl prepare_el3_entry
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100470
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000471#if ENABLE_PAUTH
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100472 /* Load and program APIAKey firmware key */
473 bl pauth_load_bl31_apiakey
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000474#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000475
Douglas Raillard0980eed2016-11-09 17:48:27 +0000476 /*
477 * Populate the parameters for the SMC handler.
478 * We already have x0-x4 in place. x5 will point to a cookie (not used
479 * now). x6 will point to the context structure (SP_EL3) and x7 will
Dimitris Papastamos04159512018-01-22 11:53:04 +0000480 * contain flags we need to pass to the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000481 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000482 mov x5, xzr
483 mov x6, sp
484
Douglas Raillard0980eed2016-11-09 17:48:27 +0000485 /*
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100486 * Restore the saved C runtime stack value which will become the new
487 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
488 * structure prior to the last ERET from EL3.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000489 */
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100490 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
491
492 /* Switch to SP_EL0 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100493 msr spsel, #MODE_SP_EL0
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000494
Douglas Raillard0980eed2016-11-09 17:48:27 +0000495 /*
496 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world
497 * switch during SMC handling.
498 * TODO: Revisit if all system registers can be saved later.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000499 */
500 mrs x16, spsr_el3
501 mrs x17, elr_el3
502 mrs x18, scr_el3
503 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
Achin Guptae1aa5162014-06-26 09:58:52 +0100504 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000505
Zelalem Aweke4d666ac2021-07-08 17:13:09 -0500506 /* Clear flag register */
507 mov x7, xzr
508
509#if ENABLE_RME
510 /* Copy SCR_EL3.NSE bit to the flag to indicate caller's security */
511 ubfx x7, x18, #SCR_NSE_SHIFT, 1
512
513 /*
514 * Shift copied SCR_EL3.NSE bit by 5 to create space for
Olivier Deprez33dd8452022-10-11 15:38:27 +0200515 * SCR_EL3.NS bit. Bit 5 of the flag corresponds to
Zelalem Aweke4d666ac2021-07-08 17:13:09 -0500516 * the SCR_EL3.NSE bit.
517 */
518 lsl x7, x7, #5
519#endif /* ENABLE_RME */
520
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000521 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
522 bfi x7, x18, #0, #1
523
Olivier Deprez33dd8452022-10-11 15:38:27 +0200524 /*
525 * Per SMCCCv1.3 a caller can set the SVE hint bit in the SMC FID
526 * passed through x0. Copy the SVE hint bit to flags and mask the
527 * bit in smc_fid passed to the standard service dispatcher.
528 * A service/dispatcher can retrieve the SVE hint bit state from
529 * flags using the appropriate helper.
530 */
531 bfi x7, x0, #FUNCID_SVE_HINT_SHIFT, #FUNCID_SVE_HINT_MASK
532 bic x0, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT)
533
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000534 mov sp, x12
535
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500536 /* Get the unique owning entity number */
537 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
538 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
539 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
540
541 /* Load descriptor index from array of indices */
Madhukar Pappireddyf4e6ea62020-01-27 15:32:15 -0600542 adrp x14, rt_svc_descs_indices
543 add x14, x14, :lo12:rt_svc_descs_indices
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500544 ldrb w15, [x14, x16]
545
546 /* Any index greater than 127 is invalid. Check bit 7. */
547 tbnz w15, 7, smc_unknown
548
Douglas Raillard0980eed2016-11-09 17:48:27 +0000549 /*
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500550 * Get the descriptor using the index
551 * x11 = (base + off), w15 = index
552 *
553 * handler = (base + off) + (index << log2(size))
554 */
555 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
556 lsl w10, w15, #RT_SVC_SIZE_LOG2
557 ldr x15, [x11, w10, uxtw]
558
559 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000560 * Call the Secure Monitor Call handler and then drop directly into
561 * el3_exit() which will program any remaining architectural state
562 * prior to issuing the ERET to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000563 */
564#if DEBUG
565 cbz x15, rt_svc_fw_critical_error
566#endif
567 blr x15
568
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100569 b el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +0100570
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000571smc_unknown:
572 /*
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500573 * Unknown SMC call. Populate return value with SMC_UNK and call
574 * el3_exit() which will restore the remaining architectural state
575 * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET
576 * to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000577 */
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000578 mov x0, #SMC_UNK
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500579 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
580 b el3_exit
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000581
582smc_prohibited:
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100583 restore_ptw_el1_sys_regs
584 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
Soby Mathew6c5192a2014-04-30 15:36:37 +0100585 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000586 mov x0, #SMC_UNK
Anthony Steinhauser0f7e6012020-01-07 15:44:06 -0800587 exception_return
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000588
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100589#if DEBUG
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000590rt_svc_fw_critical_error:
Douglas Raillard0980eed2016-11-09 17:48:27 +0000591 /* Switch to SP_ELx */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100592 msr spsel, #MODE_SP_ELX
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000593 no_ret report_unhandled_exception
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100594#endif
Kévin Petita877c252015-03-24 14:03:57 +0000595endfunc smc_handler
Justin Chadwell83e04882019-08-20 11:01:52 +0100596
597 /* ---------------------------------------------------------------------
598 * The following code handles exceptions caused by BRK instructions.
599 * Following a BRK instruction, the only real valid cause of action is
600 * to print some information and panic, as the code that caused it is
601 * likely in an inconsistent internal state.
602 *
603 * This is initially intended to be used in conjunction with
604 * __builtin_trap.
605 * ---------------------------------------------------------------------
606 */
607#ifdef MONITOR_TRAPS
608func brk_handler
609 /* Extract the ISS */
610 mrs x10, esr_el3
611 ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH
612
613 /* Ensure the console is initialized */
614 bl plat_crash_console_init
615
616 adr x4, brk_location
617 bl asm_print_str
618 mrs x4, elr_el3
619 bl asm_print_hex
620 bl asm_print_newline
621
622 adr x4, brk_message
623 bl asm_print_str
624 mov x4, x10
625 mov x5, #28
626 bl asm_print_hex_bits
627 bl asm_print_newline
628
629 no_ret plat_panic_handler
630endfunc brk_handler
631#endif /* MONITOR_TRAPS */