Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __TEGRA_DEF_H__ |
| 8 | #define __TEGRA_DEF_H__ |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | /******************************************************************************* |
| 13 | * These values are used by the PSCI implementation during the `CPU_SUSPEND` |
| 14 | * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' |
| 15 | * parameter. |
| 16 | ******************************************************************************/ |
| 17 | #define PSTATE_ID_CORE_IDLE 6 |
| 18 | #define PSTATE_ID_CORE_POWERDN 7 |
| 19 | #define PSTATE_ID_SOC_POWERDN 2 |
| 20 | |
| 21 | /******************************************************************************* |
| 22 | * Platform power states (used by PSCI framework) |
| 23 | * |
| 24 | * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID |
| 25 | * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID |
| 26 | ******************************************************************************/ |
| 27 | #define PLAT_MAX_RET_STATE 1 |
| 28 | #define PLAT_MAX_OFF_STATE 8 |
| 29 | |
| 30 | /******************************************************************************* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 31 | * Secure IRQ definitions |
| 32 | ******************************************************************************/ |
| 33 | #define TEGRA186_MAX_SEC_IRQS 5 |
| 34 | #define TEGRA186_BPMP_WDT_IRQ 46 |
| 35 | #define TEGRA186_SPE_WDT_IRQ 47 |
| 36 | #define TEGRA186_SCE_WDT_IRQ 48 |
| 37 | #define TEGRA186_TOP_WDT_IRQ 49 |
| 38 | #define TEGRA186_AON_WDT_IRQ 50 |
| 39 | |
| 40 | #define TEGRA186_SEC_IRQ_TARGET_MASK 0xFF /* 8 Carmel */ |
| 41 | |
| 42 | /******************************************************************************* |
| 43 | * Tegra Miscellanous register constants |
| 44 | ******************************************************************************/ |
Steven Kao | 7dfbca7 | 2017-07-25 12:44:32 +0800 | [diff] [blame] | 45 | #define TEGRA_MISC_BASE 0x00100000U |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 46 | |
Steven Kao | 7dfbca7 | 2017-07-25 12:44:32 +0800 | [diff] [blame] | 47 | #define HARDWARE_REVISION_OFFSET 0x4U |
| 48 | #define MISCREG_EMU_REVID 0x3160U |
| 49 | #define BOARD_MASK_BITS 0xFFU |
| 50 | #define BOARD_SHIFT_BITS 24U |
| 51 | #define MISCREG_PFCFG 0x200CU |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 52 | |
| 53 | /******************************************************************************* |
| 54 | * Tegra TSA Controller constants |
| 55 | ******************************************************************************/ |
| 56 | #define TEGRA_TSA_BASE 0x02000000 |
| 57 | |
| 58 | #define TSA_CONFIG_STATIC0_CSW_SESWR 0x1010 |
| 59 | #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 |
| 60 | #define TSA_CONFIG_STATIC0_CSW_ETRW 0xD034 |
| 61 | #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 |
| 62 | #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x3020 |
| 63 | #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 |
| 64 | #define TSA_CONFIG_STATIC0_CSW_AXISW 0x8008 |
| 65 | #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 |
| 66 | #define TSA_CONFIG_STATIC0_CSW_HDAW 0xD008 |
| 67 | #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x1100 |
| 68 | #define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xE018 |
| 69 | #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 |
| 70 | #define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x9008 |
| 71 | #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 |
| 72 | #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9028 |
| 73 | #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 |
| 74 | #define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xB008 |
| 75 | #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 |
| 76 | #define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6008 |
| 77 | #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 |
| 78 | #define TSA_CONFIG_STATIC0_CSW_AFIW 0xF008 |
| 79 | #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 |
| 80 | #define TSA_CONFIG_STATIC0_CSW_SATAW 0x4008 |
| 81 | #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 |
| 82 | #define TSA_CONFIG_STATIC0_CSW_EQOSW 0x3038 |
| 83 | #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 |
| 84 | #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x6018 |
| 85 | #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 |
| 86 | #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x6028 |
| 87 | #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 |
| 88 | |
| 89 | #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) |
| 90 | #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) |
| 91 | |
| 92 | /******************************************************************************* |
| 93 | * Tegra Memory Controller constants |
| 94 | ******************************************************************************/ |
| 95 | #define TEGRA_MC_STREAMID_BASE 0x02C00000 |
| 96 | #define TEGRA_MC_BASE 0x02C10000 |
| 97 | |
Varun Wadekar | 07897a9 | 2017-02-13 09:00:04 -0800 | [diff] [blame] | 98 | /* General Security Carveout register macros */ |
| 99 | #define MC_GSC_CONFIG_REGS_SIZE 0x40 |
| 100 | #define MC_GSC_LOCK_CFG_SETTINGS_BIT (1 << 1) |
| 101 | #define MC_GSC_ENABLE_TZ_LOCK_BIT (1 << 0) |
| 102 | #define MC_GSC_SIZE_RANGE_4KB_SHIFT 27 |
| 103 | #define MC_GSC_BASE_LO_SHIFT 12 |
| 104 | #define MC_GSC_BASE_LO_MASK 0xFFFFF |
| 105 | #define MC_GSC_BASE_HI_SHIFT 0 |
| 106 | #define MC_GSC_BASE_HI_MASK 3 |
| 107 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 108 | /* TZDRAM carveout configuration registers */ |
| 109 | #define MC_SECURITY_CFG0_0 0x70 |
| 110 | #define MC_SECURITY_CFG1_0 0x74 |
| 111 | #define MC_SECURITY_CFG3_0 0x9BC |
| 112 | |
Harvey Hsieh | 53fc032 | 2017-08-09 16:26:33 +0800 | [diff] [blame^] | 113 | #define MC_SECURITY_BOM_MASK (U(0xFFF) << 20) |
| 114 | #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) |
| 115 | #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) |
| 116 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 117 | /* Video Memory carveout configuration registers */ |
| 118 | #define MC_VIDEO_PROTECT_BASE_HI 0x978 |
| 119 | #define MC_VIDEO_PROTECT_BASE_LO 0x648 |
| 120 | #define MC_VIDEO_PROTECT_SIZE_MB 0x64c |
| 121 | |
Varun Wadekar | 07897a9 | 2017-02-13 09:00:04 -0800 | [diff] [blame] | 122 | /* |
| 123 | * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the |
| 124 | * non-overlapping Video memory region |
| 125 | */ |
| 126 | #define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0 |
| 127 | #define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4 |
| 128 | #define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8 |
| 129 | #define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC |
| 130 | #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0 |
| 131 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 132 | /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ |
Varun Wadekar | 07897a9 | 2017-02-13 09:00:04 -0800 | [diff] [blame] | 133 | #define MC_TZRAM_CARVEOUT_CFG 0x2190 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 134 | #define MC_TZRAM_BASE_LO 0x2194 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 135 | #define MC_TZRAM_BASE_HI 0x2198 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 136 | #define MC_TZRAM_SIZE 0x219C |
Varun Wadekar | 07897a9 | 2017-02-13 09:00:04 -0800 | [diff] [blame] | 137 | #define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 138 | |
| 139 | /* Memory Controller Reset Control registers */ |
| 140 | #define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1 << 27) |
| 141 | #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28) |
| 142 | #define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29) |
| 143 | #define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30) |
| 144 | #define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (1 << 31) |
| 145 | |
| 146 | /******************************************************************************* |
| 147 | * Tegra UART Controller constants |
| 148 | ******************************************************************************/ |
| 149 | #define TEGRA_UARTA_BASE 0x03100000 |
| 150 | #define TEGRA_UARTB_BASE 0x03110000 |
| 151 | #define TEGRA_UARTC_BASE 0x0C280000 |
| 152 | #define TEGRA_UARTD_BASE 0x03130000 |
| 153 | #define TEGRA_UARTE_BASE 0x03140000 |
| 154 | #define TEGRA_UARTF_BASE 0x03150000 |
| 155 | #define TEGRA_UARTG_BASE 0x0C290000 |
| 156 | |
| 157 | /******************************************************************************* |
| 158 | * Tegra Fuse Controller related constants |
| 159 | ******************************************************************************/ |
| 160 | #define TEGRA_FUSE_BASE 0x03820000 |
| 161 | #define OPT_SUBREVISION 0x248 |
| 162 | #define SUBREVISION_MASK 0xF |
| 163 | |
| 164 | /******************************************************************************* |
| 165 | * GICv2 & interrupt handling related constants |
| 166 | ******************************************************************************/ |
| 167 | #define TEGRA_GICD_BASE 0x03881000 |
| 168 | #define TEGRA_GICC_BASE 0x03882000 |
| 169 | |
| 170 | /******************************************************************************* |
| 171 | * Security Engine related constants |
| 172 | ******************************************************************************/ |
| 173 | #define TEGRA_SE0_BASE 0x03AC0000 |
| 174 | #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C |
| 175 | #define TEGRA_PKA1_BASE 0x03AD0000 |
| 176 | #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 |
| 177 | #define TEGRA_RNG1_BASE 0x03AE0000 |
| 178 | #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 |
| 179 | |
| 180 | /******************************************************************************* |
| 181 | * Tegra micro-seconds timer constants |
| 182 | ******************************************************************************/ |
| 183 | #define TEGRA_TMRUS_BASE 0x0C2E0000 |
Steven Kao | 0d87c13 | 2017-03-07 13:13:27 +0800 | [diff] [blame] | 184 | #define TEGRA_TMRUS_SIZE 0x10000 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 185 | |
| 186 | /******************************************************************************* |
| 187 | * Tegra Power Mgmt Controller constants |
| 188 | ******************************************************************************/ |
| 189 | #define TEGRA_PMC_BASE 0x0C360000 |
| 190 | |
| 191 | /******************************************************************************* |
| 192 | * Tegra scratch registers constants |
| 193 | ******************************************************************************/ |
| 194 | #define TEGRA_SCRATCH_BASE 0x0C390000 |
| 195 | #define SECURE_SCRATCH_RSV1_LO 0x06C |
| 196 | #define SECURE_SCRATCH_RSV1_HI 0x070 |
| 197 | #define SECURE_SCRATCH_RSV6 0x094 |
| 198 | #define SECURE_SCRATCH_RSV11_LO 0x0BC |
| 199 | #define SECURE_SCRATCH_RSV11_HI 0x0C0 |
| 200 | #define SECURE_SCRATCH_RSV53_LO 0x20C |
| 201 | #define SECURE_SCRATCH_RSV53_HI 0x210 |
| 202 | #define SECURE_SCRATCH_RSV54_HI 0x218 |
| 203 | #define SECURE_SCRATCH_RSV55_LO 0x21C |
| 204 | #define SECURE_SCRATCH_RSV55_HI 0x220 |
| 205 | |
| 206 | /******************************************************************************* |
| 207 | * Tegra Memory Mapped Control Register Access Bus constants |
| 208 | ******************************************************************************/ |
| 209 | #define TEGRA_MMCRAB_BASE 0x0E000000 |
| 210 | |
| 211 | /******************************************************************************* |
| 212 | * Tegra SMMU Controller constants |
| 213 | ******************************************************************************/ |
Pritesh Raithatha | 1c2b5c7 | 2017-01-24 14:16:07 +0530 | [diff] [blame] | 214 | #define TEGRA_SMMU0_BASE 0x12000000 |
| 215 | #define TEGRA_SMMU1_BASE 0x11000000 |
| 216 | #define TEGRA_SMMU2_BASE 0x10000000 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 217 | |
| 218 | /******************************************************************************* |
| 219 | * Tegra TZRAM constants |
| 220 | ******************************************************************************/ |
| 221 | #define TEGRA_TZRAM_BASE 0x40000000 |
| 222 | #define TEGRA_TZRAM_SIZE 0x40000 |
| 223 | |
| 224 | /******************************************************************************* |
| 225 | * Tegra Clock and Reset Controller constants |
| 226 | ******************************************************************************/ |
| 227 | #define TEGRA_CAR_RESET_BASE 0x200000000 |
Varun Wadekar | f2d5466 | 2017-04-26 08:57:27 -0700 | [diff] [blame] | 228 | #define TEGRA_GPU_RESET_REG_OFFSET 0x18UL |
| 229 | #define GPU_RESET_BIT (1UL << 0) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 230 | |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 231 | /******************************************************************************* |
| 232 | * Stream ID Override Config registers |
| 233 | ******************************************************************************/ |
| 234 | #define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U |
| 235 | #define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U |
| 236 | #define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U |
| 237 | #define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U |
| 238 | #define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U |
| 239 | #define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U |
| 240 | #define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U |
| 241 | #define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U |
| 242 | #define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U |
| 243 | #define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U |
| 244 | #define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U |
| 245 | #define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5E0U |
| 246 | #define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5E8U |
| 247 | #define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5F0U |
| 248 | #define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5F8U |
| 249 | #define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U |
| 250 | #define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U |
| 251 | #define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U |
| 252 | #define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U |
| 253 | #define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U |
| 254 | #define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U |
| 255 | #define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U |
| 256 | #define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U |
| 257 | #define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U |
| 258 | #define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U |
| 259 | #define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U |
| 260 | #define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U |
| 261 | #define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U |
| 262 | #define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U |
| 263 | #define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U |
| 264 | #define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U |
| 265 | #define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U |
| 266 | #define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U |
| 267 | #define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U |
| 268 | #define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U |
| 269 | #define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6A0U |
| 270 | #define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6A8U |
| 271 | #define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6B0U |
| 272 | #define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6B8U |
| 273 | #define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6C0U |
| 274 | #define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6C8U |
| 275 | #define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6D0U |
| 276 | #define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6D8U |
| 277 | #define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6E0U |
| 278 | #define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6E8U |
| 279 | #define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6F0U |
| 280 | #define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6F8U |
| 281 | #define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U |
| 282 | #define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U |
| 283 | #define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U |
| 284 | #define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U |
| 285 | #define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U |
| 286 | #define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U |
| 287 | #define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U |
| 288 | #define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U |
| 289 | #define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U |
| 290 | #define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U |
| 291 | #define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U |
| 292 | #define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U |
| 293 | #define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U |
| 294 | #define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U |
| 295 | #define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U |
| 296 | #define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U |
| 297 | #define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7C8U |
| 298 | #define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7D0U |
| 299 | #define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7D8U |
| 300 | |
| 301 | /******************************************************************************* |
| 302 | * Memory Controller transaction override config registers |
| 303 | ******************************************************************************/ |
| 304 | #define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530 |
| 305 | #define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538 |
| 306 | #define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540 |
| 307 | #define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548 |
| 308 | #define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570 |
| 309 | #define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578 |
| 310 | #define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580 |
| 311 | #define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158C |
| 312 | #define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15E4 |
| 313 | #define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15EC |
| 314 | #define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15F4 |
| 315 | #define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15FC |
| 316 | #define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604 |
| 317 | #define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160C |
| 318 | #define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614 |
| 319 | #define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161C |
| 320 | #define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624 |
| 321 | #define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162C |
| 322 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634 |
| 323 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163C |
| 324 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644 |
| 325 | #define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164C |
| 326 | #define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654 |
| 327 | #define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165C |
| 328 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664 |
| 329 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166C |
| 330 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674 |
| 331 | #define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167C |
| 332 | #define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684 |
| 333 | #define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168C |
| 334 | #define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694 |
| 335 | #define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169C |
| 336 | #define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16A4 |
| 337 | #define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16AC |
| 338 | #define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16B4 |
| 339 | #define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16BC |
| 340 | #define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16C4 |
| 341 | #define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16CC |
| 342 | #define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16D4 |
| 343 | #define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16DC |
| 344 | #define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16E4 |
| 345 | #define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16EC |
| 346 | #define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16F4 |
| 347 | #define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16FC |
| 348 | #define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704 |
| 349 | #define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170C |
| 350 | #define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714 |
| 351 | #define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171C |
| 352 | #define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724 |
| 353 | #define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174C |
| 354 | #define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754 |
| 355 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175C |
| 356 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764 |
| 357 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176C |
| 358 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774 |
| 359 | #define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177C |
| 360 | #define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784 |
| 361 | #define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178C |
| 362 | #define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794 |
| 363 | #define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179C |
| 364 | #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17CC |
| 365 | #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17D4 |
| 366 | #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17DC |
| 367 | |
Ajay Gupta | 8162109 | 2017-08-01 15:53:04 -0700 | [diff] [blame] | 368 | /******************************************************************************* |
| 369 | * XUSB PADCTL |
| 370 | ******************************************************************************/ |
| 371 | #define TEGRA_XUSB_PADCTL_BASE (0x3520000U) |
| 372 | #define TEGRA_XUSB_PADCTL_SIZE (0x10000U) |
| 373 | #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) |
| 374 | #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) |
| 375 | #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) |
| 376 | #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) |
| 377 | #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) |
| 378 | #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) |
| 379 | |
| 380 | /******************************************************************************* |
| 381 | * XUSB STREAMIDs |
| 382 | ******************************************************************************/ |
| 383 | #define TEGRA_SID_XUSB_HOST (0x1bU) |
| 384 | #define TEGRA_SID_XUSB_DEV (0x1cU) |
| 385 | #define TEGRA_SID_XUSB_VF0 (0x5dU) |
| 386 | #define TEGRA_SID_XUSB_VF1 (0x5eU) |
| 387 | #define TEGRA_SID_XUSB_VF2 (0x5fU) |
| 388 | #define TEGRA_SID_XUSB_VF3 (0x60U) |
| 389 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 390 | #endif /* __TEGRA_DEF_H__ */ |