Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 1 | /* |
Yann Gautier | dca6154 | 2021-02-10 18:19:23 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 7 | #include <assert.h> |
Yann Gautier | 658775c | 2021-07-06 10:00:44 +0200 | [diff] [blame] | 8 | #include <errno.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <string.h> |
| 10 | |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 11 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | |
| 13 | #include <arch_helpers.h> |
| 14 | #include <common/bl_common.h> |
| 15 | #include <common/debug.h> |
| 16 | #include <common/desc_image_load.h> |
| 17 | #include <drivers/delay_timer.h> |
| 18 | #include <drivers/generic_delay_timer.h> |
Yann Gautier | a3bd8d1 | 2021-06-18 11:33:26 +0200 | [diff] [blame] | 19 | #include <drivers/mmc.h> |
Yann Gautier | 3edc7c3 | 2019-05-20 19:17:08 +0200 | [diff] [blame] | 20 | #include <drivers/st/bsec.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 21 | #include <drivers/st/stm32_console.h> |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 22 | #include <drivers/st/stm32_iwdg.h> |
Yann Gautier | a45433b | 2019-01-16 18:31:00 +0100 | [diff] [blame] | 23 | #include <drivers/st/stm32mp_pmic.h> |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 24 | #include <drivers/st/stm32mp_reset.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 25 | #include <drivers/st/stm32mp1_clk.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 26 | #include <drivers/st/stm32mp1_pwr.h> |
| 27 | #include <drivers/st/stm32mp1_ram.h> |
Yann Gautier | 658775c | 2021-07-06 10:00:44 +0200 | [diff] [blame] | 28 | #include <lib/fconf/fconf.h> |
| 29 | #include <lib/fconf/fconf_dyn_cfg_getter.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 30 | #include <lib/mmio.h> |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 31 | #include <lib/optee_utils.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 32 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 33 | #include <plat/common/platform.h> |
| 34 | |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 35 | #include <stm32mp1_dbgmcu.h> |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 36 | |
Etienne Carriere | f02647a | 2019-12-08 08:14:40 +0100 | [diff] [blame] | 37 | #define RESET_TIMEOUT_US_1MS 1000U |
| 38 | |
Andre Przywara | 678c6fa | 2020-01-25 00:58:35 +0000 | [diff] [blame] | 39 | static console_t console; |
Lionel Debieve | 7bd96f4 | 2019-09-03 12:22:23 +0200 | [diff] [blame] | 40 | static struct stm32mp_auth_ops stm32mp1_auth_ops; |
Yann Gautier | 8593e44 | 2018-11-14 18:46:15 +0100 | [diff] [blame] | 41 | |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 42 | static void print_reset_reason(void) |
| 43 | { |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 44 | uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 45 | |
| 46 | if (rstsr == 0U) { |
| 47 | WARN("Reset reason unknown\n"); |
| 48 | return; |
| 49 | } |
| 50 | |
| 51 | INFO("Reset reason (0x%x):\n", rstsr); |
| 52 | |
| 53 | if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { |
| 54 | if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { |
| 55 | INFO("System exits from STANDBY\n"); |
| 56 | return; |
| 57 | } |
| 58 | |
| 59 | if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { |
| 60 | INFO("MPU exits from CSTANDBY\n"); |
| 61 | return; |
| 62 | } |
| 63 | } |
| 64 | |
| 65 | if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { |
| 66 | INFO(" Power-on Reset (rst_por)\n"); |
| 67 | return; |
| 68 | } |
| 69 | |
| 70 | if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { |
| 71 | INFO(" Brownout Reset (rst_bor)\n"); |
| 72 | return; |
| 73 | } |
| 74 | |
| 75 | if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { |
| 76 | if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { |
| 77 | INFO(" System reset generated by MCU (MCSYSRST)\n"); |
| 78 | } else { |
| 79 | INFO(" Local reset generated by MCU (MCSYSRST)\n"); |
| 80 | } |
| 81 | return; |
| 82 | } |
| 83 | |
| 84 | if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { |
| 85 | INFO(" System reset generated by MPU (MPSYSRST)\n"); |
| 86 | return; |
| 87 | } |
| 88 | |
| 89 | if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { |
| 90 | INFO(" Reset due to a clock failure on HSE\n"); |
| 91 | return; |
| 92 | } |
| 93 | |
| 94 | if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { |
| 95 | INFO(" IWDG1 Reset (rst_iwdg1)\n"); |
| 96 | return; |
| 97 | } |
| 98 | |
| 99 | if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { |
| 100 | INFO(" IWDG2 Reset (rst_iwdg2)\n"); |
| 101 | return; |
| 102 | } |
| 103 | |
| 104 | if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { |
| 105 | INFO(" MPU Processor 0 Reset\n"); |
| 106 | return; |
| 107 | } |
| 108 | |
| 109 | if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { |
| 110 | INFO(" MPU Processor 1 Reset\n"); |
| 111 | return; |
| 112 | } |
| 113 | |
| 114 | if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { |
| 115 | INFO(" Pad Reset from NRST\n"); |
| 116 | return; |
| 117 | } |
| 118 | |
| 119 | if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { |
| 120 | INFO(" Reset due to a failure of VDD_CORE\n"); |
| 121 | return; |
| 122 | } |
| 123 | |
| 124 | ERROR(" Unidentified reset reason\n"); |
| 125 | } |
| 126 | |
| 127 | void bl2_el3_early_platform_setup(u_register_t arg0, |
| 128 | u_register_t arg1 __unused, |
| 129 | u_register_t arg2 __unused, |
| 130 | u_register_t arg3 __unused) |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 131 | { |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 132 | stm32mp_save_boot_ctx_address(arg0); |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 133 | } |
| 134 | |
| 135 | void bl2_platform_setup(void) |
| 136 | { |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 137 | int ret; |
| 138 | |
Yann Gautier | f3928f6 | 2019-02-14 11:15:03 +0100 | [diff] [blame] | 139 | if (dt_pmic_status() > 0) { |
Yann Gautier | bb836ee | 2018-07-16 17:55:07 +0200 | [diff] [blame] | 140 | initialize_pmic(); |
| 141 | } |
| 142 | |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 143 | ret = stm32mp1_ddr_probe(); |
| 144 | if (ret < 0) { |
| 145 | ERROR("Invalid DDR init: error %d\n", ret); |
| 146 | panic(); |
| 147 | } |
| 148 | |
Yann Gautier | f3bd87e | 2020-09-04 15:55:53 +0200 | [diff] [blame] | 149 | /* Map DDR for binary load, now with cacheable attribute */ |
Yann Gautier | a55169b | 2020-01-10 18:18:59 +0100 | [diff] [blame] | 150 | ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, |
Yann Gautier | f3bd87e | 2020-09-04 15:55:53 +0200 | [diff] [blame] | 151 | STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); |
| 152 | if (ret < 0) { |
| 153 | ERROR("DDR mapping: error %d\n", ret); |
| 154 | panic(); |
| 155 | } |
Yann Gautier | a55169b | 2020-01-10 18:18:59 +0100 | [diff] [blame] | 156 | |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 157 | #if STM32MP_USE_STM32IMAGE |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 158 | #ifdef AARCH32_SP_OPTEE |
| 159 | INFO("BL2 runs OP-TEE setup\n"); |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 160 | #else |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 161 | INFO("BL2 runs SP_MIN setup\n"); |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 162 | #endif |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 163 | #endif /* STM32MP_USE_STM32IMAGE */ |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 164 | } |
| 165 | |
| 166 | void bl2_el3_plat_arch_setup(void) |
| 167 | { |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 168 | int32_t result; |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 169 | struct dt_node_info dt_uart_info; |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 170 | const char *board_model; |
Yann Gautier | 4193466 | 2018-07-20 11:36:05 +0200 | [diff] [blame] | 171 | boot_api_context_t *boot_context = |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 172 | (boot_api_context_t *)stm32mp_get_boot_ctx_address(); |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 173 | uint32_t clk_rate; |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 174 | uintptr_t pwr_base; |
| 175 | uintptr_t rcc_base; |
Yann Gautier | 4193466 | 2018-07-20 11:36:05 +0200 | [diff] [blame] | 176 | |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 177 | mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, |
| 178 | BL_CODE_END - BL_CODE_BASE, |
| 179 | MT_CODE | MT_SECURE); |
| 180 | |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 181 | #if STM32MP_USE_STM32IMAGE |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 182 | #ifdef AARCH32_SP_OPTEE |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 183 | mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, |
| 184 | STM32MP_OPTEE_SIZE, |
| 185 | MT_MEMORY | MT_RW | MT_SECURE); |
Yann Gautier | 90f84d7 | 2021-07-13 14:44:09 +0200 | [diff] [blame] | 186 | #else |
| 187 | /* Prevent corruption of preloaded BL32 */ |
| 188 | mmap_add_region(BL32_BASE, BL32_BASE, |
| 189 | BL32_LIMIT - BL32_BASE, |
| 190 | MT_RO_DATA | MT_SECURE); |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 191 | #endif |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 192 | #endif /* STM32MP_USE_STM32IMAGE */ |
| 193 | |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 194 | /* Prevent corruption of preloaded Device Tree */ |
| 195 | mmap_add_region(DTB_BASE, DTB_BASE, |
| 196 | DTB_LIMIT - DTB_BASE, |
Yann Gautier | 3d33df6 | 2019-12-17 17:11:10 +0100 | [diff] [blame] | 197 | MT_RO_DATA | MT_SECURE); |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 198 | |
| 199 | configure_mmu(); |
| 200 | |
Yann Gautier | 05773eb | 2020-08-24 11:51:50 +0200 | [diff] [blame] | 201 | if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 202 | panic(); |
| 203 | } |
| 204 | |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 205 | pwr_base = stm32mp_pwr_base(); |
| 206 | rcc_base = stm32mp_rcc_base(); |
| 207 | |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 208 | /* |
| 209 | * Disable the backup domain write protection. |
| 210 | * The protection is enable at each reset by hardware |
| 211 | * and must be disabled by software. |
| 212 | */ |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 213 | mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 214 | |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 215 | while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 216 | ; |
| 217 | } |
| 218 | |
Yann Gautier | 3edc7c3 | 2019-05-20 19:17:08 +0200 | [diff] [blame] | 219 | if (bsec_probe() != 0) { |
| 220 | panic(); |
| 221 | } |
| 222 | |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 223 | /* Reset backup domain on cold boot cases */ |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 224 | if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { |
| 225 | mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 226 | |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 227 | while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 228 | 0U) { |
| 229 | ; |
| 230 | } |
| 231 | |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 232 | mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 233 | } |
| 234 | |
Yann Gautier | ed34232 | 2019-02-15 17:33:27 +0100 | [diff] [blame] | 235 | /* Disable MCKPROT */ |
| 236 | mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); |
| 237 | |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 238 | generic_delay_timer_init(); |
| 239 | |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 240 | if (stm32mp1_clk_probe() < 0) { |
| 241 | panic(); |
| 242 | } |
| 243 | |
| 244 | if (stm32mp1_clk_init() < 0) { |
| 245 | panic(); |
| 246 | } |
| 247 | |
Yann Gautier | 3edc7c3 | 2019-05-20 19:17:08 +0200 | [diff] [blame] | 248 | stm32mp1_syscfg_init(); |
| 249 | |
Yann Gautier | 6eef525 | 2021-12-10 17:04:40 +0100 | [diff] [blame] | 250 | stm32_save_boot_interface(boot_context->boot_interface_selected, |
| 251 | boot_context->boot_interface_instance); |
| 252 | |
Yann Gautier | cd16df3 | 2021-06-04 14:04:05 +0200 | [diff] [blame] | 253 | #if STM32MP_USB_PROGRAMMER |
| 254 | /* Deconfigure all UART RX pins configured by ROM code */ |
| 255 | stm32mp1_deconfigure_uart_pins(); |
| 256 | #endif |
| 257 | |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 258 | result = dt_get_stdout_uart_info(&dt_uart_info); |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 259 | |
| 260 | if ((result <= 0) || |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 261 | (dt_uart_info.status == 0U) || |
| 262 | (dt_uart_info.clock < 0) || |
| 263 | (dt_uart_info.reset < 0)) { |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 264 | goto skip_console_init; |
| 265 | } |
| 266 | |
| 267 | if (dt_set_stdout_pinctrl() != 0) { |
| 268 | goto skip_console_init; |
| 269 | } |
| 270 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 271 | stm32mp_clk_enable((unsigned long)dt_uart_info.clock); |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 272 | |
Etienne Carriere | f02647a | 2019-12-08 08:14:40 +0100 | [diff] [blame] | 273 | if (stm32mp_reset_assert((uint32_t)dt_uart_info.reset, |
| 274 | RESET_TIMEOUT_US_1MS) != 0) { |
| 275 | panic(); |
| 276 | } |
| 277 | |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 278 | udelay(2); |
Etienne Carriere | f02647a | 2019-12-08 08:14:40 +0100 | [diff] [blame] | 279 | |
| 280 | if (stm32mp_reset_deassert((uint32_t)dt_uart_info.reset, |
| 281 | RESET_TIMEOUT_US_1MS) != 0) { |
| 282 | panic(); |
| 283 | } |
| 284 | |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 285 | mdelay(1); |
| 286 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 287 | clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock); |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 288 | |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 289 | if (console_stm32_register(dt_uart_info.base, clk_rate, |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 290 | STM32MP_UART_BAUDRATE, &console) == 0) { |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 291 | panic(); |
| 292 | } |
| 293 | |
Andre Przywara | 678c6fa | 2020-01-25 00:58:35 +0000 | [diff] [blame] | 294 | console_set_scope(&console, CONSOLE_FLAG_BOOT | |
Yann Gautier | a30e5f7 | 2019-09-04 11:55:10 +0200 | [diff] [blame] | 295 | CONSOLE_FLAG_CRASH | CONSOLE_FLAG_TRANSLATE_CRLF); |
| 296 | |
Yann Gautier | c737405 | 2019-06-04 18:02:37 +0200 | [diff] [blame] | 297 | stm32mp_print_cpuinfo(); |
| 298 | |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 299 | board_model = dt_get_board_model(); |
| 300 | if (board_model != NULL) { |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 301 | NOTICE("Model: %s\n", board_model); |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 302 | } |
| 303 | |
Yann Gautier | 35dc077 | 2019-05-13 18:34:48 +0200 | [diff] [blame] | 304 | stm32mp_print_boardinfo(); |
| 305 | |
Lionel Debieve | 7bd96f4 | 2019-09-03 12:22:23 +0200 | [diff] [blame] | 306 | if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { |
| 307 | NOTICE("Bootrom authentication %s\n", |
| 308 | (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? |
| 309 | "failed" : "succeeded"); |
| 310 | } |
| 311 | |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 312 | skip_console_init: |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 313 | if (stm32_iwdg_init() < 0) { |
| 314 | panic(); |
| 315 | } |
| 316 | |
| 317 | stm32_iwdg_refresh(); |
| 318 | |
| 319 | result = stm32mp1_dbgmcu_freeze_iwdg2(); |
| 320 | if (result != 0) { |
| 321 | INFO("IWDG2 freeze error : %i\n", result); |
| 322 | } |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 323 | |
Lionel Debieve | 7bd96f4 | 2019-09-03 12:22:23 +0200 | [diff] [blame] | 324 | stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; |
| 325 | stm32mp1_auth_ops.verify_signature = |
| 326 | boot_context->bootrom_ecdsa_verify_signature; |
| 327 | |
| 328 | stm32mp_init_auth(&stm32mp1_auth_ops); |
| 329 | |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 330 | stm32mp1_arch_security_setup(); |
| 331 | |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 332 | print_reset_reason(); |
| 333 | |
Yann Gautier | 29f1f94 | 2021-07-13 18:07:41 +0200 | [diff] [blame] | 334 | #if !STM32MP_USE_STM32IMAGE |
| 335 | fconf_populate("TB_FW", STM32MP_DTB_BASE); |
| 336 | #endif /* !STM32MP_USE_STM32IMAGE */ |
| 337 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 338 | stm32mp_io_setup(); |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 339 | } |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 340 | |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 341 | /******************************************************************************* |
| 342 | * This function can be used by the platforms to update/use image |
| 343 | * information for given `image_id`. |
| 344 | ******************************************************************************/ |
| 345 | int bl2_plat_handle_post_image_load(unsigned int image_id) |
| 346 | { |
| 347 | int err = 0; |
| 348 | bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); |
| 349 | bl_mem_params_node_t *bl32_mem_params; |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 350 | bl_mem_params_node_t *pager_mem_params __unused; |
| 351 | bl_mem_params_node_t *paged_mem_params __unused; |
Yann Gautier | 658775c | 2021-07-06 10:00:44 +0200 | [diff] [blame] | 352 | #if !STM32MP_USE_STM32IMAGE |
| 353 | const struct dyn_cfg_dtb_info_t *config_info; |
| 354 | bl_mem_params_node_t *tos_fw_mem_params; |
| 355 | unsigned int i; |
| 356 | unsigned long long ddr_top __unused; |
| 357 | const unsigned int image_ids[] = { |
| 358 | BL32_IMAGE_ID, |
| 359 | BL33_IMAGE_ID, |
| 360 | HW_CONFIG_ID, |
| 361 | TOS_FW_CONFIG_ID, |
| 362 | }; |
| 363 | #endif /* !STM32MP_USE_STM32IMAGE */ |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 364 | |
| 365 | assert(bl_mem_params != NULL); |
| 366 | |
| 367 | switch (image_id) { |
Yann Gautier | 658775c | 2021-07-06 10:00:44 +0200 | [diff] [blame] | 368 | #if !STM32MP_USE_STM32IMAGE |
| 369 | case FW_CONFIG_ID: |
| 370 | /* Set global DTB info for fixed fw_config information */ |
| 371 | set_config_info(STM32MP_FW_CONFIG_BASE, STM32MP_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID); |
| 372 | fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); |
| 373 | |
| 374 | /* Iterate through all the fw config IDs */ |
| 375 | for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { |
| 376 | bl_mem_params = get_bl_mem_params_node(image_ids[i]); |
| 377 | assert(bl_mem_params != NULL); |
| 378 | |
| 379 | config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); |
| 380 | if (config_info == NULL) { |
| 381 | continue; |
| 382 | } |
| 383 | |
| 384 | bl_mem_params->image_info.image_base = config_info->config_addr; |
| 385 | bl_mem_params->image_info.image_max_size = config_info->config_max_size; |
| 386 | |
| 387 | bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; |
| 388 | |
| 389 | switch (image_ids[i]) { |
| 390 | case BL32_IMAGE_ID: |
| 391 | bl_mem_params->ep_info.pc = config_info->config_addr; |
| 392 | |
| 393 | /* In case of OPTEE, initialize address space with tos_fw addr */ |
| 394 | pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); |
| 395 | pager_mem_params->image_info.image_base = config_info->config_addr; |
| 396 | pager_mem_params->image_info.image_max_size = |
| 397 | config_info->config_max_size; |
| 398 | |
| 399 | /* Init base and size for pager if exist */ |
| 400 | paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); |
| 401 | paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + |
| 402 | (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - |
| 403 | STM32MP_DDR_SHMEM_SIZE); |
| 404 | paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; |
| 405 | break; |
| 406 | |
| 407 | case BL33_IMAGE_ID: |
| 408 | bl_mem_params->ep_info.pc = config_info->config_addr; |
| 409 | break; |
| 410 | |
| 411 | case HW_CONFIG_ID: |
| 412 | case TOS_FW_CONFIG_ID: |
| 413 | break; |
| 414 | |
| 415 | default: |
| 416 | return -EINVAL; |
| 417 | } |
| 418 | } |
| 419 | break; |
| 420 | #endif /* !STM32MP_USE_STM32IMAGE */ |
| 421 | |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 422 | case BL32_IMAGE_ID: |
Yann Gautier | 90f84d7 | 2021-07-13 14:44:09 +0200 | [diff] [blame] | 423 | if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { |
| 424 | /* BL32 is OP-TEE header */ |
| 425 | bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; |
| 426 | pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); |
| 427 | paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); |
| 428 | assert((pager_mem_params != NULL) && (paged_mem_params != NULL)); |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 429 | |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 430 | #if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) |
Yann Gautier | 90f84d7 | 2021-07-13 14:44:09 +0200 | [diff] [blame] | 431 | /* Set OP-TEE extra image load areas at run-time */ |
| 432 | pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; |
| 433 | pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 434 | |
Yann Gautier | 90f84d7 | 2021-07-13 14:44:09 +0200 | [diff] [blame] | 435 | paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + |
| 436 | dt_get_ddr_size() - |
| 437 | STM32MP_DDR_S_SIZE - |
| 438 | STM32MP_DDR_SHMEM_SIZE; |
| 439 | paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 440 | #endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 441 | |
Yann Gautier | 90f84d7 | 2021-07-13 14:44:09 +0200 | [diff] [blame] | 442 | err = parse_optee_header(&bl_mem_params->ep_info, |
| 443 | &pager_mem_params->image_info, |
| 444 | &paged_mem_params->image_info); |
| 445 | if (err) { |
| 446 | ERROR("OPTEE header parse error.\n"); |
| 447 | panic(); |
| 448 | } |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 449 | |
Yann Gautier | 90f84d7 | 2021-07-13 14:44:09 +0200 | [diff] [blame] | 450 | /* Set optee boot info from parsed header data */ |
| 451 | bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base; |
| 452 | bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ |
| 453 | bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 454 | } else { |
| 455 | #if !STM32MP_USE_STM32IMAGE |
| 456 | bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; |
Yann Gautier | 658775c | 2021-07-06 10:00:44 +0200 | [diff] [blame] | 457 | tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID); |
| 458 | bl_mem_params->image_info.image_max_size += |
| 459 | tos_fw_mem_params->image_info.image_max_size; |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 460 | #endif /* !STM32MP_USE_STM32IMAGE */ |
| 461 | bl_mem_params->ep_info.args.arg0 = 0; |
Yann Gautier | 90f84d7 | 2021-07-13 14:44:09 +0200 | [diff] [blame] | 462 | } |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 463 | break; |
| 464 | |
| 465 | case BL33_IMAGE_ID: |
| 466 | bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); |
| 467 | assert(bl32_mem_params != NULL); |
| 468 | bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; |
| 469 | break; |
| 470 | |
| 471 | default: |
| 472 | /* Do nothing in default case */ |
| 473 | break; |
| 474 | } |
| 475 | |
Yann Gautier | a3bd8d1 | 2021-06-18 11:33:26 +0200 | [diff] [blame] | 476 | #if STM32MP_SDMMC || STM32MP_EMMC |
| 477 | /* |
| 478 | * Invalidate remaining data read from MMC but not flushed by load_image_flush(). |
| 479 | * We take the worst case which is 2 MMC blocks. |
| 480 | */ |
| 481 | if ((image_id != FW_CONFIG_ID) && |
| 482 | ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { |
| 483 | inv_dcache_range(bl_mem_params->image_info.image_base + |
| 484 | bl_mem_params->image_info.image_size, |
| 485 | 2U * MMC_BLOCK_SIZE); |
| 486 | } |
| 487 | #endif /* STM32MP_SDMMC || STM32MP_EMMC */ |
| 488 | |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 489 | return err; |
| 490 | } |
Yann Gautier | d2d9b96 | 2021-08-16 11:58:01 +0200 | [diff] [blame] | 491 | |
| 492 | void bl2_el3_plat_prepare_exit(void) |
| 493 | { |
Patrick Delaunay | 9c5ee78 | 2021-07-06 14:07:56 +0200 | [diff] [blame] | 494 | uint16_t boot_itf = stm32mp_get_boot_itf_selected(); |
| 495 | |
| 496 | switch (boot_itf) { |
Patrick Delaunay | e50571b | 2021-10-28 13:48:52 +0200 | [diff] [blame] | 497 | #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER |
| 498 | case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: |
Patrick Delaunay | 9c5ee78 | 2021-07-06 14:07:56 +0200 | [diff] [blame] | 499 | case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: |
| 500 | /* Invalidate the downloaded buffer used with io_memmap */ |
| 501 | inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE); |
| 502 | break; |
Patrick Delaunay | e50571b | 2021-10-28 13:48:52 +0200 | [diff] [blame] | 503 | #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ |
Patrick Delaunay | 9c5ee78 | 2021-07-06 14:07:56 +0200 | [diff] [blame] | 504 | default: |
| 505 | /* Do nothing in default case */ |
| 506 | break; |
| 507 | } |
| 508 | |
Yann Gautier | d2d9b96 | 2021-08-16 11:58:01 +0200 | [diff] [blame] | 509 | stm32mp1_security_setup(); |
| 510 | } |