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Varun Wadekar921b9062015-08-25 17:03:14 +05301/*
Steven Kao0cb8b332018-02-09 20:50:02 +08002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekar1b0c1242018-05-15 11:24:59 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +05304 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar921b9062015-08-25 17:03:14 +05306 */
7
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00008#ifndef TEGRA_DEF_H
9#define TEGRA_DEF_H
Varun Wadekar921b9062015-08-25 17:03:14 +053010
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/utils_def.h>
Varun Wadekar761ca732017-04-24 14:17:12 -070012
Varun Wadekar921b9062015-08-25 17:03:14 +053013/*******************************************************************************
anzhou508d20d2020-07-21 16:22:44 +080014 * Platform BL31 specific defines.
15 ******************************************************************************/
16#define BL31_SIZE U(0x40000)
17
18/*******************************************************************************
Varun Wadekaracf1cad2016-12-12 14:24:17 -080019 * MCE apertures used by the ARI interface
20 *
21 * Aperture 0 - Cpu0 (ARM Cortex A-57)
22 * Aperture 1 - Cpu1 (ARM Cortex A-57)
23 * Aperture 2 - Cpu2 (ARM Cortex A-57)
24 * Aperture 3 - Cpu3 (ARM Cortex A-57)
25 * Aperture 4 - Cpu4 (Denver15)
26 * Aperture 5 - Cpu5 (Denver15)
27 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070028#define MCE_ARI_APERTURE_0_OFFSET U(0x0)
29#define MCE_ARI_APERTURE_1_OFFSET U(0x10000)
30#define MCE_ARI_APERTURE_2_OFFSET U(0x20000)
31#define MCE_ARI_APERTURE_3_OFFSET U(0x30000)
32#define MCE_ARI_APERTURE_4_OFFSET U(0x40000)
33#define MCE_ARI_APERTURE_5_OFFSET U(0x50000)
Varun Wadekaracf1cad2016-12-12 14:24:17 -080034#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET
35
36/* number of apertures */
Varun Wadekar761ca732017-04-24 14:17:12 -070037#define MCE_ARI_APERTURES_MAX U(6)
Varun Wadekaracf1cad2016-12-12 14:24:17 -080038
39/* each ARI aperture is 64KB */
Varun Wadekar761ca732017-04-24 14:17:12 -070040#define MCE_ARI_APERTURE_SIZE U(0x10000)
Varun Wadekaracf1cad2016-12-12 14:24:17 -080041
42/*******************************************************************************
43 * CPU core id macros for the MCE_ONLINE_CORE ARI
44 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070045#define MCE_CORE_ID_MAX U(8)
46#define MCE_CORE_ID_MASK U(0x7)
Varun Wadekaracf1cad2016-12-12 14:24:17 -080047
48/*******************************************************************************
Varun Wadekar42236572016-01-18 19:03:19 -080049 * These values are used by the PSCI implementation during the `CPU_SUSPEND`
50 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
51 * parameter.
52 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070053#define PSTATE_ID_CORE_IDLE U(6)
54#define PSTATE_ID_CORE_POWERDN U(7)
55#define PSTATE_ID_SOC_POWERDN U(2)
Varun Wadekar42236572016-01-18 19:03:19 -080056
57/*******************************************************************************
58 * Platform power states (used by PSCI framework)
59 *
60 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
61 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
Varun Wadekar921b9062015-08-25 17:03:14 +053062 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070063#define PLAT_MAX_RET_STATE U(1)
64#define PLAT_MAX_OFF_STATE U(8)
Varun Wadekar921b9062015-08-25 17:03:14 +053065
66/*******************************************************************************
Steven Kao0cb8b332018-02-09 20:50:02 +080067 * Chip specific page table and MMU setup constants
68 ******************************************************************************/
69#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
70#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
71
72/*******************************************************************************
Varun Wadekarcad7b082015-12-28 18:12:59 -080073 * Secure IRQ definitions
74 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070075#define TEGRA186_TOP_WDT_IRQ U(49)
76#define TEGRA186_AON_WDT_IRQ U(50)
Varun Wadekarcad7b082015-12-28 18:12:59 -080077
Varun Wadekar761ca732017-04-24 14:17:12 -070078#define TEGRA186_SEC_IRQ_TARGET_MASK U(0xF3) /* 4 A57 - 2 Denver */
Varun Wadekarcad7b082015-12-28 18:12:59 -080079
80/*******************************************************************************
Varun Wadekare55c27b2018-09-13 08:47:43 -070081 * Clock identifier for the SE device
82 ******************************************************************************/
83#define TEGRA186_CLK_SE U(103)
84#define TEGRA_CLK_SE TEGRA186_CLK_SE
85
86/*******************************************************************************
Elyes Haouas2be03c02023-02-13 09:14:48 +010087 * Tegra Miscellaneous register constants
Varun Wadekar921b9062015-08-25 17:03:14 +053088 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070089#define TEGRA_MISC_BASE U(0x00100000)
90#define HARDWARE_REVISION_OFFSET U(0x4)
Varun Wadekare2bc7f22016-04-02 15:41:20 -070091
Varun Wadekar761ca732017-04-24 14:17:12 -070092#define MISCREG_PFCFG U(0x200C)
Varun Wadekar921b9062015-08-25 17:03:14 +053093
94/*******************************************************************************
Varun Wadekara0f26972016-03-11 17:18:51 -080095 * Tegra TSA Controller constants
96 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070097#define TEGRA_TSA_BASE U(0x02400000)
Varun Wadekara0f26972016-03-11 17:18:51 -080098
99/*******************************************************************************
Varun Wadekarf5fc53f2016-12-15 11:54:51 -0800100 * TSA configuration registers
101 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700102#define TSA_CONFIG_STATIC0_CSW_SESWR U(0x4010)
103#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET U(0x1100)
104#define TSA_CONFIG_STATIC0_CSW_ETRW U(0x4038)
105#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET U(0x1100)
106#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB U(0x5010)
107#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET U(0x1100)
108#define TSA_CONFIG_STATIC0_CSW_AXISW U(0x7008)
109#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET U(0x1100)
110#define TSA_CONFIG_STATIC0_CSW_HDAW U(0xA008)
111#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET U(0x100)
112#define TSA_CONFIG_STATIC0_CSW_AONDMAW U(0xB018)
113#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET U(0x1100)
114#define TSA_CONFIG_STATIC0_CSW_SCEDMAW U(0xD018)
115#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET U(0x1100)
116#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW U(0xD028)
117#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET U(0x1100)
118#define TSA_CONFIG_STATIC0_CSW_APEDMAW U(0x12018)
119#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET U(0x1100)
120#define TSA_CONFIG_STATIC0_CSW_UFSHCW U(0x13008)
121#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET U(0x1100)
122#define TSA_CONFIG_STATIC0_CSW_AFIW U(0x13018)
123#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET U(0x1100)
124#define TSA_CONFIG_STATIC0_CSW_SATAW U(0x13028)
125#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET U(0x1100)
126#define TSA_CONFIG_STATIC0_CSW_EQOSW U(0x13038)
127#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET U(0x1100)
128#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW U(0x15008)
129#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET U(0x1100)
130#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW U(0x15018)
131#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET U(0x1100)
Varun Wadekarf5fc53f2016-12-15 11:54:51 -0800132
Anthony Zhou0844b972017-06-28 16:35:54 +0800133#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11)
134#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11)
Varun Wadekarf5fc53f2016-12-15 11:54:51 -0800135
136/*******************************************************************************
Varun Wadekaree25e822017-06-28 14:38:19 -0700137 * Tegra General Purpose Centralised DMA constants
138 ******************************************************************************/
Anthony Zhou0e07e452017-07-26 17:16:54 +0800139#define TEGRA_GPCDMA_BASE ULL(0x2610000)
Varun Wadekaree25e822017-06-28 14:38:19 -0700140
141/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530142 * Tegra Memory Controller constants
143 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700144#define TEGRA_MC_STREAMID_BASE U(0x02C00000)
145#define TEGRA_MC_BASE U(0x02C10000)
Varun Wadekar921b9062015-08-25 17:03:14 +0530146
Varun Wadekar153982c2016-12-21 14:50:18 -0800147/* General Security Carveout register macros */
Varun Wadekar761ca732017-04-24 14:17:12 -0700148#define MC_GSC_CONFIG_REGS_SIZE U(0x40)
149#define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1)
Anthony Zhou0844b972017-06-28 16:35:54 +0800150#define MC_GSC_ENABLE_TZ_LOCK_BIT (ULL(1) << 0)
Varun Wadekar761ca732017-04-24 14:17:12 -0700151#define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27)
152#define MC_GSC_BASE_LO_SHIFT U(12)
153#define MC_GSC_BASE_LO_MASK U(0xFFFFF)
154#define MC_GSC_BASE_HI_SHIFT U(0)
155#define MC_GSC_BASE_HI_MASK U(3)
Steven Kaob688d382017-09-06 13:32:21 +0800156#define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31)
Varun Wadekar153982c2016-12-21 14:50:18 -0800157
Varun Wadekar64443ca2016-12-12 16:14:57 -0800158/* TZDRAM carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700159#define MC_SECURITY_CFG0_0 U(0x70)
160#define MC_SECURITY_CFG1_0 U(0x74)
161#define MC_SECURITY_CFG3_0 U(0x9BC)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800162
Harvey Hsiehb7355412017-08-09 16:24:40 +0800163#define MC_SECURITY_BOM_MASK (U(0xFFF) << 20)
164#define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0)
165#define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0)
166
Varun Wadekar64443ca2016-12-12 16:14:57 -0800167/* Video Memory carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700168#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
169#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
170#define MC_VIDEO_PROTECT_SIZE_MB U(0x64C)
Anthony Zhou41eac8a2019-12-04 14:58:23 +0800171#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
172#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
Varun Wadekar153982c2016-12-21 14:50:18 -0800173
174/*
175 * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
176 * non-overlapping Video memory region
177 */
Varun Wadekar761ca732017-04-24 14:17:12 -0700178#define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0)
179#define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4)
180#define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8)
181#define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC)
182#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800183
184/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700185#define MC_TZRAM_CARVEOUT_CFG U(0x2190)
186#define MC_TZRAM_BASE_LO U(0x2194)
187#define MC_TZRAM_BASE_HI U(0x2198)
188#define MC_TZRAM_SIZE U(0x219C)
Steven Kaob688d382017-09-06 13:32:21 +0800189#define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0)
190#define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4)
191#define TZRAM_ALLOW_MPCORER (U(1) << 7)
192#define TZRAM_ALLOW_MPCOREW (U(1) << 25)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800193
Varun Wadekar921b9062015-08-25 17:03:14 +0530194/*******************************************************************************
195 * Tegra UART Controller constants
196 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700197#define TEGRA_UARTA_BASE U(0x03100000)
198#define TEGRA_UARTB_BASE U(0x03110000)
199#define TEGRA_UARTC_BASE U(0x0C280000)
200#define TEGRA_UARTD_BASE U(0x03130000)
201#define TEGRA_UARTE_BASE U(0x03140000)
202#define TEGRA_UARTF_BASE U(0x03150000)
203#define TEGRA_UARTG_BASE U(0x0C290000)
Varun Wadekar921b9062015-08-25 17:03:14 +0530204
205/*******************************************************************************
Varun Wadekar4debe052016-05-18 13:39:16 -0700206 * Tegra Fuse Controller related constants
207 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700208#define TEGRA_FUSE_BASE U(0x03820000)
209#define OPT_SUBREVISION U(0x248)
210#define SUBREVISION_MASK U(0xFF)
Varun Wadekar4debe052016-05-18 13:39:16 -0700211
212/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530213 * GICv2 & interrupt handling related constants
214 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700215#define TEGRA_GICD_BASE U(0x03881000)
216#define TEGRA_GICC_BASE U(0x03882000)
Varun Wadekar921b9062015-08-25 17:03:14 +0530217
218/*******************************************************************************
Varun Wadekarb8776152016-03-03 13:52:52 -0800219 * Security Engine related constants
220 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700221#define TEGRA_SE0_BASE U(0x03AC0000)
222#define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C)
223#define TEGRA_PKA1_BASE U(0x03AD0000)
224#define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144)
225#define TEGRA_RNG1_BASE U(0x03AE0000)
226#define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0)
Varun Wadekarb8776152016-03-03 13:52:52 -0800227
228/*******************************************************************************
Jeetesh Burman29e03be2018-05-31 14:15:30 +0530229 * Tegra HSP doorbell #0 constants
230 ******************************************************************************/
231#define TEGRA_HSP_DBELL_BASE U(0x03C90000)
232#define HSP_DBELL_1_ENABLE U(0x104)
233#define HSP_DBELL_3_TRIGGER U(0x300)
234#define HSP_DBELL_3_ENABLE U(0x304)
235
236/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530237 * Tegra Clock and Reset Controller constants
238 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700239#define TEGRA_CAR_RESET_BASE U(0x05000000)
Varun Wadekara59a7c52017-04-26 08:31:50 -0700240#define TEGRA_GPU_RESET_REG_OFFSET U(0x30)
Jeetesh Burman48fef882018-01-22 15:40:08 +0530241#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x34)
Varun Wadekara59a7c52017-04-26 08:31:50 -0700242#define GPU_RESET_BIT (U(1) << 0)
Jeetesh Burman48fef882018-01-22 15:40:08 +0530243#define GPU_SET_BIT (U(1) << 0)
Varun Wadekaree25e822017-06-28 14:38:19 -0700244#define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004)
245#define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008)
Varun Wadekar921b9062015-08-25 17:03:14 +0530246
247/*******************************************************************************
248 * Tegra micro-seconds timer constants
249 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700250#define TEGRA_TMRUS_BASE U(0x0C2E0000)
251#define TEGRA_TMRUS_SIZE U(0x1000)
Varun Wadekar921b9062015-08-25 17:03:14 +0530252
253/*******************************************************************************
254 * Tegra Power Mgmt Controller constants
255 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700256#define TEGRA_PMC_BASE U(0x0C360000)
Varun Wadekar921b9062015-08-25 17:03:14 +0530257
258/*******************************************************************************
259 * Tegra scratch registers constants
260 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700261#define TEGRA_SCRATCH_BASE U(0x0C390000)
Jeetesh Burman50cd1062018-07-19 13:07:23 +0530262#define SECURE_SCRATCH_RSV0_HI U(0x654)
Varun Wadekar761ca732017-04-24 14:17:12 -0700263#define SECURE_SCRATCH_RSV1_LO U(0x658)
264#define SECURE_SCRATCH_RSV1_HI U(0x65C)
265#define SECURE_SCRATCH_RSV6 U(0x680)
266#define SECURE_SCRATCH_RSV11_LO U(0x6A8)
267#define SECURE_SCRATCH_RSV11_HI U(0x6AC)
268#define SECURE_SCRATCH_RSV53_LO U(0x7F8)
269#define SECURE_SCRATCH_RSV53_HI U(0x7FC)
Varun Wadekar761ca732017-04-24 14:17:12 -0700270#define SECURE_SCRATCH_RSV55_LO U(0x808)
271#define SECURE_SCRATCH_RSV55_HI U(0x80C)
Jeetesh Burman50cd1062018-07-19 13:07:23 +0530272#define SECURE_SCRATCH_RSV63_LO U(0x848)
273#define SECURE_SCRATCH_RSV63_HI U(0x84C)
274#define SECURE_SCRATCH_RSV64_LO U(0x850)
275#define SECURE_SCRATCH_RSV64_HI U(0x854)
276#define SECURE_SCRATCH_RSV65_LO U(0x858)
277#define SECURE_SCRATCH_RSV65_HI U(0x85c)
278#define SECURE_SCRATCH_RSV66_LO U(0x860)
279#define SECURE_SCRATCH_RSV66_HI U(0x864)
280#define SECURE_SCRATCH_RSV68_LO U(0x870)
Varun Wadekar921b9062015-08-25 17:03:14 +0530281
Steven Kao186485e2017-10-23 18:22:09 +0800282#define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV1_LO
283#define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV1_HI
284#define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV6
Pritesh Raithatha75c94432018-08-03 15:48:15 +0530285#define SCRATCH_MC_TABLE_ADDR_LO SECURE_SCRATCH_RSV11_LO
286#define SCRATCH_MC_TABLE_ADDR_HI SECURE_SCRATCH_RSV11_HI
Steven Kao186485e2017-10-23 18:22:09 +0800287#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV53_LO
288#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV53_HI
289#define SCRATCH_TZDRAM_ADDR_LO SECURE_SCRATCH_RSV55_LO
290#define SCRATCH_TZDRAM_ADDR_HI SECURE_SCRATCH_RSV55_HI
291
Varun Wadekar921b9062015-08-25 17:03:14 +0530292/*******************************************************************************
Varun Wadekard64db962016-09-23 14:28:16 -0700293 * Tegra Memory Mapped Control Register Access constants
Varun Wadekar921b9062015-08-25 17:03:14 +0530294 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700295#define TEGRA_MMCRAB_BASE U(0x0E000000)
Varun Wadekar921b9062015-08-25 17:03:14 +0530296
297/*******************************************************************************
Varun Wadekard64db962016-09-23 14:28:16 -0700298 * Tegra Memory Mapped Activity Monitor Register Access constants
299 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700300#define TEGRA_ARM_ACTMON_CTR_BASE U(0x0E060000)
301#define TEGRA_DENVER_ACTMON_CTR_BASE U(0x0E070000)
Varun Wadekard64db962016-09-23 14:28:16 -0700302
303/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530304 * Tegra SMMU Controller constants
305 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700306#define TEGRA_SMMU0_BASE U(0x12000000)
Varun Wadekar921b9062015-08-25 17:03:14 +0530307
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800308/*******************************************************************************
309 * Tegra TZRAM constants
310 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700311#define TEGRA_TZRAM_BASE U(0x30000000)
312#define TEGRA_TZRAM_SIZE U(0x40000)
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800313
Varun Wadekar1b0c1242018-05-15 11:24:59 -0700314/*******************************************************************************
Jeetesh Burman29e03be2018-05-31 14:15:30 +0530315 * Tegra CCPLEX-BPMP IPC constants
316 ******************************************************************************/
317#define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x3004C000)
318#define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x3004D000)
319#define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */
320
321/*******************************************************************************
Varun Wadekar1b0c1242018-05-15 11:24:59 -0700322 * Tegra DRAM memory base address
323 ******************************************************************************/
324#define TEGRA_DRAM_BASE ULL(0x80000000)
325#define TEGRA_DRAM_END ULL(0x27FFFFFFF)
326
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000327#endif /* TEGRA_DEF_H */