Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 1 | /* |
Steven Kao | 0cb8b33 | 2018-02-09 20:50:02 +0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 1b0c124 | 2018-05-15 11:24:59 -0700 | [diff] [blame] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 8 | #ifndef TEGRA_DEF_H |
| 9 | #define TEGRA_DEF_H |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 10 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <lib/utils_def.h> |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 12 | |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 13 | /******************************************************************************* |
Varun Wadekar | acf1cad | 2016-12-12 14:24:17 -0800 | [diff] [blame] | 14 | * MCE apertures used by the ARI interface |
| 15 | * |
| 16 | * Aperture 0 - Cpu0 (ARM Cortex A-57) |
| 17 | * Aperture 1 - Cpu1 (ARM Cortex A-57) |
| 18 | * Aperture 2 - Cpu2 (ARM Cortex A-57) |
| 19 | * Aperture 3 - Cpu3 (ARM Cortex A-57) |
| 20 | * Aperture 4 - Cpu4 (Denver15) |
| 21 | * Aperture 5 - Cpu5 (Denver15) |
| 22 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 23 | #define MCE_ARI_APERTURE_0_OFFSET U(0x0) |
| 24 | #define MCE_ARI_APERTURE_1_OFFSET U(0x10000) |
| 25 | #define MCE_ARI_APERTURE_2_OFFSET U(0x20000) |
| 26 | #define MCE_ARI_APERTURE_3_OFFSET U(0x30000) |
| 27 | #define MCE_ARI_APERTURE_4_OFFSET U(0x40000) |
| 28 | #define MCE_ARI_APERTURE_5_OFFSET U(0x50000) |
Varun Wadekar | acf1cad | 2016-12-12 14:24:17 -0800 | [diff] [blame] | 29 | #define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET |
| 30 | |
| 31 | /* number of apertures */ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 32 | #define MCE_ARI_APERTURES_MAX U(6) |
Varun Wadekar | acf1cad | 2016-12-12 14:24:17 -0800 | [diff] [blame] | 33 | |
| 34 | /* each ARI aperture is 64KB */ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 35 | #define MCE_ARI_APERTURE_SIZE U(0x10000) |
Varun Wadekar | acf1cad | 2016-12-12 14:24:17 -0800 | [diff] [blame] | 36 | |
| 37 | /******************************************************************************* |
| 38 | * CPU core id macros for the MCE_ONLINE_CORE ARI |
| 39 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 40 | #define MCE_CORE_ID_MAX U(8) |
| 41 | #define MCE_CORE_ID_MASK U(0x7) |
Varun Wadekar | acf1cad | 2016-12-12 14:24:17 -0800 | [diff] [blame] | 42 | |
| 43 | /******************************************************************************* |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 44 | * These values are used by the PSCI implementation during the `CPU_SUSPEND` |
| 45 | * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' |
| 46 | * parameter. |
| 47 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 48 | #define PSTATE_ID_CORE_IDLE U(6) |
| 49 | #define PSTATE_ID_CORE_POWERDN U(7) |
| 50 | #define PSTATE_ID_SOC_POWERDN U(2) |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 51 | |
| 52 | /******************************************************************************* |
| 53 | * Platform power states (used by PSCI framework) |
| 54 | * |
| 55 | * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID |
| 56 | * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 57 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 58 | #define PLAT_MAX_RET_STATE U(1) |
| 59 | #define PLAT_MAX_OFF_STATE U(8) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 60 | |
| 61 | /******************************************************************************* |
Steven Kao | 0cb8b33 | 2018-02-09 20:50:02 +0800 | [diff] [blame] | 62 | * Chip specific page table and MMU setup constants |
| 63 | ******************************************************************************/ |
| 64 | #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) |
| 65 | #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) |
| 66 | |
| 67 | /******************************************************************************* |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 68 | * Secure IRQ definitions |
| 69 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 70 | #define TEGRA186_TOP_WDT_IRQ U(49) |
| 71 | #define TEGRA186_AON_WDT_IRQ U(50) |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 72 | |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 73 | #define TEGRA186_SEC_IRQ_TARGET_MASK U(0xF3) /* 4 A57 - 2 Denver */ |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 74 | |
| 75 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 76 | * Tegra Miscellanous register constants |
| 77 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 78 | #define TEGRA_MISC_BASE U(0x00100000) |
| 79 | #define HARDWARE_REVISION_OFFSET U(0x4) |
Varun Wadekar | e2bc7f2 | 2016-04-02 15:41:20 -0700 | [diff] [blame] | 80 | |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 81 | #define MISCREG_PFCFG U(0x200C) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 82 | |
| 83 | /******************************************************************************* |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 84 | * Tegra TSA Controller constants |
| 85 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 86 | #define TEGRA_TSA_BASE U(0x02400000) |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 87 | |
| 88 | /******************************************************************************* |
Varun Wadekar | f5fc53f | 2016-12-15 11:54:51 -0800 | [diff] [blame] | 89 | * TSA configuration registers |
| 90 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 91 | #define TSA_CONFIG_STATIC0_CSW_SESWR U(0x4010) |
| 92 | #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET U(0x1100) |
| 93 | #define TSA_CONFIG_STATIC0_CSW_ETRW U(0x4038) |
| 94 | #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET U(0x1100) |
| 95 | #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB U(0x5010) |
| 96 | #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET U(0x1100) |
| 97 | #define TSA_CONFIG_STATIC0_CSW_AXISW U(0x7008) |
| 98 | #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET U(0x1100) |
| 99 | #define TSA_CONFIG_STATIC0_CSW_HDAW U(0xA008) |
| 100 | #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET U(0x100) |
| 101 | #define TSA_CONFIG_STATIC0_CSW_AONDMAW U(0xB018) |
| 102 | #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET U(0x1100) |
| 103 | #define TSA_CONFIG_STATIC0_CSW_SCEDMAW U(0xD018) |
| 104 | #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET U(0x1100) |
| 105 | #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW U(0xD028) |
| 106 | #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET U(0x1100) |
| 107 | #define TSA_CONFIG_STATIC0_CSW_APEDMAW U(0x12018) |
| 108 | #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET U(0x1100) |
| 109 | #define TSA_CONFIG_STATIC0_CSW_UFSHCW U(0x13008) |
| 110 | #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET U(0x1100) |
| 111 | #define TSA_CONFIG_STATIC0_CSW_AFIW U(0x13018) |
| 112 | #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET U(0x1100) |
| 113 | #define TSA_CONFIG_STATIC0_CSW_SATAW U(0x13028) |
| 114 | #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET U(0x1100) |
| 115 | #define TSA_CONFIG_STATIC0_CSW_EQOSW U(0x13038) |
| 116 | #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET U(0x1100) |
| 117 | #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW U(0x15008) |
| 118 | #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET U(0x1100) |
| 119 | #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW U(0x15018) |
| 120 | #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET U(0x1100) |
Varun Wadekar | f5fc53f | 2016-12-15 11:54:51 -0800 | [diff] [blame] | 121 | |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 122 | #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11) |
| 123 | #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11) |
Varun Wadekar | f5fc53f | 2016-12-15 11:54:51 -0800 | [diff] [blame] | 124 | |
| 125 | /******************************************************************************* |
Varun Wadekar | ee25e82 | 2017-06-28 14:38:19 -0700 | [diff] [blame] | 126 | * Tegra General Purpose Centralised DMA constants |
| 127 | ******************************************************************************/ |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 128 | #define TEGRA_GPCDMA_BASE ULL(0x2610000) |
Varun Wadekar | ee25e82 | 2017-06-28 14:38:19 -0700 | [diff] [blame] | 129 | |
| 130 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 131 | * Tegra Memory Controller constants |
| 132 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 133 | #define TEGRA_MC_STREAMID_BASE U(0x02C00000) |
| 134 | #define TEGRA_MC_BASE U(0x02C10000) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 135 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 136 | /* General Security Carveout register macros */ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 137 | #define MC_GSC_CONFIG_REGS_SIZE U(0x40) |
| 138 | #define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1) |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 139 | #define MC_GSC_ENABLE_TZ_LOCK_BIT (ULL(1) << 0) |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 140 | #define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27) |
| 141 | #define MC_GSC_BASE_LO_SHIFT U(12) |
| 142 | #define MC_GSC_BASE_LO_MASK U(0xFFFFF) |
| 143 | #define MC_GSC_BASE_HI_SHIFT U(0) |
| 144 | #define MC_GSC_BASE_HI_MASK U(3) |
Steven Kao | b688d38 | 2017-09-06 13:32:21 +0800 | [diff] [blame] | 145 | #define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31) |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 146 | |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 147 | /* TZDRAM carveout configuration registers */ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 148 | #define MC_SECURITY_CFG0_0 U(0x70) |
| 149 | #define MC_SECURITY_CFG1_0 U(0x74) |
| 150 | #define MC_SECURITY_CFG3_0 U(0x9BC) |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 151 | |
Harvey Hsieh | b735541 | 2017-08-09 16:24:40 +0800 | [diff] [blame] | 152 | #define MC_SECURITY_BOM_MASK (U(0xFFF) << 20) |
| 153 | #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) |
| 154 | #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) |
| 155 | |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 156 | /* Video Memory carveout configuration registers */ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 157 | #define MC_VIDEO_PROTECT_BASE_HI U(0x978) |
| 158 | #define MC_VIDEO_PROTECT_BASE_LO U(0x648) |
| 159 | #define MC_VIDEO_PROTECT_SIZE_MB U(0x64C) |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 160 | |
| 161 | /* |
| 162 | * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the |
| 163 | * non-overlapping Video memory region |
| 164 | */ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 165 | #define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0) |
| 166 | #define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4) |
| 167 | #define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8) |
| 168 | #define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC) |
| 169 | #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0) |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 170 | |
| 171 | /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 172 | #define MC_TZRAM_CARVEOUT_CFG U(0x2190) |
| 173 | #define MC_TZRAM_BASE_LO U(0x2194) |
| 174 | #define MC_TZRAM_BASE_HI U(0x2198) |
| 175 | #define MC_TZRAM_SIZE U(0x219C) |
Steven Kao | b688d38 | 2017-09-06 13:32:21 +0800 | [diff] [blame] | 176 | #define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0) |
| 177 | #define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4) |
| 178 | #define TZRAM_ALLOW_MPCORER (U(1) << 7) |
| 179 | #define TZRAM_ALLOW_MPCOREW (U(1) << 25) |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 180 | |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 181 | /******************************************************************************* |
| 182 | * Tegra UART Controller constants |
| 183 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 184 | #define TEGRA_UARTA_BASE U(0x03100000) |
| 185 | #define TEGRA_UARTB_BASE U(0x03110000) |
| 186 | #define TEGRA_UARTC_BASE U(0x0C280000) |
| 187 | #define TEGRA_UARTD_BASE U(0x03130000) |
| 188 | #define TEGRA_UARTE_BASE U(0x03140000) |
| 189 | #define TEGRA_UARTF_BASE U(0x03150000) |
| 190 | #define TEGRA_UARTG_BASE U(0x0C290000) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 191 | |
| 192 | /******************************************************************************* |
Varun Wadekar | 4debe05 | 2016-05-18 13:39:16 -0700 | [diff] [blame] | 193 | * Tegra Fuse Controller related constants |
| 194 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 195 | #define TEGRA_FUSE_BASE U(0x03820000) |
| 196 | #define OPT_SUBREVISION U(0x248) |
| 197 | #define SUBREVISION_MASK U(0xFF) |
Varun Wadekar | 4debe05 | 2016-05-18 13:39:16 -0700 | [diff] [blame] | 198 | |
| 199 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 200 | * GICv2 & interrupt handling related constants |
| 201 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 202 | #define TEGRA_GICD_BASE U(0x03881000) |
| 203 | #define TEGRA_GICC_BASE U(0x03882000) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 204 | |
| 205 | /******************************************************************************* |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 206 | * Security Engine related constants |
| 207 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 208 | #define TEGRA_SE0_BASE U(0x03AC0000) |
| 209 | #define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C) |
| 210 | #define TEGRA_PKA1_BASE U(0x03AD0000) |
| 211 | #define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144) |
| 212 | #define TEGRA_RNG1_BASE U(0x03AE0000) |
| 213 | #define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 214 | |
| 215 | /******************************************************************************* |
Jeetesh Burman | 29e03be | 2018-05-31 14:15:30 +0530 | [diff] [blame] | 216 | * Tegra HSP doorbell #0 constants |
| 217 | ******************************************************************************/ |
| 218 | #define TEGRA_HSP_DBELL_BASE U(0x03C90000) |
| 219 | #define HSP_DBELL_1_ENABLE U(0x104) |
| 220 | #define HSP_DBELL_3_TRIGGER U(0x300) |
| 221 | #define HSP_DBELL_3_ENABLE U(0x304) |
| 222 | |
| 223 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 224 | * Tegra Clock and Reset Controller constants |
| 225 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 226 | #define TEGRA_CAR_RESET_BASE U(0x05000000) |
Varun Wadekar | a59a7c5 | 2017-04-26 08:31:50 -0700 | [diff] [blame] | 227 | #define TEGRA_GPU_RESET_REG_OFFSET U(0x30) |
Jeetesh Burman | 48fef88 | 2018-01-22 15:40:08 +0530 | [diff] [blame] | 228 | #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x34) |
Varun Wadekar | a59a7c5 | 2017-04-26 08:31:50 -0700 | [diff] [blame] | 229 | #define GPU_RESET_BIT (U(1) << 0) |
Jeetesh Burman | 48fef88 | 2018-01-22 15:40:08 +0530 | [diff] [blame] | 230 | #define GPU_SET_BIT (U(1) << 0) |
Varun Wadekar | ee25e82 | 2017-06-28 14:38:19 -0700 | [diff] [blame] | 231 | #define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004) |
| 232 | #define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 233 | |
| 234 | /******************************************************************************* |
| 235 | * Tegra micro-seconds timer constants |
| 236 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 237 | #define TEGRA_TMRUS_BASE U(0x0C2E0000) |
| 238 | #define TEGRA_TMRUS_SIZE U(0x1000) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 239 | |
| 240 | /******************************************************************************* |
| 241 | * Tegra Power Mgmt Controller constants |
| 242 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 243 | #define TEGRA_PMC_BASE U(0x0C360000) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 244 | |
| 245 | /******************************************************************************* |
| 246 | * Tegra scratch registers constants |
| 247 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 248 | #define TEGRA_SCRATCH_BASE U(0x0C390000) |
Jeetesh Burman | 50cd106 | 2018-07-19 13:07:23 +0530 | [diff] [blame^] | 249 | #define SECURE_SCRATCH_RSV0_HI U(0x654) |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 250 | #define SECURE_SCRATCH_RSV1_LO U(0x658) |
| 251 | #define SECURE_SCRATCH_RSV1_HI U(0x65C) |
| 252 | #define SECURE_SCRATCH_RSV6 U(0x680) |
| 253 | #define SECURE_SCRATCH_RSV11_LO U(0x6A8) |
| 254 | #define SECURE_SCRATCH_RSV11_HI U(0x6AC) |
| 255 | #define SECURE_SCRATCH_RSV53_LO U(0x7F8) |
| 256 | #define SECURE_SCRATCH_RSV53_HI U(0x7FC) |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 257 | #define SECURE_SCRATCH_RSV55_LO U(0x808) |
| 258 | #define SECURE_SCRATCH_RSV55_HI U(0x80C) |
Jeetesh Burman | 50cd106 | 2018-07-19 13:07:23 +0530 | [diff] [blame^] | 259 | #define SECURE_SCRATCH_RSV63_LO U(0x848) |
| 260 | #define SECURE_SCRATCH_RSV63_HI U(0x84C) |
| 261 | #define SECURE_SCRATCH_RSV64_LO U(0x850) |
| 262 | #define SECURE_SCRATCH_RSV64_HI U(0x854) |
| 263 | #define SECURE_SCRATCH_RSV65_LO U(0x858) |
| 264 | #define SECURE_SCRATCH_RSV65_HI U(0x85c) |
| 265 | #define SECURE_SCRATCH_RSV66_LO U(0x860) |
| 266 | #define SECURE_SCRATCH_RSV66_HI U(0x864) |
| 267 | #define SECURE_SCRATCH_RSV68_LO U(0x870) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 268 | |
Steven Kao | 186485e | 2017-10-23 18:22:09 +0800 | [diff] [blame] | 269 | #define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV1_LO |
| 270 | #define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV1_HI |
| 271 | #define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV6 |
| 272 | #define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV11_LO |
| 273 | #define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV11_HI |
| 274 | #define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV53_LO |
| 275 | #define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV53_HI |
| 276 | #define SCRATCH_TZDRAM_ADDR_LO SECURE_SCRATCH_RSV55_LO |
| 277 | #define SCRATCH_TZDRAM_ADDR_HI SECURE_SCRATCH_RSV55_HI |
| 278 | |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 279 | /******************************************************************************* |
Varun Wadekar | d64db96 | 2016-09-23 14:28:16 -0700 | [diff] [blame] | 280 | * Tegra Memory Mapped Control Register Access constants |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 281 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 282 | #define TEGRA_MMCRAB_BASE U(0x0E000000) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 283 | |
| 284 | /******************************************************************************* |
Varun Wadekar | d64db96 | 2016-09-23 14:28:16 -0700 | [diff] [blame] | 285 | * Tegra Memory Mapped Activity Monitor Register Access constants |
| 286 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 287 | #define TEGRA_ARM_ACTMON_CTR_BASE U(0x0E060000) |
| 288 | #define TEGRA_DENVER_ACTMON_CTR_BASE U(0x0E070000) |
Varun Wadekar | d64db96 | 2016-09-23 14:28:16 -0700 | [diff] [blame] | 289 | |
| 290 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 291 | * Tegra SMMU Controller constants |
| 292 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 293 | #define TEGRA_SMMU0_BASE U(0x12000000) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 294 | |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 295 | /******************************************************************************* |
| 296 | * Tegra TZRAM constants |
| 297 | ******************************************************************************/ |
Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 298 | #define TEGRA_TZRAM_BASE U(0x30000000) |
| 299 | #define TEGRA_TZRAM_SIZE U(0x40000) |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 300 | |
Varun Wadekar | 1b0c124 | 2018-05-15 11:24:59 -0700 | [diff] [blame] | 301 | /******************************************************************************* |
Jeetesh Burman | 29e03be | 2018-05-31 14:15:30 +0530 | [diff] [blame] | 302 | * Tegra CCPLEX-BPMP IPC constants |
| 303 | ******************************************************************************/ |
| 304 | #define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x3004C000) |
| 305 | #define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x3004D000) |
| 306 | #define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */ |
| 307 | |
| 308 | /******************************************************************************* |
Varun Wadekar | 1b0c124 | 2018-05-15 11:24:59 -0700 | [diff] [blame] | 309 | * Tegra DRAM memory base address |
| 310 | ******************************************************************************/ |
| 311 | #define TEGRA_DRAM_BASE ULL(0x80000000) |
| 312 | #define TEGRA_DRAM_END ULL(0x27FFFFFFF) |
| 313 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 314 | #endif /* TEGRA_DEF_H */ |