Tegra186: read activity monitor's clock counter values
This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requires this information to calculate the CPU's frequency.
Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq"
The following CPU registers have to be set by the non-secure driver
before issuing the SMC:
X1 = MPIDR of the target core
X2 = MIDR of the target core
Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index 4c99a7b..f919ac3 100644
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -261,11 +261,17 @@
#define SECURE_SCRATCH_RSV55_HI 0x80C
/*******************************************************************************
- * Tegra Memory Mapped Control Register Access Bus constants
+ * Tegra Memory Mapped Control Register Access constants
******************************************************************************/
#define TEGRA_MMCRAB_BASE 0x0E000000
/*******************************************************************************
+ * Tegra Memory Mapped Activity Monitor Register Access constants
+ ******************************************************************************/
+#define TEGRA_ARM_ACTMON_CTR_BASE 0x0E060000
+#define TEGRA_DENVER_ACTMON_CTR_BASE 0x0E070000
+
+/*******************************************************************************
* Tegra SMMU Controller constants
******************************************************************************/
#define TEGRA_SMMU_BASE 0x12000000