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git01.mediatek.com / filogic / atf / acf1cadffa6dca7efb984afb914369eb7cf4def0 / . / plat / nvidia / tegra / include / t186 / tegra_def.h
blob: b5a8ab38d327cf95307f2b84ea2e80ccaccd69fe [file] [log] [blame]
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]1/*
Varun Wadekarcad7b082015-12-28 18:12:59 -0800[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __TEGRA_DEF_H__
32#define __TEGRA_DEF_H__
33
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]34/*******************************************************************************
Varun Wadekaracf1cad2016-12-12 14:24:17 -0800[diff] [blame^]35 * MCE apertures used by the ARI interface
36 *
37 * Aperture 0 - Cpu0 (ARM Cortex A-57)
38 * Aperture 1 - Cpu1 (ARM Cortex A-57)
39 * Aperture 2 - Cpu2 (ARM Cortex A-57)
40 * Aperture 3 - Cpu3 (ARM Cortex A-57)
41 * Aperture 4 - Cpu4 (Denver15)
42 * Aperture 5 - Cpu5 (Denver15)
43 ******************************************************************************/
44#define MCE_ARI_APERTURE_0_OFFSET 0x0
45#define MCE_ARI_APERTURE_1_OFFSET 0x10000
46#define MCE_ARI_APERTURE_2_OFFSET 0x20000
47#define MCE_ARI_APERTURE_3_OFFSET 0x30000
48#define MCE_ARI_APERTURE_4_OFFSET 0x40000
49#define MCE_ARI_APERTURE_5_OFFSET 0x50000
50#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET
51
52/* number of apertures */
53#define MCE_ARI_APERTURES_MAX 6
54
55/* each ARI aperture is 64KB */
56#define MCE_ARI_APERTURE_SIZE 0x10000
57
58/*******************************************************************************
59 * CPU core id macros for the MCE_ONLINE_CORE ARI
60 ******************************************************************************/
61#define MCE_CORE_ID_MAX 8
62#define MCE_CORE_ID_MASK 0x7
63
64/*******************************************************************************
Varun Wadekar42236572016-01-18 19:03:19 -0800[diff] [blame]65 * These values are used by the PSCI implementation during the `CPU_SUSPEND`
66 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
67 * parameter.
68 ******************************************************************************/
69#define PSTATE_ID_CORE_IDLE 6
70#define PSTATE_ID_CORE_POWERDN 7
71#define PSTATE_ID_SOC_POWERDN 2
72
73/*******************************************************************************
74 * Platform power states (used by PSCI framework)
75 *
76 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
77 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]78 ******************************************************************************/
Varun Wadekar42236572016-01-18 19:03:19 -0800[diff] [blame]79#define PLAT_MAX_RET_STATE 1
80#define PLAT_MAX_OFF_STATE 8
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]81
82/*******************************************************************************
83 * Implementation defined ACTLR_EL3 bit definitions
84 ******************************************************************************/
85#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
86#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
87#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
88#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
89#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
90#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
91 ACTLR_EL3_L2ECTLR_BIT | \
92 ACTLR_EL3_L2CTLR_BIT | \
93 ACTLR_EL3_CPUECTLR_BIT | \
94 ACTLR_EL3_CPUACTLR_BIT)
95
96/*******************************************************************************
Varun Wadekarcad7b082015-12-28 18:12:59 -0800[diff] [blame]97 * Secure IRQ definitions
98 ******************************************************************************/
99#define TEGRA186_TOP_WDT_IRQ 49
100#define TEGRA186_AON_WDT_IRQ 50
101
102#define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */
103
104/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]105 * Tegra Miscellanous register constants
106 ******************************************************************************/
107#define TEGRA_MISC_BASE 0x00100000
Varun Wadekarc9ac3e42016-02-17 15:07:49 -0800[diff] [blame]108#define HARDWARE_REVISION_OFFSET 0x4
Varun Wadekare2bc7f22016-04-02 15:41:20 -0700[diff] [blame]109
Varun Wadekarb8776152016-03-03 13:52:52 -0800[diff] [blame]110#define MISCREG_PFCFG 0x200C
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]111
112/*******************************************************************************
Varun Wadekara0f26972016-03-11 17:18:51 -0800[diff] [blame]113 * Tegra TSA Controller constants
114 ******************************************************************************/
115#define TEGRA_TSA_BASE 0x02400000
116
117/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]118 * Tegra Memory Controller constants
119 ******************************************************************************/
120#define TEGRA_MC_STREAMID_BASE 0x02C00000
121#define TEGRA_MC_BASE 0x02C10000
122
123/*******************************************************************************
124 * Tegra UART Controller constants
125 ******************************************************************************/
126#define TEGRA_UARTA_BASE 0x03100000
127#define TEGRA_UARTB_BASE 0x03110000
128#define TEGRA_UARTC_BASE 0x0C280000
129#define TEGRA_UARTD_BASE 0x03130000
130#define TEGRA_UARTE_BASE 0x03140000
131#define TEGRA_UARTF_BASE 0x03150000
132#define TEGRA_UARTG_BASE 0x0C290000
133
134/*******************************************************************************
Varun Wadekar4debe052016-05-18 13:39:16 -0700[diff] [blame]135 * Tegra Fuse Controller related constants
136 ******************************************************************************/
137#define TEGRA_FUSE_BASE 0x03820000
138#define OPT_SUBREVISION 0x248
139#define SUBREVISION_MASK 0xFF
140
141/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]142 * GICv2 & interrupt handling related constants
143 ******************************************************************************/
144#define TEGRA_GICD_BASE 0x03881000
145#define TEGRA_GICC_BASE 0x03882000
146
147/*******************************************************************************
Varun Wadekarb8776152016-03-03 13:52:52 -0800[diff] [blame]148 * Security Engine related constants
149 ******************************************************************************/
150#define TEGRA_SE0_BASE 0x03AC0000
151#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C
152#define TEGRA_PKA1_BASE 0x03AD0000
153#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144
154#define TEGRA_RNG1_BASE 0x03AE0000
155#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0
156
157/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]158 * Tegra Clock and Reset Controller constants
159 ******************************************************************************/
160#define TEGRA_CAR_RESET_BASE 0x05000000
161
162/*******************************************************************************
163 * Tegra micro-seconds timer constants
164 ******************************************************************************/
165#define TEGRA_TMRUS_BASE 0x0C2E0000
166
167/*******************************************************************************
168 * Tegra Power Mgmt Controller constants
169 ******************************************************************************/
170#define TEGRA_PMC_BASE 0x0C360000
171
172/*******************************************************************************
173 * Tegra scratch registers constants
174 ******************************************************************************/
175#define TEGRA_SCRATCH_BASE 0x0C390000
Varun Wadekarb8776152016-03-03 13:52:52 -0800[diff] [blame]176#define SECURE_SCRATCH_RSV6 0x680
177#define SECURE_SCRATCH_RSV11_LO 0x6A8
178#define SECURE_SCRATCH_RSV11_HI 0x6AC
Varun Wadekar94701ff2016-05-23 11:47:34 -0700[diff] [blame]179#define SECURE_SCRATCH_RSV53_LO 0x7F8
180#define SECURE_SCRATCH_RSV53_HI 0x7FC
Harvey Hsiehc95802d2016-07-29 20:10:59 +0800[diff] [blame]181#define SECURE_SCRATCH_RSV54_HI 0x804
182#define SECURE_SCRATCH_RSV55_LO 0x808
183#define SECURE_SCRATCH_RSV55_HI 0x80C
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]184
185/*******************************************************************************
186 * Tegra Memory Mapped Control Register Access Bus constants
187 ******************************************************************************/
188#define TEGRA_MMCRAB_BASE 0x0E000000
189
190/*******************************************************************************
191 * Tegra SMMU Controller constants
192 ******************************************************************************/
193#define TEGRA_SMMU_BASE 0x12000000
194
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800[diff] [blame]195/*******************************************************************************
196 * Tegra TZRAM constants
197 ******************************************************************************/
198#define TEGRA_TZRAM_BASE 0x30000000
Varun Wadekare6d43222016-05-25 16:35:04 -0700[diff] [blame]199#define TEGRA_TZRAM_SIZE 0x40000
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800[diff] [blame]200
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]201#endif /* __TEGRA_DEF_H__ */