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git01.mediatek.com / filogic / atf / 921b906828011a8bc1c215a4b303cfce78063e77 / . / plat / nvidia / tegra / include / t186 / tegra_def.h
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Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame^]1/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __TEGRA_DEF_H__
32#define __TEGRA_DEF_H__
33
34#include <platform_def.h>
35
36/*******************************************************************************
37 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
38 * call as the `state-id` field in the 'power state' parameter.
39 ******************************************************************************/
40#define PLAT_SYS_SUSPEND_STATE_ID 0
41
42/*******************************************************************************
43 * Implementation defined ACTLR_EL3 bit definitions
44 ******************************************************************************/
45#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
46#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
47#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
48#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
49#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
50#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
51 ACTLR_EL3_L2ECTLR_BIT | \
52 ACTLR_EL3_L2CTLR_BIT | \
53 ACTLR_EL3_CPUECTLR_BIT | \
54 ACTLR_EL3_CPUACTLR_BIT)
55
56/*******************************************************************************
57 * Tegra Miscellanous register constants
58 ******************************************************************************/
59#define TEGRA_MISC_BASE 0x00100000
60
61/*******************************************************************************
62 * Tegra Memory Controller constants
63 ******************************************************************************/
64#define TEGRA_MC_STREAMID_BASE 0x02C00000
65#define TEGRA_MC_BASE 0x02C10000
66
67/*******************************************************************************
68 * Tegra UART Controller constants
69 ******************************************************************************/
70#define TEGRA_UARTA_BASE 0x03100000
71#define TEGRA_UARTB_BASE 0x03110000
72#define TEGRA_UARTC_BASE 0x0C280000
73#define TEGRA_UARTD_BASE 0x03130000
74#define TEGRA_UARTE_BASE 0x03140000
75#define TEGRA_UARTF_BASE 0x03150000
76#define TEGRA_UARTG_BASE 0x0C290000
77
78/*******************************************************************************
79 * GICv2 & interrupt handling related constants
80 ******************************************************************************/
81#define TEGRA_GICD_BASE 0x03881000
82#define TEGRA_GICC_BASE 0x03882000
83
84/*******************************************************************************
85 * Tegra Clock and Reset Controller constants
86 ******************************************************************************/
87#define TEGRA_CAR_RESET_BASE 0x05000000
88
89/*******************************************************************************
90 * Tegra micro-seconds timer constants
91 ******************************************************************************/
92#define TEGRA_TMRUS_BASE 0x0C2E0000
93
94/*******************************************************************************
95 * Tegra Power Mgmt Controller constants
96 ******************************************************************************/
97#define TEGRA_PMC_BASE 0x0C360000
98
99/*******************************************************************************
100 * Tegra scratch registers constants
101 ******************************************************************************/
102#define TEGRA_SCRATCH_BASE 0x0C390000
103
104/*******************************************************************************
105 * Tegra Memory Mapped Control Register Access Bus constants
106 ******************************************************************************/
107#define TEGRA_MMCRAB_BASE 0x0E000000
108
109/*******************************************************************************
110 * Tegra SMMU Controller constants
111 ******************************************************************************/
112#define TEGRA_SMMU_BASE 0x12000000
113
114#endif /* __TEGRA_DEF_H__ */