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git01.mediatek.com / filogic / atf / e2bc7f22f5ecca7c2b5a1fd1e2c710e7eb053d63 / . / plat / nvidia / tegra / include / t186 / tegra_def.h
blob: 7f618bdd3097cca976b357e0340cdead1715ff9d [file] [log] [blame]
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]1/*
Varun Wadekarcad7b082015-12-28 18:12:59 -0800[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __TEGRA_DEF_H__
32#define __TEGRA_DEF_H__
33
34#include <platform_def.h>
35
36/*******************************************************************************
Varun Wadekar42236572016-01-18 19:03:19 -0800[diff] [blame]37 * These values are used by the PSCI implementation during the `CPU_SUSPEND`
38 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
39 * parameter.
40 ******************************************************************************/
41#define PSTATE_ID_CORE_IDLE 6
42#define PSTATE_ID_CORE_POWERDN 7
43#define PSTATE_ID_SOC_POWERDN 2
44
45/*******************************************************************************
46 * Platform power states (used by PSCI framework)
47 *
48 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
49 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]50 ******************************************************************************/
Varun Wadekar42236572016-01-18 19:03:19 -0800[diff] [blame]51#define PLAT_MAX_RET_STATE 1
52#define PLAT_MAX_OFF_STATE 8
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]53
54/*******************************************************************************
55 * Implementation defined ACTLR_EL3 bit definitions
56 ******************************************************************************/
57#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
58#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
59#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
60#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
61#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
62#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
63 ACTLR_EL3_L2ECTLR_BIT | \
64 ACTLR_EL3_L2CTLR_BIT | \
65 ACTLR_EL3_CPUECTLR_BIT | \
66 ACTLR_EL3_CPUACTLR_BIT)
67
68/*******************************************************************************
Varun Wadekarcad7b082015-12-28 18:12:59 -0800[diff] [blame]69 * Secure IRQ definitions
70 ******************************************************************************/
71#define TEGRA186_TOP_WDT_IRQ 49
72#define TEGRA186_AON_WDT_IRQ 50
73
74#define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */
75
76/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]77 * Tegra Miscellanous register constants
78 ******************************************************************************/
79#define TEGRA_MISC_BASE 0x00100000
Varun Wadekarc9ac3e42016-02-17 15:07:49 -0800[diff] [blame]80#define HARDWARE_REVISION_OFFSET 0x4
Varun Wadekare2bc7f22016-04-02 15:41:20 -0700[diff] [blame^]81#define MAJOR_VERSION_SHIFT 0x4
82#define MAJOR_VERSION_MASK 0xF
83#define MINOR_VERSION_SHIFT 0x10
84#define MINOR_VERSION_MASK 0xF
85
Varun Wadekarb8776152016-03-03 13:52:52 -0800[diff] [blame]86#define MISCREG_PFCFG 0x200C
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]87
88/*******************************************************************************
Varun Wadekara0f26972016-03-11 17:18:51 -0800[diff] [blame]89 * Tegra TSA Controller constants
90 ******************************************************************************/
91#define TEGRA_TSA_BASE 0x02400000
92
93/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]94 * Tegra Memory Controller constants
95 ******************************************************************************/
96#define TEGRA_MC_STREAMID_BASE 0x02C00000
97#define TEGRA_MC_BASE 0x02C10000
98
99/*******************************************************************************
100 * Tegra UART Controller constants
101 ******************************************************************************/
102#define TEGRA_UARTA_BASE 0x03100000
103#define TEGRA_UARTB_BASE 0x03110000
104#define TEGRA_UARTC_BASE 0x0C280000
105#define TEGRA_UARTD_BASE 0x03130000
106#define TEGRA_UARTE_BASE 0x03140000
107#define TEGRA_UARTF_BASE 0x03150000
108#define TEGRA_UARTG_BASE 0x0C290000
109
110/*******************************************************************************
111 * GICv2 & interrupt handling related constants
112 ******************************************************************************/
113#define TEGRA_GICD_BASE 0x03881000
114#define TEGRA_GICC_BASE 0x03882000
115
116/*******************************************************************************
Varun Wadekarb8776152016-03-03 13:52:52 -0800[diff] [blame]117 * Security Engine related constants
118 ******************************************************************************/
119#define TEGRA_SE0_BASE 0x03AC0000
120#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C
121#define TEGRA_PKA1_BASE 0x03AD0000
122#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144
123#define TEGRA_RNG1_BASE 0x03AE0000
124#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0
125
126/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]127 * Tegra Clock and Reset Controller constants
128 ******************************************************************************/
129#define TEGRA_CAR_RESET_BASE 0x05000000
130
131/*******************************************************************************
132 * Tegra micro-seconds timer constants
133 ******************************************************************************/
134#define TEGRA_TMRUS_BASE 0x0C2E0000
135
136/*******************************************************************************
137 * Tegra Power Mgmt Controller constants
138 ******************************************************************************/
139#define TEGRA_PMC_BASE 0x0C360000
140
141/*******************************************************************************
142 * Tegra scratch registers constants
143 ******************************************************************************/
144#define TEGRA_SCRATCH_BASE 0x0C390000
Varun Wadekarb8776152016-03-03 13:52:52 -0800[diff] [blame]145#define SECURE_SCRATCH_RSV6 0x680
146#define SECURE_SCRATCH_RSV11_LO 0x6A8
147#define SECURE_SCRATCH_RSV11_HI 0x6AC
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]148
149/*******************************************************************************
150 * Tegra Memory Mapped Control Register Access Bus constants
151 ******************************************************************************/
152#define TEGRA_MMCRAB_BASE 0x0E000000
153
154/*******************************************************************************
155 * Tegra SMMU Controller constants
156 ******************************************************************************/
157#define TEGRA_SMMU_BASE 0x12000000
158
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800[diff] [blame]159/*******************************************************************************
160 * Tegra TZRAM constants
161 ******************************************************************************/
162#define TEGRA_TZRAM_BASE 0x30000000
163#define TEGRA_TZRAM_SIZE 0x50000
164
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]165#endif /* __TEGRA_DEF_H__ */