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git01.mediatek.com / filogic / atf / 47ddd0005b83ac00c222f39b124bd554b1ed58b2 / . / plat / nvidia / tegra / include / t186 / tegra_def.h
blob: 04a7d0b3b768acf3974f6c1fef48f556381a93a6 [file] [log] [blame]
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]1/*
Varun Wadekarcad7b082015-12-28 18:12:59 -0800[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __TEGRA_DEF_H__
32#define __TEGRA_DEF_H__
33
34#include <platform_def.h>
35
36/*******************************************************************************
Varun Wadekar42236572016-01-18 19:03:19 -0800[diff] [blame]37 * These values are used by the PSCI implementation during the `CPU_SUSPEND`
38 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
39 * parameter.
40 ******************************************************************************/
41#define PSTATE_ID_CORE_IDLE 6
42#define PSTATE_ID_CORE_POWERDN 7
43#define PSTATE_ID_SOC_POWERDN 2
44
45/*******************************************************************************
46 * Platform power states (used by PSCI framework)
47 *
48 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
49 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]50 ******************************************************************************/
Varun Wadekar42236572016-01-18 19:03:19 -0800[diff] [blame]51#define PLAT_MAX_RET_STATE 1
52#define PLAT_MAX_OFF_STATE 8
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]53
54/*******************************************************************************
55 * Implementation defined ACTLR_EL3 bit definitions
56 ******************************************************************************/
57#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
58#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
59#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
60#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
61#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
62#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
63 ACTLR_EL3_L2ECTLR_BIT | \
64 ACTLR_EL3_L2CTLR_BIT | \
65 ACTLR_EL3_CPUECTLR_BIT | \
66 ACTLR_EL3_CPUACTLR_BIT)
67
68/*******************************************************************************
Varun Wadekarcad7b082015-12-28 18:12:59 -0800[diff] [blame]69 * Secure IRQ definitions
70 ******************************************************************************/
71#define TEGRA186_TOP_WDT_IRQ 49
72#define TEGRA186_AON_WDT_IRQ 50
73
74#define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */
75
76/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]77 * Tegra Miscellanous register constants
78 ******************************************************************************/
79#define TEGRA_MISC_BASE 0x00100000
Varun Wadekarc9ac3e42016-02-17 15:07:49 -0800[diff] [blame]80#define HARDWARE_REVISION_OFFSET 0x4
81#define HARDWARE_MINOR_REVISION_MASK 0xf0000
82#define HARDWARE_MINOR_REVISION_SHIFT 0x10
83#define HARDWARE_REVISION_A01 1
Varun Wadekarb8776152016-03-03 13:52:52 -0800[diff] [blame]84#define MISCREG_PFCFG 0x200C
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]85
86/*******************************************************************************
Varun Wadekara0f26972016-03-11 17:18:51 -0800[diff] [blame]87 * Tegra TSA Controller constants
88 ******************************************************************************/
89#define TEGRA_TSA_BASE 0x02400000
90
91/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]92 * Tegra Memory Controller constants
93 ******************************************************************************/
94#define TEGRA_MC_STREAMID_BASE 0x02C00000
95#define TEGRA_MC_BASE 0x02C10000
96
97/*******************************************************************************
98 * Tegra UART Controller constants
99 ******************************************************************************/
100#define TEGRA_UARTA_BASE 0x03100000
101#define TEGRA_UARTB_BASE 0x03110000
102#define TEGRA_UARTC_BASE 0x0C280000
103#define TEGRA_UARTD_BASE 0x03130000
104#define TEGRA_UARTE_BASE 0x03140000
105#define TEGRA_UARTF_BASE 0x03150000
106#define TEGRA_UARTG_BASE 0x0C290000
107
108/*******************************************************************************
109 * GICv2 & interrupt handling related constants
110 ******************************************************************************/
111#define TEGRA_GICD_BASE 0x03881000
112#define TEGRA_GICC_BASE 0x03882000
113
114/*******************************************************************************
Varun Wadekarb8776152016-03-03 13:52:52 -0800[diff] [blame]115 * Security Engine related constants
116 ******************************************************************************/
117#define TEGRA_SE0_BASE 0x03AC0000
118#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C
119#define TEGRA_PKA1_BASE 0x03AD0000
120#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144
121#define TEGRA_RNG1_BASE 0x03AE0000
122#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0
123
124/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]125 * Tegra Clock and Reset Controller constants
126 ******************************************************************************/
127#define TEGRA_CAR_RESET_BASE 0x05000000
128
129/*******************************************************************************
130 * Tegra micro-seconds timer constants
131 ******************************************************************************/
132#define TEGRA_TMRUS_BASE 0x0C2E0000
133
134/*******************************************************************************
135 * Tegra Power Mgmt Controller constants
136 ******************************************************************************/
137#define TEGRA_PMC_BASE 0x0C360000
138
139/*******************************************************************************
140 * Tegra scratch registers constants
141 ******************************************************************************/
142#define TEGRA_SCRATCH_BASE 0x0C390000
Varun Wadekarb8776152016-03-03 13:52:52 -0800[diff] [blame]143#define SECURE_SCRATCH_RSV6 0x680
144#define SECURE_SCRATCH_RSV11_LO 0x6A8
145#define SECURE_SCRATCH_RSV11_HI 0x6AC
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]146
147/*******************************************************************************
148 * Tegra Memory Mapped Control Register Access Bus constants
149 ******************************************************************************/
150#define TEGRA_MMCRAB_BASE 0x0E000000
151
152/*******************************************************************************
153 * Tegra SMMU Controller constants
154 ******************************************************************************/
155#define TEGRA_SMMU_BASE 0x12000000
156
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800[diff] [blame]157/*******************************************************************************
158 * Tegra TZRAM constants
159 ******************************************************************************/
160#define TEGRA_TZRAM_BASE 0x30000000
161#define TEGRA_TZRAM_SIZE 0x50000
162
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]163#endif /* __TEGRA_DEF_H__ */