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git01.mediatek.com / filogic / atf / c9ac3e466e46b6b82224dc17dca02660cd57e6d6 / . / plat / nvidia / tegra / include / t186 / tegra_def.h
blob: e74ed166fe63cc84095f0d03c25ad98da8ad11a6 [file] [log] [blame]
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]1/*
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -0800[diff] [blame]2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __TEGRA_DEF_H__
32#define __TEGRA_DEF_H__
33
34#include <platform_def.h>
35
36/*******************************************************************************
Varun Wadekar42236572016-01-18 19:03:19 -0800[diff] [blame]37 * These values are used by the PSCI implementation during the `CPU_SUSPEND`
38 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
39 * parameter.
40 ******************************************************************************/
41#define PSTATE_ID_CORE_IDLE 6
42#define PSTATE_ID_CORE_POWERDN 7
43#define PSTATE_ID_SOC_POWERDN 2
44
45/*******************************************************************************
46 * Platform power states (used by PSCI framework)
47 *
48 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
49 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]50 ******************************************************************************/
Varun Wadekar42236572016-01-18 19:03:19 -0800[diff] [blame]51#define PLAT_MAX_RET_STATE 1
52#define PLAT_MAX_OFF_STATE 8
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]53
54/*******************************************************************************
55 * Implementation defined ACTLR_EL3 bit definitions
56 ******************************************************************************/
57#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
58#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
59#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
60#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
61#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
62#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
63 ACTLR_EL3_L2ECTLR_BIT | \
64 ACTLR_EL3_L2CTLR_BIT | \
65 ACTLR_EL3_CPUECTLR_BIT | \
66 ACTLR_EL3_CPUACTLR_BIT)
67
68/*******************************************************************************
69 * Tegra Miscellanous register constants
70 ******************************************************************************/
71#define TEGRA_MISC_BASE 0x00100000
Varun Wadekarc9ac3e42016-02-17 15:07:49 -0800[diff] [blame^]72#define HARDWARE_REVISION_OFFSET 0x4
73#define HARDWARE_MINOR_REVISION_MASK 0xf0000
74#define HARDWARE_MINOR_REVISION_SHIFT 0x10
75#define HARDWARE_REVISION_A01 1
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]76
77/*******************************************************************************
78 * Tegra Memory Controller constants
79 ******************************************************************************/
80#define TEGRA_MC_STREAMID_BASE 0x02C00000
81#define TEGRA_MC_BASE 0x02C10000
82
83/*******************************************************************************
84 * Tegra UART Controller constants
85 ******************************************************************************/
86#define TEGRA_UARTA_BASE 0x03100000
87#define TEGRA_UARTB_BASE 0x03110000
88#define TEGRA_UARTC_BASE 0x0C280000
89#define TEGRA_UARTD_BASE 0x03130000
90#define TEGRA_UARTE_BASE 0x03140000
91#define TEGRA_UARTF_BASE 0x03150000
92#define TEGRA_UARTG_BASE 0x0C290000
93
94/*******************************************************************************
95 * GICv2 & interrupt handling related constants
96 ******************************************************************************/
97#define TEGRA_GICD_BASE 0x03881000
98#define TEGRA_GICC_BASE 0x03882000
99
100/*******************************************************************************
101 * Tegra Clock and Reset Controller constants
102 ******************************************************************************/
103#define TEGRA_CAR_RESET_BASE 0x05000000
104
105/*******************************************************************************
106 * Tegra micro-seconds timer constants
107 ******************************************************************************/
108#define TEGRA_TMRUS_BASE 0x0C2E0000
109
110/*******************************************************************************
111 * Tegra Power Mgmt Controller constants
112 ******************************************************************************/
113#define TEGRA_PMC_BASE 0x0C360000
114
115/*******************************************************************************
116 * Tegra scratch registers constants
117 ******************************************************************************/
118#define TEGRA_SCRATCH_BASE 0x0C390000
119
120/*******************************************************************************
121 * Tegra Memory Mapped Control Register Access Bus constants
122 ******************************************************************************/
123#define TEGRA_MMCRAB_BASE 0x0E000000
124
125/*******************************************************************************
126 * Tegra SMMU Controller constants
127 ******************************************************************************/
128#define TEGRA_SMMU_BASE 0x12000000
129
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800[diff] [blame]130/*******************************************************************************
131 * Tegra TZRAM constants
132 ******************************************************************************/
133#define TEGRA_TZRAM_BASE 0x30000000
134#define TEGRA_TZRAM_SIZE 0x50000
135
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]136#endif /* __TEGRA_DEF_H__ */