Tegra: memctrl_v2: implement MC txn override WAR
This patch sets the Memory Controller's TXN_OVERRIDE registers
for most write clients to CGID_ADR. This ensures ordering is maintained.
In some cases WAW ordering problems could occur. There are different
settings for Tegra version A01 v A02.
Original changes by Alex Waterman <alexw@nvidia.com>
Change-Id: I82ea02afa43a24250ed56985757b83e78e71178c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index 3983a6b..e74ed16 100644
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -69,6 +69,10 @@
* Tegra Miscellanous register constants
******************************************************************************/
#define TEGRA_MISC_BASE 0x00100000
+#define HARDWARE_REVISION_OFFSET 0x4
+#define HARDWARE_MINOR_REVISION_MASK 0xf0000
+#define HARDWARE_MINOR_REVISION_SHIFT 0x10
+#define HARDWARE_REVISION_A01 1
/*******************************************************************************
* Tegra Memory Controller constants