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Achin Gupta92712a52015-09-03 14:18:02 +01001/*
Manish V Badarkhe173c2962022-05-09 21:55:19 +01002 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
Varun Wadekar61286d22023-03-08 16:47:38 +00003 * Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
Achin Gupta92712a52015-09-03 14:18:02 +01004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta92712a52015-09-03 14:18:02 +01006 */
7
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <assert.h>
9
Achin Gupta92712a52015-09-03 14:18:02 +010010#include <arch.h>
11#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <common/debug.h>
13#include <common/interrupt_props.h>
Varun Wadekar61286d22023-03-08 16:47:38 +000014#include <drivers/arm/gic600_multichip.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <drivers/arm/gic_common.h>
16
Claus Pedersen785e66c2022-09-12 22:42:58 +000017#include <platform_def.h>
18
Soby Mathew50f6fe42016-02-01 17:59:22 +000019#include "../common/gic_common_private.h"
Achin Gupta92712a52015-09-03 14:18:02 +010020#include "gicv3_private.h"
21
Varun Wadekar61286d22023-03-08 16:47:38 +000022uintptr_t gicv3_get_multichip_base(uint32_t spi_id, uintptr_t gicd_base)
23{
24#if GICV3_IMPL_GIC600_MULTICHIP
25 if (gic600_multichip_is_initialized()) {
26 return gic600_multichip_gicd_base_for_spi(spi_id);
27 }
28#endif
29 return gicd_base;
30}
31
Achin Gupta92712a52015-09-03 14:18:02 +010032/******************************************************************************
33 * This function marks the core as awake in the re-distributor and
34 * ensures that the interface is active.
35 *****************************************************************************/
36void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base)
37{
38 /*
39 * The WAKER_PS_BIT should be changed to 0
40 * only when WAKER_CA_BIT is 1.
41 */
Antonio Nino Diazca994e72018-08-21 10:02:33 +010042 assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U);
Achin Gupta92712a52015-09-03 14:18:02 +010043
44 /* Mark the connected core as awake */
45 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT);
46
47 /* Wait till the WAKER_CA_BIT changes to 0 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010048 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) {
49 }
Achin Gupta92712a52015-09-03 14:18:02 +010050}
51
Achin Gupta92712a52015-09-03 14:18:02 +010052/******************************************************************************
53 * This function marks the core as asleep in the re-distributor and ensures
54 * that the interface is quiescent.
55 *****************************************************************************/
56void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base)
57{
58 /* Mark the connected core as asleep */
59 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT);
60
61 /* Wait till the WAKER_CA_BIT changes to 1 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010062 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) {
63 }
Achin Gupta92712a52015-09-03 14:18:02 +010064}
65
Achin Gupta92712a52015-09-03 14:18:02 +010066/*******************************************************************************
67 * This function probes the Redistributor frames when the driver is initialised
68 * and saves their base addresses. These base addresses are used later to
69 * initialise each Redistributor interface.
70 ******************************************************************************/
71void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
72 unsigned int rdistif_num,
73 uintptr_t gicr_base,
74 mpidr_hash_fn mpidr_to_core_pos)
75{
Soby Mathewa0fedc42016-06-16 14:52:04 +010076 u_register_t mpidr;
Achin Gupta92712a52015-09-03 14:18:02 +010077 unsigned int proc_num;
Antonio Nino Diazca994e72018-08-21 10:02:33 +010078 uint64_t typer_val;
Achin Gupta92712a52015-09-03 14:18:02 +010079 uintptr_t rdistif_base = gicr_base;
80
Antonio Nino Diazca994e72018-08-21 10:02:33 +010081 assert(rdistif_base_addrs != NULL);
Achin Gupta92712a52015-09-03 14:18:02 +010082
83 /*
84 * Iterate over the Redistributor frames. Store the base address of each
85 * frame in the platform provided array. Use the "Processor Number"
86 * field to index into the array if the platform has not provided a hash
87 * function to convert an MPIDR (obtained from the "Affinity Value"
88 * field into a linear index.
89 */
90 do {
91 typer_val = gicr_read_typer(rdistif_base);
Antonio Nino Diazca994e72018-08-21 10:02:33 +010092 if (mpidr_to_core_pos != NULL) {
Achin Gupta92712a52015-09-03 14:18:02 +010093 mpidr = mpidr_from_gicr_typer(typer_val);
94 proc_num = mpidr_to_core_pos(mpidr);
95 } else {
96 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) &
97 TYPER_PROC_NUM_MASK;
98 }
Soby Mathewd1463bd2019-01-17 14:57:54 +000099
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100100 if (proc_num < rdistif_num) {
Soby Mathewd1463bd2019-01-17 14:57:54 +0000101 rdistif_base_addrs[proc_num] = rdistif_base;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100102 }
Andre Przywaraf70f4b92021-05-18 15:51:06 +0100103 rdistif_base += gicv3_redist_size(typer_val);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100104 } while ((typer_val & TYPER_LAST_BIT) == 0U);
Achin Gupta92712a52015-09-03 14:18:02 +0100105}
106
107/*******************************************************************************
Heyi Guo06f85b42021-01-20 18:50:16 +0800108 * Helper function to get the maximum SPI INTID + 1.
109 ******************************************************************************/
110unsigned int gicv3_get_spi_limit(uintptr_t gicd_base)
111{
112 unsigned int spi_limit;
113 unsigned int typer_reg = gicd_read_typer(gicd_base);
114
115 /* (maximum SPI INTID + 1) is equal to 32 * (GICD_TYPER.ITLinesNumber+1) */
116 spi_limit = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
117
118 /* Filter out special INTIDs 1020-1023 */
119 if (spi_limit > (MAX_SPI_ID + 1U)) {
120 return MAX_SPI_ID + 1U;
121 }
122
123 return spi_limit;
124}
125
Heyi Guo60ce8252021-01-20 18:50:16 +0800126#if GIC_EXT_INTID
127/*******************************************************************************
128 * Helper function to get the maximum ESPI INTID + 1.
129 ******************************************************************************/
130unsigned int gicv3_get_espi_limit(uintptr_t gicd_base)
131{
132 unsigned int typer_reg = gicd_read_typer(gicd_base);
133
134 /* Check if extended SPI range is implemented */
135 if ((typer_reg & TYPER_ESPI) != 0U) {
136 /*
137 * (maximum ESPI INTID + 1) is equal to
138 * 32 * (GICD_TYPER.ESPI_range + 1) + 4096
139 */
140 return ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
141 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
142 }
143
144 return 0U;
145}
146#endif /* GIC_EXT_INTID */
147
Heyi Guo06f85b42021-01-20 18:50:16 +0800148/*******************************************************************************
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100149 * Helper function to configure the default attributes of (E)SPIs.
Achin Gupta92712a52015-09-03 14:18:02 +0100150 ******************************************************************************/
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100151void gicv3_spis_config_defaults(uintptr_t gicd_base)
Achin Gupta92712a52015-09-03 14:18:02 +0100152{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100153 unsigned int i, num_ints;
154#if GIC_EXT_INTID
155 unsigned int num_eints;
156#endif
Achin Gupta92712a52015-09-03 14:18:02 +0100157
Heyi Guo79bc7a72021-01-20 19:05:51 +0800158 num_ints = gicv3_get_spi_limit(gicd_base);
Heyi Guoce380252021-01-21 10:34:00 +0800159 INFO("Maximum SPI INTID supported: %u\n", num_ints - 1);
Heyi Guo0d5d24d2020-05-19 15:41:14 +0800160
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100161 /* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */
162 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) {
Varun Wadekar61286d22023-03-08 16:47:38 +0000163 gicd_write_igroupr(gicv3_get_multichip_base(i, gicd_base), i, ~0U);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100164 }
Achin Gupta92712a52015-09-03 14:18:02 +0100165
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100166#if GIC_EXT_INTID
Heyi Guo79bc7a72021-01-20 19:05:51 +0800167 num_eints = gicv3_get_espi_limit(gicd_base);
168 if (num_eints != 0U) {
Heyi Guoce380252021-01-21 10:34:00 +0800169 INFO("Maximum ESPI INTID supported: %u\n", num_eints - 1);
Achin Gupta92712a52015-09-03 14:18:02 +0100170
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100171 for (i = MIN_ESPI_ID; i < num_eints;
172 i += (1U << IGROUPR_SHIFT)) {
Varun Wadekar61286d22023-03-08 16:47:38 +0000173 gicd_write_igroupr(gicv3_get_multichip_base(i, gicd_base), i, ~0U);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100174 }
175 } else {
Heyi Guoce380252021-01-21 10:34:00 +0800176 INFO("ESPI range is not implemented.\n");
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100177 }
178#endif
179
180 /* Setup the default (E)SPI priorities doing four at a time */
181 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) {
Varun Wadekar61286d22023-03-08 16:47:38 +0000182 gicd_write_ipriorityr(gicv3_get_multichip_base(i, gicd_base), i, GICD_IPRIORITYR_DEF_VAL);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100183 }
184
185#if GIC_EXT_INTID
186 for (i = MIN_ESPI_ID; i < num_eints;
187 i += (1U << IPRIORITYR_SHIFT)) {
Varun Wadekar61286d22023-03-08 16:47:38 +0000188 gicd_write_ipriorityr(gicv3_get_multichip_base(i, gicd_base), i, GICD_IPRIORITYR_DEF_VAL);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100189 }
190#endif
Achin Gupta92712a52015-09-03 14:18:02 +0100191 /*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100192 * Treat all (E)SPIs as level triggered by default, write 16 at a time
Achin Gupta92712a52015-09-03 14:18:02 +0100193 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100194 for (i = MIN_SPI_ID; i < num_ints; i += (1U << ICFGR_SHIFT)) {
Varun Wadekar61286d22023-03-08 16:47:38 +0000195 gicd_write_icfgr(gicv3_get_multichip_base(i, gicd_base), i, 0U);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100196 }
197
198#if GIC_EXT_INTID
199 for (i = MIN_ESPI_ID; i < num_eints; i += (1U << ICFGR_SHIFT)) {
Varun Wadekar61286d22023-03-08 16:47:38 +0000200 gicd_write_icfgr(gicv3_get_multichip_base(i, gicd_base), i, 0U);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100201 }
202#endif
Achin Gupta92712a52015-09-03 14:18:02 +0100203}
204
Achin Gupta92712a52015-09-03 14:18:02 +0100205/*******************************************************************************
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100206 * Helper function to configure properties of secure (E)SPIs
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100207 ******************************************************************************/
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100208unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100209 const interrupt_prop_t *interrupt_props,
210 unsigned int interrupt_props_num)
211{
212 unsigned int i;
213 const interrupt_prop_t *current_prop;
214 unsigned long long gic_affinity_val;
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100215 unsigned int ctlr_enable = 0U;
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100216
217 /* Make sure there's a valid property array */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100218 if (interrupt_props_num > 0U) {
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100219 assert(interrupt_props != NULL);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100220 }
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100221
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100222 for (i = 0U; i < interrupt_props_num; i++) {
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100223 current_prop = &interrupt_props[i];
224
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100225 unsigned int intr_num = current_prop->intr_num;
Varun Wadekar61286d22023-03-08 16:47:38 +0000226 uintptr_t multichip_gicd_base = gicv3_get_multichip_base(intr_num, gicd_base);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100227
228 /* Skip SGI, (E)PPI and LPI interrupts */
229 if (!IS_SPI(intr_num)) {
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100230 continue;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100231 }
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100232
233 /* Configure this interrupt as a secure interrupt */
Varun Wadekar61286d22023-03-08 16:47:38 +0000234 gicd_clr_igroupr(multichip_gicd_base, intr_num);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100235
236 /* Configure this interrupt as G0 or a G1S interrupt */
237 assert((current_prop->intr_grp == INTR_GROUP0) ||
238 (current_prop->intr_grp == INTR_GROUP1S));
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100239
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100240 if (current_prop->intr_grp == INTR_GROUP1S) {
Varun Wadekar61286d22023-03-08 16:47:38 +0000241 gicd_set_igrpmodr(multichip_gicd_base, intr_num);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100242 ctlr_enable |= CTLR_ENABLE_G1S_BIT;
243 } else {
Varun Wadekar61286d22023-03-08 16:47:38 +0000244 gicd_clr_igrpmodr(multichip_gicd_base, intr_num);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100245 ctlr_enable |= CTLR_ENABLE_G0_BIT;
246 }
247
248 /* Set interrupt configuration */
Varun Wadekar61286d22023-03-08 16:47:38 +0000249 gicd_set_icfgr(multichip_gicd_base, intr_num,
250 current_prop->intr_cfg);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100251
252 /* Set the priority of this interrupt */
Varun Wadekar61286d22023-03-08 16:47:38 +0000253 gicd_set_ipriorityr(multichip_gicd_base, intr_num,
254 current_prop->intr_pri);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100255
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100256 /* Target (E)SPIs to the primary CPU */
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100257 gic_affinity_val =
258 gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
Varun Wadekar61286d22023-03-08 16:47:38 +0000259 gicd_write_irouter(multichip_gicd_base, intr_num,
260 gic_affinity_val);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100261
262 /* Enable this interrupt */
Varun Wadekar61286d22023-03-08 16:47:38 +0000263 gicd_set_isenabler(multichip_gicd_base, intr_num);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100264 }
265
266 return ctlr_enable;
267}
268
269/*******************************************************************************
Sylwester Garncarek799adfd2023-01-07 08:50:25 +0700270 * Helper function to configure the default attributes of (E)PPIs/SGIs
Achin Gupta92712a52015-09-03 14:18:02 +0100271 ******************************************************************************/
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100272void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base)
Achin Gupta92712a52015-09-03 14:18:02 +0100273{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100274 unsigned int i, ppi_regs_num, regs_num;
Achin Gupta92712a52015-09-03 14:18:02 +0100275
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100276#if GIC_EXT_INTID
277 /* Calculate number of PPI registers */
278 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >>
279 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1;
280 /* All other values except PPInum [0-2] are reserved */
281 if (ppi_regs_num > 3U) {
282 ppi_regs_num = 1U;
283 }
284#else
285 ppi_regs_num = 1U;
286#endif
Achin Gupta92712a52015-09-03 14:18:02 +0100287 /*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100288 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them.
289 * This is a more scalable approach as it avoids clearing
290 * the enable bits in the GICD_CTLR.
Achin Gupta92712a52015-09-03 14:18:02 +0100291 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100292 for (i = 0U; i < ppi_regs_num; ++i) {
293 gicr_write_icenabler(gicr_base, i, ~0U);
294 }
295
296 /* Wait for pending writes to GICR_ICENABLER */
Achin Gupta92712a52015-09-03 14:18:02 +0100297 gicr_wait_for_pending_write(gicr_base);
298
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100299 /* 32 interrupt IDs per GICR_IGROUPR register */
300 for (i = 0U; i < ppi_regs_num; ++i) {
301 /* Treat all SGIs/(E)PPIs as G1NS by default */
302 gicr_write_igroupr(gicr_base, i, ~0U);
303 }
Achin Gupta92712a52015-09-03 14:18:02 +0100304
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100305 /* 4 interrupt IDs per GICR_IPRIORITYR register */
306 regs_num = ppi_regs_num << 3;
307 for (i = 0U; i < regs_num; ++i) {
308 /* Setup the default (E)PPI/SGI priorities doing 4 at a time */
Sylwester Garncarek799adfd2023-01-07 08:50:25 +0700309 gicr_write_ipriorityr(gicr_base, i << 2, GICD_IPRIORITYR_DEF_VAL);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100310 }
Achin Gupta92712a52015-09-03 14:18:02 +0100311
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100312 /* 16 interrupt IDs per GICR_ICFGR register */
313 regs_num = ppi_regs_num << 1;
314 for (i = (MIN_PPI_ID >> ICFGR_SHIFT); i < regs_num; ++i) {
315 /* Configure all (E)PPIs as level triggered by default */
316 gicr_write_icfgr(gicr_base, i, 0U);
317 }
Achin Gupta92712a52015-09-03 14:18:02 +0100318}
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100319
320/*******************************************************************************
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100321 * Helper function to configure properties of secure G0 and G1S (E)PPIs and SGIs
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100322 ******************************************************************************/
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100323unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100324 const interrupt_prop_t *interrupt_props,
325 unsigned int interrupt_props_num)
326{
327 unsigned int i;
328 const interrupt_prop_t *current_prop;
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100329 unsigned int ctlr_enable = 0U;
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100330
331 /* Make sure there's a valid property array */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100332 if (interrupt_props_num > 0U) {
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100333 assert(interrupt_props != NULL);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100334 }
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100335
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100336 for (i = 0U; i < interrupt_props_num; i++) {
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100337 current_prop = &interrupt_props[i];
338
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100339 unsigned int intr_num = current_prop->intr_num;
340
341 /* Skip (E)SPI interrupt */
342 if (!IS_SGI_PPI(intr_num)) {
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100343 continue;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100344 }
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100345
346 /* Configure this interrupt as a secure interrupt */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100347 gicr_clr_igroupr(gicr_base, intr_num);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100348
349 /* Configure this interrupt as G0 or a G1S interrupt */
350 assert((current_prop->intr_grp == INTR_GROUP0) ||
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100351 (current_prop->intr_grp == INTR_GROUP1S));
352
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000353 if (current_prop->intr_grp == INTR_GROUP1S) {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100354 gicr_set_igrpmodr(gicr_base, intr_num);
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000355 ctlr_enable |= CTLR_ENABLE_G1S_BIT;
356 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100357 gicr_clr_igrpmodr(gicr_base, intr_num);
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000358 ctlr_enable |= CTLR_ENABLE_G0_BIT;
359 }
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100360
361 /* Set the priority of this interrupt */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100362 gicr_set_ipriorityr(gicr_base, intr_num,
363 current_prop->intr_pri);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100364
365 /*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100366 * Set interrupt configuration for (E)PPIs.
367 * Configurations for SGIs 0-15 are ignored.
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100368 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100369 if (intr_num >= MIN_PPI_ID) {
370 gicr_set_icfgr(gicr_base, intr_num,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100371 current_prop->intr_cfg);
372 }
373
374 /* Enable this interrupt */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100375 gicr_set_isenabler(gicr_base, intr_num);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100376 }
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000377
378 return ctlr_enable;
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100379}
Andre Przywara95581b42020-09-07 14:53:58 +0100380
381/**
382 * gicv3_rdistif_get_number_frames() - determine size of GICv3 GICR region
383 * @gicr_frame: base address of the GICR region to check
384 *
385 * This iterates over the GICR_TYPER registers of multiple GICR frames in
386 * a GICR region, to find the instance which has the LAST bit set. For most
387 * systems this corresponds to the number of cores handled by a redistributor,
388 * but there could be disabled cores among them.
389 * It assumes that each GICR region is fully accessible (till the LAST bit
390 * marks the end of the region).
391 * If a platform has multiple GICR regions, this function would need to be
392 * called multiple times, providing the respective GICR base address each time.
393 *
394 * Return: number of valid GICR frames (at least 1, up to PLATFORM_CORE_COUNT)
395 ******************************************************************************/
396unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame)
397{
398 uintptr_t rdistif_base = gicr_frame;
399 unsigned int count;
400
Andre Przywaraf70f4b92021-05-18 15:51:06 +0100401 for (count = 1U; count < PLATFORM_CORE_COUNT; count++) {
402 uint64_t typer_val = gicr_read_typer(rdistif_base);
403
404 if ((typer_val & TYPER_LAST_BIT) != 0U) {
Andre Przywara95581b42020-09-07 14:53:58 +0100405 break;
406 }
Andre Przywaraf70f4b92021-05-18 15:51:06 +0100407 rdistif_base += gicv3_redist_size(typer_val);
Andre Przywara95581b42020-09-07 14:53:58 +0100408 }
409
410 return count;
411}
Andre Przywarab8da1c62021-08-24 10:03:57 +0100412
413unsigned int gicv3_get_component_partnum(const uintptr_t gic_frame)
414{
415 unsigned int part_id;
416
417 /*
418 * The lower 8 bits of PIDR0, complemented by the lower 4 bits of
419 * PIDR1 contain a part number identifying the GIC component at a
420 * particular base address.
421 */
422 part_id = mmio_read_32(gic_frame + GICD_PIDR0_GICV3) & 0xff;
423 part_id |= (mmio_read_32(gic_frame + GICD_PIDR1_GICV3) << 8) & 0xf00;
424
425 return part_id;
426}
Manish V Badarkhe173c2962022-05-09 21:55:19 +0100427
428/*******************************************************************************
429 * Helper function to return product ID and revision of GIC
430 * @gicd_base: base address of the GIC distributor
431 * @gic_prod_id: retrieved product id of GIC
432 * @gic_rev: retrieved revision of GIC
433 ******************************************************************************/
434void gicv3_get_component_prodid_rev(const uintptr_t gicd_base,
435 unsigned int *gic_prod_id,
436 uint8_t *gic_rev)
437{
438 unsigned int gicd_iidr;
439 uint8_t gic_variant;
440
441 gicd_iidr = gicd_read_iidr(gicd_base);
442 *gic_prod_id = gicd_iidr >> IIDR_PRODUCT_ID_SHIFT;
443 *gic_prod_id &= IIDR_PRODUCT_ID_MASK;
444
445 gic_variant = gicd_iidr >> IIDR_VARIANT_SHIFT;
446 gic_variant &= IIDR_VARIANT_MASK;
447
448 *gic_rev = gicd_iidr >> IIDR_REV_SHIFT;
449 *gic_rev &= IIDR_REV_MASK;
450
451 /*
452 * pack gic variant and gic_rev in 1 byte
453 * gic_rev = gic_variant[7:4] and gic_rev[0:3]
454 */
455 *gic_rev = *gic_rev | gic_variant << 0x4;
456
457}