Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | c326c34 | 2019-01-11 11:20:10 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 7 | #ifndef ARCH_H |
| 8 | #define ARCH_H |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 11 | |
| 12 | /******************************************************************************* |
| 13 | * MIDR bit definitions |
| 14 | ******************************************************************************/ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 15 | #define MIDR_IMPL_MASK U(0xff) |
| 16 | #define MIDR_IMPL_SHIFT U(0x18) |
| 17 | #define MIDR_VAR_SHIFT U(20) |
| 18 | #define MIDR_VAR_BITS U(4) |
| 19 | #define MIDR_VAR_MASK U(0xf) |
| 20 | #define MIDR_REV_SHIFT U(0) |
| 21 | #define MIDR_REV_BITS U(4) |
| 22 | #define MIDR_REV_MASK U(0xf) |
| 23 | #define MIDR_PN_MASK U(0xfff) |
| 24 | #define MIDR_PN_SHIFT U(0x4) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 25 | |
| 26 | /******************************************************************************* |
| 27 | * MPIDR macros |
| 28 | ******************************************************************************/ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 29 | #define MPIDR_MT_MASK (ULL(1) << 24) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 30 | #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 31 | #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) |
| 32 | #define MPIDR_AFFINITY_BITS U(8) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 33 | #define MPIDR_AFFLVL_MASK ULL(0xff) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 34 | #define MPIDR_AFF0_SHIFT U(0) |
| 35 | #define MPIDR_AFF1_SHIFT U(8) |
| 36 | #define MPIDR_AFF2_SHIFT U(16) |
| 37 | #define MPIDR_AFF3_SHIFT U(32) |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 38 | #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 39 | #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 40 | #define MPIDR_AFFLVL_SHIFT U(3) |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 41 | #define MPIDR_AFFLVL0 ULL(0x0) |
| 42 | #define MPIDR_AFFLVL1 ULL(0x1) |
| 43 | #define MPIDR_AFFLVL2 ULL(0x2) |
| 44 | #define MPIDR_AFFLVL3 ULL(0x3) |
| 45 | #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n |
Vikram Kanigiri | 4e97e54 | 2015-02-26 15:25:58 +0000 | [diff] [blame] | 46 | #define MPIDR_AFFLVL0_VAL(mpidr) \ |
Antonio Nino Diaz | 34235a3 | 2018-07-11 16:45:49 +0100 | [diff] [blame] | 47 | (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) |
Vikram Kanigiri | 4e97e54 | 2015-02-26 15:25:58 +0000 | [diff] [blame] | 48 | #define MPIDR_AFFLVL1_VAL(mpidr) \ |
Antonio Nino Diaz | 34235a3 | 2018-07-11 16:45:49 +0100 | [diff] [blame] | 49 | (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) |
Vikram Kanigiri | 4e97e54 | 2015-02-26 15:25:58 +0000 | [diff] [blame] | 50 | #define MPIDR_AFFLVL2_VAL(mpidr) \ |
Antonio Nino Diaz | 34235a3 | 2018-07-11 16:45:49 +0100 | [diff] [blame] | 51 | (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) |
Vikram Kanigiri | 4e97e54 | 2015-02-26 15:25:58 +0000 | [diff] [blame] | 52 | #define MPIDR_AFFLVL3_VAL(mpidr) \ |
Antonio Nino Diaz | 34235a3 | 2018-07-11 16:45:49 +0100 | [diff] [blame] | 53 | (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) |
Soby Mathew | e2b2d8f | 2014-12-04 14:14:12 +0000 | [diff] [blame] | 54 | /* |
| 55 | * The MPIDR_MAX_AFFLVL count starts from 0. Take care to |
| 56 | * add one while using this macro to define array sizes. |
| 57 | * TODO: Support only the first 3 affinity levels for now. |
| 58 | */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 59 | #define MPIDR_MAX_AFFLVL U(2) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 60 | |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 61 | #define MPID_MASK (MPIDR_MT_MASK | \ |
| 62 | (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ |
| 63 | (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ |
| 64 | (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ |
| 65 | (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) |
| 66 | |
| 67 | #define MPIDR_AFF_ID(mpid, n) \ |
| 68 | (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) |
| 69 | |
| 70 | /* |
| 71 | * An invalid MPID. This value can be used by functions that return an MPID to |
| 72 | * indicate an error. |
| 73 | */ |
| 74 | #define INVALID_MPID U(0xFFFFFFFF) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 75 | |
| 76 | /******************************************************************************* |
Andrew Thoelke | 3f78dc3 | 2014-06-02 15:44:43 +0100 | [diff] [blame] | 77 | * Definitions for CPU system register interface to GICv3 |
| 78 | ******************************************************************************/ |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 79 | #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 |
| 80 | #define ICC_SGI1R S3_0_C12_C11_5 |
| 81 | #define ICC_SRE_EL1 S3_0_C12_C12_5 |
| 82 | #define ICC_SRE_EL2 S3_4_C12_C9_5 |
| 83 | #define ICC_SRE_EL3 S3_6_C12_C12_5 |
| 84 | #define ICC_CTLR_EL1 S3_0_C12_C12_4 |
| 85 | #define ICC_CTLR_EL3 S3_6_C12_C12_4 |
| 86 | #define ICC_PMR_EL1 S3_0_C4_C6_0 |
| 87 | #define ICC_RPR_EL1 S3_0_C12_C11_3 |
| 88 | #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 |
| 89 | #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 |
| 90 | #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 |
| 91 | #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 |
| 92 | #define ICC_IAR0_EL1 S3_0_c12_c8_0 |
| 93 | #define ICC_IAR1_EL1 S3_0_c12_c12_0 |
| 94 | #define ICC_EOIR0_EL1 S3_0_c12_c8_1 |
| 95 | #define ICC_EOIR1_EL1 S3_0_c12_c12_1 |
| 96 | #define ICC_SGI0R_EL1 S3_0_c12_c11_7 |
Andrew Thoelke | 3f78dc3 | 2014-06-02 15:44:43 +0100 | [diff] [blame] | 97 | |
| 98 | /******************************************************************************* |
Achin Gupta | c2b43af | 2013-10-31 11:27:43 +0000 | [diff] [blame] | 99 | * Generic timer memory mapped registers & offsets |
| 100 | ******************************************************************************/ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 101 | #define CNTCR_OFF U(0x000) |
Yann Gautier | 007d745 | 2019-04-17 13:47:07 +0200 | [diff] [blame] | 102 | #define CNTCV_OFF U(0x008) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 103 | #define CNTFID_OFF U(0x020) |
Achin Gupta | c2b43af | 2013-10-31 11:27:43 +0000 | [diff] [blame] | 104 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 105 | #define CNTCR_EN (U(1) << 0) |
| 106 | #define CNTCR_HDBG (U(1) << 1) |
Sandrine Bailleux | 3fa9847 | 2014-03-31 11:25:18 +0100 | [diff] [blame] | 107 | #define CNTCR_FCREQ(x) ((x) << 8) |
Achin Gupta | c2b43af | 2013-10-31 11:27:43 +0000 | [diff] [blame] | 108 | |
| 109 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 110 | * System register bit definitions |
| 111 | ******************************************************************************/ |
| 112 | /* CLIDR definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 113 | #define LOUIS_SHIFT U(21) |
| 114 | #define LOC_SHIFT U(24) |
| 115 | #define CLIDR_FIELD_WIDTH U(3) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 116 | |
| 117 | /* CSSELR definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 118 | #define LEVEL_SHIFT U(1) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 119 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 120 | /* Data cache set/way op type defines */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 121 | #define DCISW U(0x0) |
| 122 | #define DCCISW U(0x1) |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 123 | #if ERRATA_A53_827319 |
| 124 | #define DCCSW DCCISW |
| 125 | #else |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 126 | #define DCCSW U(0x2) |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 127 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 128 | |
| 129 | /* ID_AA64PFR0_EL1 definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 130 | #define ID_AA64PFR0_EL0_SHIFT U(0) |
| 131 | #define ID_AA64PFR0_EL1_SHIFT U(4) |
| 132 | #define ID_AA64PFR0_EL2_SHIFT U(8) |
| 133 | #define ID_AA64PFR0_EL3_SHIFT U(12) |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 134 | #define ID_AA64PFR0_AMU_SHIFT U(44) |
| 135 | #define ID_AA64PFR0_AMU_LENGTH U(4) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 136 | #define ID_AA64PFR0_AMU_MASK ULL(0xf) |
| 137 | #define ID_AA64PFR0_ELX_MASK ULL(0xf) |
David Cunado | ce88eee | 2017-10-20 11:30:57 +0100 | [diff] [blame] | 138 | #define ID_AA64PFR0_SVE_SHIFT U(32) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 139 | #define ID_AA64PFR0_SVE_MASK ULL(0xf) |
David Cunado | ce88eee | 2017-10-20 11:30:57 +0100 | [diff] [blame] | 140 | #define ID_AA64PFR0_SVE_LENGTH U(4) |
Jeenu Viswambharan | 2da918c | 2018-07-31 16:13:33 +0100 | [diff] [blame] | 141 | #define ID_AA64PFR0_MPAM_SHIFT U(40) |
| 142 | #define ID_AA64PFR0_MPAM_MASK ULL(0xf) |
Sathees Balya | 0911df1 | 2018-12-06 13:33:24 +0000 | [diff] [blame] | 143 | #define ID_AA64PFR0_DIT_SHIFT U(48) |
| 144 | #define ID_AA64PFR0_DIT_MASK ULL(0xf) |
| 145 | #define ID_AA64PFR0_DIT_LENGTH U(4) |
| 146 | #define ID_AA64PFR0_DIT_SUPPORTED U(1) |
Dimitris Papastamos | 43e05ec | 2018-01-02 15:53:01 +0000 | [diff] [blame] | 147 | #define ID_AA64PFR0_CSV2_SHIFT U(56) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 148 | #define ID_AA64PFR0_CSV2_MASK ULL(0xf) |
Dimitris Papastamos | 43e05ec | 2018-01-02 15:53:01 +0000 | [diff] [blame] | 149 | #define ID_AA64PFR0_CSV2_LENGTH U(4) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 150 | |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 151 | /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ |
| 152 | #define ID_AA64DFR0_PMS_SHIFT U(32) |
| 153 | #define ID_AA64DFR0_PMS_LENGTH U(4) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 154 | #define ID_AA64DFR0_PMS_MASK ULL(0xf) |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 155 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 156 | #define EL_IMPL_NONE ULL(0) |
| 157 | #define EL_IMPL_A64ONLY ULL(1) |
| 158 | #define EL_IMPL_A64_A32 ULL(2) |
Jeenu Viswambharan | 2a9b882 | 2017-02-21 14:40:44 +0000 | [diff] [blame] | 159 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 160 | #define ID_AA64PFR0_GIC_SHIFT U(24) |
| 161 | #define ID_AA64PFR0_GIC_WIDTH U(4) |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 162 | #define ID_AA64PFR0_GIC_MASK ULL(0xf) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 163 | |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 164 | /* ID_AA64ISAR1_EL1 definitions */ |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 165 | #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 166 | #define ID_AA64ISAR1_GPI_SHIFT U(28) |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 167 | #define ID_AA64ISAR1_GPI_MASK ULL(0xf) |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 168 | #define ID_AA64ISAR1_GPA_SHIFT U(24) |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 169 | #define ID_AA64ISAR1_GPA_MASK ULL(0xf) |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 170 | #define ID_AA64ISAR1_API_SHIFT U(8) |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 171 | #define ID_AA64ISAR1_API_MASK ULL(0xf) |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 172 | #define ID_AA64ISAR1_APA_SHIFT U(4) |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 173 | #define ID_AA64ISAR1_APA_MASK ULL(0xf) |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 174 | |
Antonio Nino Diaz | c326c34 | 2019-01-11 11:20:10 +0000 | [diff] [blame] | 175 | /* ID_AA64MMFR0_EL1 definitions */ |
| 176 | #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) |
| 177 | #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) |
| 178 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 179 | #define PARANGE_0000 U(32) |
| 180 | #define PARANGE_0001 U(36) |
| 181 | #define PARANGE_0010 U(40) |
| 182 | #define PARANGE_0011 U(42) |
| 183 | #define PARANGE_0100 U(44) |
| 184 | #define PARANGE_0101 U(48) |
Antonio Nino Diaz | b9ef664 | 2017-11-17 09:52:53 +0000 | [diff] [blame] | 185 | #define PARANGE_0110 U(52) |
Antonio Nino Diaz | d1beee2 | 2016-12-13 15:28:54 +0000 | [diff] [blame] | 186 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 187 | #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 188 | #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) |
| 189 | #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) |
| 190 | #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 191 | |
| 192 | #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 193 | #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) |
| 194 | #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) |
| 195 | #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 196 | |
| 197 | #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 198 | #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) |
| 199 | #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) |
| 200 | #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 201 | |
Antonio Nino Diaz | c326c34 | 2019-01-11 11:20:10 +0000 | [diff] [blame] | 202 | /* ID_AA64MMFR2_EL1 definitions */ |
| 203 | #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 |
Sathees Balya | 7415597 | 2019-01-25 11:36:01 +0000 | [diff] [blame] | 204 | |
| 205 | #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) |
| 206 | #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) |
| 207 | |
Antonio Nino Diaz | c326c34 | 2019-01-11 11:20:10 +0000 | [diff] [blame] | 208 | #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) |
| 209 | #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) |
| 210 | |
Jeenu Viswambharan | aa00aff | 2018-11-15 11:38:03 +0000 | [diff] [blame] | 211 | /* ID_AA64PFR1_EL1 definitions */ |
| 212 | #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) |
| 213 | #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) |
| 214 | |
| 215 | #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ |
| 216 | |
Alexei Fedorov | 90f2e88 | 2019-05-24 12:17:09 +0100 | [diff] [blame] | 217 | #define ID_AA64PFR1_EL1_BT_SHIFT U(0) |
| 218 | #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) |
| 219 | |
| 220 | #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ |
| 221 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 222 | /* ID_PFR1_EL1 definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 223 | #define ID_PFR1_VIRTEXT_SHIFT U(12) |
| 224 | #define ID_PFR1_VIRTEXT_MASK U(0xf) |
Antonio Nino Diaz | 34235a3 | 2018-07-11 16:45:49 +0100 | [diff] [blame] | 225 | #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 226 | & ID_PFR1_VIRTEXT_MASK) |
| 227 | |
| 228 | /* SCTLR definitions */ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 229 | #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 230 | (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ |
| 231 | (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 232 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 233 | #define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 234 | (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) |
Jens Wiklander | c93c9df | 2014-09-04 10:23:27 +0200 | [diff] [blame] | 235 | #define SCTLR_AARCH32_EL1_RES1 \ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 236 | ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ |
| 237 | (U(1) << 4) | (U(1) << 3)) |
Jens Wiklander | c93c9df | 2014-09-04 10:23:27 +0200 | [diff] [blame] | 238 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 239 | #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ |
| 240 | (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ |
| 241 | (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) |
| 242 | |
Jeenu Viswambharan | aa00aff | 2018-11-15 11:38:03 +0000 | [diff] [blame] | 243 | #define SCTLR_M_BIT (ULL(1) << 0) |
| 244 | #define SCTLR_A_BIT (ULL(1) << 1) |
| 245 | #define SCTLR_C_BIT (ULL(1) << 2) |
| 246 | #define SCTLR_SA_BIT (ULL(1) << 3) |
| 247 | #define SCTLR_SA0_BIT (ULL(1) << 4) |
| 248 | #define SCTLR_CP15BEN_BIT (ULL(1) << 5) |
| 249 | #define SCTLR_ITD_BIT (ULL(1) << 7) |
| 250 | #define SCTLR_SED_BIT (ULL(1) << 8) |
| 251 | #define SCTLR_UMA_BIT (ULL(1) << 9) |
| 252 | #define SCTLR_I_BIT (ULL(1) << 12) |
Alexei Fedorov | c31ab38 | 2019-07-10 10:49:12 +0100 | [diff] [blame] | 253 | #define SCTLR_EnDB_BIT (ULL(1) << 13) |
Jeenu Viswambharan | aa00aff | 2018-11-15 11:38:03 +0000 | [diff] [blame] | 254 | #define SCTLR_DZE_BIT (ULL(1) << 14) |
| 255 | #define SCTLR_UCT_BIT (ULL(1) << 15) |
| 256 | #define SCTLR_NTWI_BIT (ULL(1) << 16) |
| 257 | #define SCTLR_NTWE_BIT (ULL(1) << 18) |
| 258 | #define SCTLR_WXN_BIT (ULL(1) << 19) |
| 259 | #define SCTLR_UWXN_BIT (ULL(1) << 20) |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 260 | #define SCTLR_IESB_BIT (ULL(1) << 21) |
Jeenu Viswambharan | aa00aff | 2018-11-15 11:38:03 +0000 | [diff] [blame] | 261 | #define SCTLR_E0E_BIT (ULL(1) << 24) |
| 262 | #define SCTLR_EE_BIT (ULL(1) << 25) |
| 263 | #define SCTLR_UCI_BIT (ULL(1) << 26) |
Alexei Fedorov | c31ab38 | 2019-07-10 10:49:12 +0100 | [diff] [blame] | 264 | #define SCTLR_EnDA_BIT (ULL(1) << 27) |
| 265 | #define SCTLR_EnIB_BIT (ULL(1) << 30) |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 266 | #define SCTLR_EnIA_BIT (ULL(1) << 31) |
Alexei Fedorov | 90f2e88 | 2019-05-24 12:17:09 +0100 | [diff] [blame] | 267 | #define SCTLR_BT0_BIT (ULL(1) << 35) |
| 268 | #define SCTLR_BT1_BIT (ULL(1) << 36) |
| 269 | #define SCTLR_BT_BIT (ULL(1) << 36) |
Jeenu Viswambharan | aa00aff | 2018-11-15 11:38:03 +0000 | [diff] [blame] | 270 | #define SCTLR_DSSBS_BIT (ULL(1) << 44) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 271 | #define SCTLR_RESET_VAL SCTLR_EL3_RES1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 272 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 273 | /* CPACR_El1 definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 274 | #define CPACR_EL1_FPEN(x) ((x) << 20) |
| 275 | #define CPACR_EL1_FP_TRAP_EL0 U(0x1) |
| 276 | #define CPACR_EL1_FP_TRAP_ALL U(0x2) |
| 277 | #define CPACR_EL1_FP_TRAP_NONE U(0x3) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 278 | |
| 279 | /* SCR definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 280 | #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) |
Jeenu Viswambharan | f00da74 | 2017-12-08 12:13:51 +0000 | [diff] [blame] | 281 | #define SCR_FIEN_BIT (U(1) << 21) |
Jeenu Viswambharan | cbad661 | 2018-08-15 14:29:29 +0100 | [diff] [blame] | 282 | #define SCR_API_BIT (U(1) << 17) |
| 283 | #define SCR_APK_BIT (U(1) << 16) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 284 | #define SCR_TWE_BIT (U(1) << 13) |
| 285 | #define SCR_TWI_BIT (U(1) << 12) |
| 286 | #define SCR_ST_BIT (U(1) << 11) |
| 287 | #define SCR_RW_BIT (U(1) << 10) |
| 288 | #define SCR_SIF_BIT (U(1) << 9) |
| 289 | #define SCR_HCE_BIT (U(1) << 8) |
| 290 | #define SCR_SMD_BIT (U(1) << 7) |
| 291 | #define SCR_EA_BIT (U(1) << 3) |
| 292 | #define SCR_FIQ_BIT (U(1) << 2) |
| 293 | #define SCR_IRQ_BIT (U(1) << 1) |
| 294 | #define SCR_NS_BIT (U(1) << 0) |
| 295 | #define SCR_VALID_BIT_MASK U(0x2f8f) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 296 | #define SCR_RESET_VAL SCR_RES1_BITS |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 297 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 298 | /* MDCR_EL3 definitions */ |
dp-arm | 595d0d5 | 2017-02-08 11:51:50 +0000 | [diff] [blame] | 299 | #define MDCR_SPD32(x) ((x) << 14) |
Antonio Nino Diaz | 3fbd3f5 | 2019-02-18 16:55:43 +0000 | [diff] [blame] | 300 | #define MDCR_SPD32_LEGACY ULL(0x0) |
| 301 | #define MDCR_SPD32_DISABLE ULL(0x2) |
| 302 | #define MDCR_SPD32_ENABLE ULL(0x3) |
| 303 | #define MDCR_SDD_BIT (ULL(1) << 16) |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 304 | #define MDCR_NSPB(x) ((x) << 12) |
Antonio Nino Diaz | 3fbd3f5 | 2019-02-18 16:55:43 +0000 | [diff] [blame] | 305 | #define MDCR_NSPB_EL1 ULL(0x3) |
| 306 | #define MDCR_TDOSA_BIT (ULL(1) << 10) |
| 307 | #define MDCR_TDA_BIT (ULL(1) << 9) |
| 308 | #define MDCR_TPM_BIT (ULL(1) << 6) |
| 309 | #define MDCR_SCCD_BIT (ULL(1) << 23) |
| 310 | #define MDCR_EL3_RESET_VAL ULL(0x0) |
dp-arm | 595d0d5 | 2017-02-08 11:51:50 +0000 | [diff] [blame] | 311 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 312 | /* MDCR_EL2 definitions */ |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 313 | #define MDCR_EL2_TPMS (U(1) << 14) |
| 314 | #define MDCR_EL2_E2PB(x) ((x) << 12) |
| 315 | #define MDCR_EL2_E2PB_EL1 U(0x3) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 316 | #define MDCR_EL2_TDRA_BIT (U(1) << 11) |
| 317 | #define MDCR_EL2_TDOSA_BIT (U(1) << 10) |
| 318 | #define MDCR_EL2_TDA_BIT (U(1) << 9) |
| 319 | #define MDCR_EL2_TDE_BIT (U(1) << 8) |
| 320 | #define MDCR_EL2_HPME_BIT (U(1) << 7) |
| 321 | #define MDCR_EL2_TPM_BIT (U(1) << 6) |
| 322 | #define MDCR_EL2_TPMCR_BIT (U(1) << 5) |
| 323 | #define MDCR_EL2_RESET_VAL U(0x0) |
| 324 | |
| 325 | /* HSTR_EL2 definitions */ |
| 326 | #define HSTR_EL2_RESET_VAL U(0x0) |
| 327 | #define HSTR_EL2_T_MASK U(0xff) |
| 328 | |
| 329 | /* CNTHP_CTL_EL2 definitions */ |
| 330 | #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) |
| 331 | #define CNTHP_CTL_RESET_VAL U(0x0) |
| 332 | |
| 333 | /* VTTBR_EL2 definitions */ |
| 334 | #define VTTBR_RESET_VAL ULL(0x0) |
| 335 | #define VTTBR_VMID_MASK ULL(0xff) |
| 336 | #define VTTBR_VMID_SHIFT U(48) |
| 337 | #define VTTBR_BADDR_MASK ULL(0xffffffffffff) |
| 338 | #define VTTBR_BADDR_SHIFT U(0) |
dp-arm | 595d0d5 | 2017-02-08 11:51:50 +0000 | [diff] [blame] | 339 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 340 | /* HCR definitions */ |
Jeenu Viswambharan | cbad661 | 2018-08-15 14:29:29 +0100 | [diff] [blame] | 341 | #define HCR_API_BIT (ULL(1) << 41) |
| 342 | #define HCR_APK_BIT (ULL(1) << 40) |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 343 | #define HCR_TGE_BIT (ULL(1) << 27) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 344 | #define HCR_RW_SHIFT U(31) |
| 345 | #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 346 | #define HCR_AMO_BIT (ULL(1) << 5) |
| 347 | #define HCR_IMO_BIT (ULL(1) << 4) |
| 348 | #define HCR_FMO_BIT (ULL(1) << 3) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 349 | |
Gerald Lejeune | 851dc7e | 2016-03-22 11:11:46 +0100 | [diff] [blame] | 350 | /* ISR definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 351 | #define ISR_A_SHIFT U(8) |
| 352 | #define ISR_I_SHIFT U(7) |
| 353 | #define ISR_F_SHIFT U(6) |
Gerald Lejeune | 851dc7e | 2016-03-22 11:11:46 +0100 | [diff] [blame] | 354 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 355 | /* CNTHCTL_EL2 definitions */ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 356 | #define CNTHCTL_RESET_VAL U(0x0) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 357 | #define EVNTEN_BIT (U(1) << 2) |
| 358 | #define EL1PCEN_BIT (U(1) << 1) |
| 359 | #define EL1PCTEN_BIT (U(1) << 0) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 360 | |
| 361 | /* CNTKCTL_EL1 definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 362 | #define EL0PTEN_BIT (U(1) << 9) |
| 363 | #define EL0VTEN_BIT (U(1) << 8) |
| 364 | #define EL0PCTEN_BIT (U(1) << 0) |
| 365 | #define EL0VCTEN_BIT (U(1) << 1) |
| 366 | #define EVNTEN_BIT (U(1) << 2) |
| 367 | #define EVNTDIR_BIT (U(1) << 3) |
| 368 | #define EVNTI_SHIFT U(4) |
| 369 | #define EVNTI_MASK U(0xf) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 370 | |
| 371 | /* CPTR_EL3 definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 372 | #define TCPAC_BIT (U(1) << 31) |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 373 | #define TAM_BIT (U(1) << 30) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 374 | #define TTA_BIT (U(1) << 20) |
| 375 | #define TFP_BIT (U(1) << 10) |
David Cunado | ce88eee | 2017-10-20 11:30:57 +0100 | [diff] [blame] | 376 | #define CPTR_EZ_BIT (U(1) << 8) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 377 | #define CPTR_EL3_RESET_VAL U(0x0) |
| 378 | |
| 379 | /* CPTR_EL2 definitions */ |
| 380 | #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) |
| 381 | #define CPTR_EL2_TCPAC_BIT (U(1) << 31) |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 382 | #define CPTR_EL2_TAM_BIT (U(1) << 30) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 383 | #define CPTR_EL2_TTA_BIT (U(1) << 20) |
| 384 | #define CPTR_EL2_TFP_BIT (U(1) << 10) |
David Cunado | ce88eee | 2017-10-20 11:30:57 +0100 | [diff] [blame] | 385 | #define CPTR_EL2_TZ_BIT (U(1) << 8) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 386 | #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 387 | |
| 388 | /* CPSR/SPSR definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 389 | #define DAIF_FIQ_BIT (U(1) << 0) |
| 390 | #define DAIF_IRQ_BIT (U(1) << 1) |
| 391 | #define DAIF_ABT_BIT (U(1) << 2) |
| 392 | #define DAIF_DBG_BIT (U(1) << 3) |
| 393 | #define SPSR_DAIF_SHIFT U(6) |
| 394 | #define SPSR_DAIF_MASK U(0xf) |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 395 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 396 | #define SPSR_AIF_SHIFT U(6) |
| 397 | #define SPSR_AIF_MASK U(0x7) |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 398 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 399 | #define SPSR_E_SHIFT U(9) |
| 400 | #define SPSR_E_MASK U(0x1) |
| 401 | #define SPSR_E_LITTLE U(0x0) |
| 402 | #define SPSR_E_BIG U(0x1) |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 403 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 404 | #define SPSR_T_SHIFT U(5) |
| 405 | #define SPSR_T_MASK U(0x1) |
| 406 | #define SPSR_T_ARM U(0x0) |
| 407 | #define SPSR_T_THUMB U(0x1) |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 408 | |
Dimitris Papastamos | c52ebdc | 2017-12-18 13:46:21 +0000 | [diff] [blame] | 409 | #define SPSR_M_SHIFT U(4) |
| 410 | #define SPSR_M_MASK U(0x1) |
| 411 | #define SPSR_M_AARCH64 U(0x0) |
| 412 | #define SPSR_M_AARCH32 U(0x1) |
| 413 | |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 414 | #define DISABLE_ALL_EXCEPTIONS \ |
| 415 | (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) |
| 416 | |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 417 | #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) |
| 418 | |
Yatharth Kochar | ede39cb | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 419 | /* |
| 420 | * RMR_EL3 definitions |
| 421 | */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 422 | #define RMR_EL3_RR_BIT (U(1) << 1) |
| 423 | #define RMR_EL3_AA64_BIT (U(1) << 0) |
Yatharth Kochar | ede39cb | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 424 | |
| 425 | /* |
| 426 | * HI-VECTOR address for AArch32 state |
| 427 | */ |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 428 | #define HI_VECTOR_BASE U(0xFFFF0000) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 429 | |
| 430 | /* |
| 431 | * TCR defintions |
| 432 | */ |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 433 | #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 434 | #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 435 | #define TCR_EL1_IPS_SHIFT U(32) |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 436 | #define TCR_EL2_PS_SHIFT U(16) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 437 | #define TCR_EL3_PS_SHIFT U(16) |
Lin Ma | 741a382 | 2014-06-27 16:56:30 -0700 | [diff] [blame] | 438 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 439 | #define TCR_TxSZ_MIN ULL(16) |
| 440 | #define TCR_TxSZ_MAX ULL(39) |
Sathees Balya | 7415597 | 2019-01-25 11:36:01 +0000 | [diff] [blame] | 441 | #define TCR_TxSZ_MAX_TTST ULL(48) |
Antonio Nino Diaz | d48ae61 | 2016-08-02 09:21:41 +0100 | [diff] [blame] | 442 | |
Antonio Nino Diaz | 37f97a5 | 2019-03-27 11:10:31 +0000 | [diff] [blame] | 443 | #define TCR_T0SZ_SHIFT U(0) |
| 444 | #define TCR_T1SZ_SHIFT U(16) |
| 445 | |
Lin Ma | 741a382 | 2014-06-27 16:56:30 -0700 | [diff] [blame] | 446 | /* (internal) physical address size bits in EL3/EL1 */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 447 | #define TCR_PS_BITS_4GB ULL(0x0) |
| 448 | #define TCR_PS_BITS_64GB ULL(0x1) |
| 449 | #define TCR_PS_BITS_1TB ULL(0x2) |
| 450 | #define TCR_PS_BITS_4TB ULL(0x3) |
| 451 | #define TCR_PS_BITS_16TB ULL(0x4) |
| 452 | #define TCR_PS_BITS_256TB ULL(0x5) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 453 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 454 | #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) |
| 455 | #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) |
| 456 | #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) |
| 457 | #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) |
| 458 | #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) |
| 459 | #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 460 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 461 | #define TCR_RGN_INNER_NC (ULL(0x0) << 8) |
| 462 | #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) |
| 463 | #define TCR_RGN_INNER_WT (ULL(0x2) << 8) |
| 464 | #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 465 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 466 | #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) |
| 467 | #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) |
| 468 | #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) |
| 469 | #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 470 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 471 | #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) |
| 472 | #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) |
| 473 | #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 474 | |
Antonio Nino Diaz | 37f97a5 | 2019-03-27 11:10:31 +0000 | [diff] [blame] | 475 | #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) |
| 476 | #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) |
| 477 | #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) |
| 478 | #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) |
| 479 | |
| 480 | #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) |
| 481 | #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) |
| 482 | #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) |
| 483 | #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) |
| 484 | |
| 485 | #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) |
| 486 | #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) |
| 487 | #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) |
| 488 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 489 | #define TCR_TG0_SHIFT U(14) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 490 | #define TCR_TG0_MASK ULL(3) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 491 | #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) |
| 492 | #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) |
| 493 | #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) |
| 494 | |
Antonio Nino Diaz | 37f97a5 | 2019-03-27 11:10:31 +0000 | [diff] [blame] | 495 | #define TCR_TG1_SHIFT U(30) |
| 496 | #define TCR_TG1_MASK ULL(3) |
| 497 | #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) |
| 498 | #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) |
| 499 | #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) |
| 500 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 501 | #define TCR_EPD0_BIT (ULL(1) << 7) |
| 502 | #define TCR_EPD1_BIT (ULL(1) << 23) |
Antonio Nino Diaz | c8274a8 | 2017-09-15 10:30:34 +0100 | [diff] [blame] | 503 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 504 | #define MODE_SP_SHIFT U(0x0) |
| 505 | #define MODE_SP_MASK U(0x1) |
| 506 | #define MODE_SP_EL0 U(0x0) |
| 507 | #define MODE_SP_ELX U(0x1) |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 508 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 509 | #define MODE_RW_SHIFT U(0x4) |
| 510 | #define MODE_RW_MASK U(0x1) |
| 511 | #define MODE_RW_64 U(0x0) |
| 512 | #define MODE_RW_32 U(0x1) |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 513 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 514 | #define MODE_EL_SHIFT U(0x2) |
| 515 | #define MODE_EL_MASK U(0x3) |
| 516 | #define MODE_EL3 U(0x3) |
| 517 | #define MODE_EL2 U(0x2) |
| 518 | #define MODE_EL1 U(0x1) |
| 519 | #define MODE_EL0 U(0x0) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 520 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 521 | #define MODE32_SHIFT U(0) |
| 522 | #define MODE32_MASK U(0xf) |
| 523 | #define MODE32_usr U(0x0) |
| 524 | #define MODE32_fiq U(0x1) |
| 525 | #define MODE32_irq U(0x2) |
| 526 | #define MODE32_svc U(0x3) |
| 527 | #define MODE32_mon U(0x6) |
| 528 | #define MODE32_abt U(0x7) |
| 529 | #define MODE32_hyp U(0xa) |
| 530 | #define MODE32_und U(0xb) |
| 531 | #define MODE32_sys U(0xf) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 532 | |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 533 | #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) |
| 534 | #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) |
| 535 | #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) |
| 536 | #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 537 | |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 538 | #define SPSR_64(el, sp, daif) \ |
Antonio Nino Diaz | e881147 | 2018-04-17 15:10:18 +0100 | [diff] [blame] | 539 | ((MODE_RW_64 << MODE_RW_SHIFT) | \ |
| 540 | (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ |
| 541 | (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ |
| 542 | (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 543 | |
| 544 | #define SPSR_MODE32(mode, isa, endian, aif) \ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 545 | ((MODE_RW_32 << MODE_RW_SHIFT) | \ |
| 546 | (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ |
| 547 | (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ |
| 548 | (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ |
| 549 | (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 550 | |
Dan Handley | 0cdebbd | 2015-03-30 17:15:16 +0100 | [diff] [blame] | 551 | /* |
Isla Mitchell | c4a1a07 | 2017-08-07 11:20:13 +0100 | [diff] [blame] | 552 | * TTBR Definitions |
| 553 | */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 554 | #define TTBR_CNP_BIT ULL(0x1) |
Isla Mitchell | c4a1a07 | 2017-08-07 11:20:13 +0100 | [diff] [blame] | 555 | |
| 556 | /* |
Dan Handley | 0cdebbd | 2015-03-30 17:15:16 +0100 | [diff] [blame] | 557 | * CTR_EL0 definitions |
| 558 | */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 559 | #define CTR_CWG_SHIFT U(24) |
| 560 | #define CTR_CWG_MASK U(0xf) |
| 561 | #define CTR_ERG_SHIFT U(20) |
| 562 | #define CTR_ERG_MASK U(0xf) |
| 563 | #define CTR_DMINLINE_SHIFT U(16) |
| 564 | #define CTR_DMINLINE_MASK U(0xf) |
| 565 | #define CTR_L1IP_SHIFT U(14) |
| 566 | #define CTR_L1IP_MASK U(0x3) |
| 567 | #define CTR_IMINLINE_SHIFT U(0) |
| 568 | #define CTR_IMINLINE_MASK U(0xf) |
Dan Handley | 0cdebbd | 2015-03-30 17:15:16 +0100 | [diff] [blame] | 569 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 570 | #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 571 | |
Achin Gupta | 405406d | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 572 | /* Physical timer control register bit fields shifts and masks */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 573 | #define CNTP_CTL_ENABLE_SHIFT U(0) |
| 574 | #define CNTP_CTL_IMASK_SHIFT U(1) |
| 575 | #define CNTP_CTL_ISTATUS_SHIFT U(2) |
Achin Gupta | 405406d | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 576 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 577 | #define CNTP_CTL_ENABLE_MASK U(1) |
| 578 | #define CNTP_CTL_IMASK_MASK U(1) |
| 579 | #define CNTP_CTL_ISTATUS_MASK U(1) |
Achin Gupta | 405406d | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 580 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 581 | /* Exception Syndrome register bits and bobs */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 582 | #define ESR_EC_SHIFT U(26) |
| 583 | #define ESR_EC_MASK U(0x3f) |
| 584 | #define ESR_EC_LENGTH U(6) |
| 585 | #define EC_UNKNOWN U(0x0) |
| 586 | #define EC_WFE_WFI U(0x1) |
| 587 | #define EC_AARCH32_CP15_MRC_MCR U(0x3) |
| 588 | #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) |
| 589 | #define EC_AARCH32_CP14_MRC_MCR U(0x5) |
| 590 | #define EC_AARCH32_CP14_LDC_STC U(0x6) |
| 591 | #define EC_FP_SIMD U(0x7) |
| 592 | #define EC_AARCH32_CP10_MRC U(0x8) |
| 593 | #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) |
| 594 | #define EC_ILLEGAL U(0xe) |
| 595 | #define EC_AARCH32_SVC U(0x11) |
| 596 | #define EC_AARCH32_HVC U(0x12) |
| 597 | #define EC_AARCH32_SMC U(0x13) |
| 598 | #define EC_AARCH64_SVC U(0x15) |
| 599 | #define EC_AARCH64_HVC U(0x16) |
| 600 | #define EC_AARCH64_SMC U(0x17) |
| 601 | #define EC_AARCH64_SYS U(0x18) |
| 602 | #define EC_IABORT_LOWER_EL U(0x20) |
| 603 | #define EC_IABORT_CUR_EL U(0x21) |
| 604 | #define EC_PC_ALIGN U(0x22) |
| 605 | #define EC_DABORT_LOWER_EL U(0x24) |
| 606 | #define EC_DABORT_CUR_EL U(0x25) |
| 607 | #define EC_SP_ALIGN U(0x26) |
| 608 | #define EC_AARCH32_FP U(0x28) |
| 609 | #define EC_AARCH64_FP U(0x2c) |
| 610 | #define EC_SERROR U(0x2f) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 611 | |
Jeenu Viswambharan | 96c7df0 | 2017-11-30 12:54:15 +0000 | [diff] [blame] | 612 | /* |
| 613 | * External Abort bit in Instruction and Data Aborts synchronous exception |
| 614 | * syndromes. |
| 615 | */ |
| 616 | #define ESR_ISS_EABORT_EA_BIT U(9) |
| 617 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 618 | #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 619 | |
Vignesh Radhakrishnan | b4a7294 | 2017-03-03 10:58:05 -0800 | [diff] [blame] | 620 | /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 621 | #define RMR_RESET_REQUEST_SHIFT U(0x1) |
| 622 | #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) |
Vignesh Radhakrishnan | b4a7294 | 2017-03-03 10:58:05 -0800 | [diff] [blame] | 623 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 624 | /******************************************************************************* |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 625 | * Definitions of register offsets, fields and macros for CPU system |
| 626 | * instructions. |
| 627 | ******************************************************************************/ |
| 628 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 629 | #define TLBI_ADDR_SHIFT U(12) |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 630 | #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) |
| 631 | #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) |
| 632 | |
| 633 | /******************************************************************************* |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 634 | * Definitions of register offsets and fields in the CNTCTLBase Frame of the |
| 635 | * system level implementation of the Generic Timer. |
| 636 | ******************************************************************************/ |
Soby Mathew | 2d9f795 | 2018-06-11 16:21:30 +0100 | [diff] [blame] | 637 | #define CNTCTLBASE_CNTFRQ U(0x0) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 638 | #define CNTNSAR U(0x4) |
| 639 | #define CNTNSAR_NS_SHIFT(x) (x) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 640 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 641 | #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) |
| 642 | #define CNTACR_RPCT_SHIFT U(0x0) |
| 643 | #define CNTACR_RVCT_SHIFT U(0x1) |
| 644 | #define CNTACR_RFRQ_SHIFT U(0x2) |
| 645 | #define CNTACR_RVOFF_SHIFT U(0x3) |
| 646 | #define CNTACR_RWVT_SHIFT U(0x4) |
| 647 | #define CNTACR_RWPT_SHIFT U(0x5) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 648 | |
Soby Mathew | 2d9f795 | 2018-06-11 16:21:30 +0100 | [diff] [blame] | 649 | /******************************************************************************* |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 650 | * Definitions of register offsets and fields in the CNTBaseN Frame of the |
Soby Mathew | 2d9f795 | 2018-06-11 16:21:30 +0100 | [diff] [blame] | 651 | * system level implementation of the Generic Timer. |
| 652 | ******************************************************************************/ |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 653 | /* Physical Count register. */ |
| 654 | #define CNTPCT_LO U(0x0) |
| 655 | /* Counter Frequency register. */ |
| 656 | #define CNTBASEN_CNTFRQ U(0x10) |
| 657 | /* Physical Timer CompareValue register. */ |
| 658 | #define CNTP_CVAL_LO U(0x20) |
| 659 | /* Physical Timer Control register. */ |
| 660 | #define CNTP_CTL U(0x2c) |
Soby Mathew | 2d9f795 | 2018-06-11 16:21:30 +0100 | [diff] [blame] | 661 | |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 662 | /* PMCR_EL0 definitions */ |
David Cunado | 4168f2f | 2017-10-02 17:41:39 +0100 | [diff] [blame] | 663 | #define PMCR_EL0_RESET_VAL U(0x0) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 664 | #define PMCR_EL0_N_SHIFT U(11) |
| 665 | #define PMCR_EL0_N_MASK U(0x1f) |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 666 | #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) |
David Cunado | 4168f2f | 2017-10-02 17:41:39 +0100 | [diff] [blame] | 667 | #define PMCR_EL0_LC_BIT (U(1) << 6) |
| 668 | #define PMCR_EL0_DP_BIT (U(1) << 5) |
| 669 | #define PMCR_EL0_X_BIT (U(1) << 4) |
| 670 | #define PMCR_EL0_D_BIT (U(1) << 3) |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 671 | |
Isla Mitchell | 02c6307 | 2017-07-21 14:44:36 +0100 | [diff] [blame] | 672 | /******************************************************************************* |
David Cunado | ce88eee | 2017-10-20 11:30:57 +0100 | [diff] [blame] | 673 | * Definitions for system register interface to SVE |
| 674 | ******************************************************************************/ |
| 675 | #define ZCR_EL3 S3_6_C1_C2_0 |
| 676 | #define ZCR_EL2 S3_4_C1_C2_0 |
| 677 | |
| 678 | /* ZCR_EL3 definitions */ |
| 679 | #define ZCR_EL3_LEN_MASK U(0xf) |
| 680 | |
| 681 | /* ZCR_EL2 definitions */ |
| 682 | #define ZCR_EL2_LEN_MASK U(0xf) |
| 683 | |
| 684 | /******************************************************************************* |
Isla Mitchell | 02c6307 | 2017-07-21 14:44:36 +0100 | [diff] [blame] | 685 | * Definitions of MAIR encodings for device and normal memory |
| 686 | ******************************************************************************/ |
| 687 | /* |
| 688 | * MAIR encodings for device memory attributes. |
| 689 | */ |
| 690 | #define MAIR_DEV_nGnRnE ULL(0x0) |
| 691 | #define MAIR_DEV_nGnRE ULL(0x4) |
| 692 | #define MAIR_DEV_nGRE ULL(0x8) |
| 693 | #define MAIR_DEV_GRE ULL(0xc) |
| 694 | |
| 695 | /* |
| 696 | * MAIR encodings for normal memory attributes. |
| 697 | * |
| 698 | * Cache Policy |
| 699 | * WT: Write Through |
| 700 | * WB: Write Back |
| 701 | * NC: Non-Cacheable |
| 702 | * |
| 703 | * Transient Hint |
| 704 | * NTR: Non-Transient |
| 705 | * TR: Transient |
| 706 | * |
| 707 | * Allocation Policy |
| 708 | * RA: Read Allocate |
| 709 | * WA: Write Allocate |
| 710 | * RWA: Read and Write Allocate |
| 711 | * NA: No Allocation |
| 712 | */ |
| 713 | #define MAIR_NORM_WT_TR_WA ULL(0x1) |
| 714 | #define MAIR_NORM_WT_TR_RA ULL(0x2) |
| 715 | #define MAIR_NORM_WT_TR_RWA ULL(0x3) |
| 716 | #define MAIR_NORM_NC ULL(0x4) |
| 717 | #define MAIR_NORM_WB_TR_WA ULL(0x5) |
| 718 | #define MAIR_NORM_WB_TR_RA ULL(0x6) |
| 719 | #define MAIR_NORM_WB_TR_RWA ULL(0x7) |
| 720 | #define MAIR_NORM_WT_NTR_NA ULL(0x8) |
| 721 | #define MAIR_NORM_WT_NTR_WA ULL(0x9) |
| 722 | #define MAIR_NORM_WT_NTR_RA ULL(0xa) |
| 723 | #define MAIR_NORM_WT_NTR_RWA ULL(0xb) |
| 724 | #define MAIR_NORM_WB_NTR_NA ULL(0xc) |
| 725 | #define MAIR_NORM_WB_NTR_WA ULL(0xd) |
| 726 | #define MAIR_NORM_WB_NTR_RA ULL(0xe) |
| 727 | #define MAIR_NORM_WB_NTR_RWA ULL(0xf) |
| 728 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 729 | #define MAIR_NORM_OUTER_SHIFT U(4) |
Isla Mitchell | 02c6307 | 2017-07-21 14:44:36 +0100 | [diff] [blame] | 730 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 731 | #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ |
| 732 | ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) |
Isla Mitchell | 02c6307 | 2017-07-21 14:44:36 +0100 | [diff] [blame] | 733 | |
Jeenu Viswambharan | 1dc771b | 2017-10-19 09:15:15 +0100 | [diff] [blame] | 734 | /* PAR_EL1 fields */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 735 | #define PAR_F_SHIFT U(0) |
| 736 | #define PAR_F_MASK ULL(0x1) |
| 737 | #define PAR_ADDR_SHIFT U(12) |
| 738 | #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ |
Jeenu Viswambharan | 1dc771b | 2017-10-19 09:15:15 +0100 | [diff] [blame] | 739 | |
Dimitris Papastamos | 5bdbb47 | 2017-10-13 12:06:06 +0100 | [diff] [blame] | 740 | /******************************************************************************* |
| 741 | * Definitions for system register interface to SPE |
| 742 | ******************************************************************************/ |
| 743 | #define PMBLIMITR_EL1 S3_0_C9_C10_0 |
| 744 | |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 745 | /******************************************************************************* |
Jeenu Viswambharan | 2da918c | 2018-07-31 16:13:33 +0100 | [diff] [blame] | 746 | * Definitions for system register interface to MPAM |
| 747 | ******************************************************************************/ |
| 748 | #define MPAMIDR_EL1 S3_0_C10_C4_4 |
| 749 | #define MPAM2_EL2 S3_4_C10_C5_0 |
| 750 | #define MPAMHCR_EL2 S3_4_C10_C4_0 |
| 751 | #define MPAM3_EL3 S3_6_C10_C5_0 |
| 752 | |
| 753 | /******************************************************************************* |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 754 | * Definitions for system register interface to AMU for ARMv8.4 onwards |
| 755 | ******************************************************************************/ |
| 756 | #define AMCR_EL0 S3_3_C13_C2_0 |
| 757 | #define AMCFGR_EL0 S3_3_C13_C2_1 |
| 758 | #define AMCGCR_EL0 S3_3_C13_C2_2 |
| 759 | #define AMUSERENR_EL0 S3_3_C13_C2_3 |
| 760 | #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 |
| 761 | #define AMCNTENSET0_EL0 S3_3_C13_C2_5 |
| 762 | #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 |
| 763 | #define AMCNTENSET1_EL0 S3_3_C13_C3_1 |
| 764 | |
| 765 | /* Activity Monitor Group 0 Event Counter Registers */ |
| 766 | #define AMEVCNTR00_EL0 S3_3_C13_C4_0 |
| 767 | #define AMEVCNTR01_EL0 S3_3_C13_C4_1 |
| 768 | #define AMEVCNTR02_EL0 S3_3_C13_C4_2 |
| 769 | #define AMEVCNTR03_EL0 S3_3_C13_C4_3 |
| 770 | |
| 771 | /* Activity Monitor Group 0 Event Type Registers */ |
| 772 | #define AMEVTYPER00_EL0 S3_3_C13_C6_0 |
| 773 | #define AMEVTYPER01_EL0 S3_3_C13_C6_1 |
| 774 | #define AMEVTYPER02_EL0 S3_3_C13_C6_2 |
| 775 | #define AMEVTYPER03_EL0 S3_3_C13_C6_3 |
| 776 | |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 777 | /* Activity Monitor Group 1 Event Counter Registers */ |
| 778 | #define AMEVCNTR10_EL0 S3_3_C13_C12_0 |
| 779 | #define AMEVCNTR11_EL0 S3_3_C13_C12_1 |
| 780 | #define AMEVCNTR12_EL0 S3_3_C13_C12_2 |
| 781 | #define AMEVCNTR13_EL0 S3_3_C13_C12_3 |
| 782 | #define AMEVCNTR14_EL0 S3_3_C13_C12_4 |
| 783 | #define AMEVCNTR15_EL0 S3_3_C13_C12_5 |
| 784 | #define AMEVCNTR16_EL0 S3_3_C13_C12_6 |
| 785 | #define AMEVCNTR17_EL0 S3_3_C13_C12_7 |
| 786 | #define AMEVCNTR18_EL0 S3_3_C13_C13_0 |
| 787 | #define AMEVCNTR19_EL0 S3_3_C13_C13_1 |
| 788 | #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 |
| 789 | #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 |
| 790 | #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 |
| 791 | #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 |
| 792 | #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 |
| 793 | #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 |
| 794 | |
| 795 | /* Activity Monitor Group 1 Event Type Registers */ |
| 796 | #define AMEVTYPER10_EL0 S3_3_C13_C14_0 |
| 797 | #define AMEVTYPER11_EL0 S3_3_C13_C14_1 |
| 798 | #define AMEVTYPER12_EL0 S3_3_C13_C14_2 |
| 799 | #define AMEVTYPER13_EL0 S3_3_C13_C14_3 |
| 800 | #define AMEVTYPER14_EL0 S3_3_C13_C14_4 |
| 801 | #define AMEVTYPER15_EL0 S3_3_C13_C14_5 |
| 802 | #define AMEVTYPER16_EL0 S3_3_C13_C14_6 |
| 803 | #define AMEVTYPER17_EL0 S3_3_C13_C14_7 |
| 804 | #define AMEVTYPER18_EL0 S3_3_C13_C15_0 |
| 805 | #define AMEVTYPER19_EL0 S3_3_C13_C15_1 |
| 806 | #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 |
| 807 | #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 |
| 808 | #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 |
| 809 | #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 |
| 810 | #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 |
| 811 | #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 |
| 812 | |
| 813 | /* AMCGCR_EL0 definitions */ |
| 814 | #define AMCGCR_EL0_CG1NC_SHIFT U(8) |
| 815 | #define AMCGCR_EL0_CG1NC_LENGTH U(8) |
| 816 | #define AMCGCR_EL0_CG1NC_MASK U(0xff) |
| 817 | |
Jeenu Viswambharan | 2da918c | 2018-07-31 16:13:33 +0100 | [diff] [blame] | 818 | /* MPAM register definitions */ |
| 819 | #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) |
Louis Mayencourt | bdfa103 | 2019-02-11 11:25:50 +0000 | [diff] [blame] | 820 | #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) |
| 821 | |
| 822 | #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) |
| 823 | #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) |
Jeenu Viswambharan | 2da918c | 2018-07-31 16:13:33 +0100 | [diff] [blame] | 824 | |
| 825 | #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) |
| 826 | |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 827 | /******************************************************************************* |
| 828 | * RAS system registers |
Sathees Balya | 0911df1 | 2018-12-06 13:33:24 +0000 | [diff] [blame] | 829 | ******************************************************************************/ |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 830 | #define DISR_EL1 S3_0_C12_C1_1 |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 831 | #define DISR_A_BIT U(31) |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 832 | |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 833 | #define ERRIDR_EL1 S3_0_C5_C3_0 |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 834 | #define ERRIDR_MASK U(0xffff) |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 835 | |
| 836 | #define ERRSELR_EL1 S3_0_C5_C3_1 |
| 837 | |
| 838 | /* System register access to Standard Error Record registers */ |
| 839 | #define ERXFR_EL1 S3_0_C5_C4_0 |
| 840 | #define ERXCTLR_EL1 S3_0_C5_C4_1 |
| 841 | #define ERXSTATUS_EL1 S3_0_C5_C4_2 |
| 842 | #define ERXADDR_EL1 S3_0_C5_C4_3 |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 843 | #define ERXPFGF_EL1 S3_0_C5_C4_4 |
| 844 | #define ERXPFGCTL_EL1 S3_0_C5_C4_5 |
| 845 | #define ERXPFGCDN_EL1 S3_0_C5_C4_6 |
Jan Dabros | 82ef8bf | 2018-08-30 13:52:23 +0200 | [diff] [blame] | 846 | #define ERXMISC0_EL1 S3_0_C5_C5_0 |
| 847 | #define ERXMISC1_EL1 S3_0_C5_C5_1 |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 848 | |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 849 | #define ERXCTLR_ED_BIT (U(1) << 0) |
| 850 | #define ERXCTLR_UE_BIT (U(1) << 4) |
| 851 | |
| 852 | #define ERXPFGCTL_UC_BIT (U(1) << 1) |
| 853 | #define ERXPFGCTL_UEU_BIT (U(1) << 2) |
| 854 | #define ERXPFGCTL_CDEN_BIT (U(1) << 31) |
| 855 | |
| 856 | /******************************************************************************* |
| 857 | * Armv8.3 Pointer Authentication Registers |
Sathees Balya | 0911df1 | 2018-12-06 13:33:24 +0000 | [diff] [blame] | 858 | ******************************************************************************/ |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 859 | #define APIAKeyLo_EL1 S3_0_C2_C1_0 |
| 860 | #define APIAKeyHi_EL1 S3_0_C2_C1_1 |
| 861 | #define APIBKeyLo_EL1 S3_0_C2_C1_2 |
| 862 | #define APIBKeyHi_EL1 S3_0_C2_C1_3 |
| 863 | #define APDAKeyLo_EL1 S3_0_C2_C2_0 |
| 864 | #define APDAKeyHi_EL1 S3_0_C2_C2_1 |
| 865 | #define APDBKeyLo_EL1 S3_0_C2_C2_2 |
| 866 | #define APDBKeyHi_EL1 S3_0_C2_C2_3 |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 867 | #define APGAKeyLo_EL1 S3_0_C2_C3_0 |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 868 | #define APGAKeyHi_EL1 S3_0_C2_C3_1 |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 869 | |
Sathees Balya | 0911df1 | 2018-12-06 13:33:24 +0000 | [diff] [blame] | 870 | /******************************************************************************* |
| 871 | * Armv8.4 Data Independent Timing Registers |
| 872 | ******************************************************************************/ |
| 873 | #define DIT S3_3_C4_C2_5 |
| 874 | #define DIT_BIT BIT(24) |
| 875 | |
John Tsichritzis | 1f9ff49 | 2019-03-04 16:41:26 +0000 | [diff] [blame] | 876 | /******************************************************************************* |
| 877 | * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field |
| 878 | ******************************************************************************/ |
| 879 | #define SSBS S3_3_C4_C2_6 |
| 880 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 881 | #endif /* ARCH_H */ |