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Dan Handley610e7e12018-03-01 18:44:00 +00001Arm CPU Specific Build Macros
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002=============================
3
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004This document describes the various build options present in the CPU specific
5operations framework to enable errata workarounds and to enable optimizations
6for a specific CPU on a platform.
7
Dimitris Papastamos446f7f12017-11-30 14:53:53 +00008Security Vulnerability Workarounds
9----------------------------------
10
Dan Handley610e7e12018-03-01 18:44:00 +000011TF-A exports a series of build flags which control which security
12vulnerability workarounds should be applied at runtime.
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000013
14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for
Dimitris Papastamos6d1f4992018-03-28 12:06:40 +010015 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none
16 of the PEs in the system need the workaround. Setting this flag to 0 provides
17 no performance benefit for non-affected platforms, it just helps to comply
18 with the recommendation in the spec regarding workaround discovery.
19 Defaults to 1.
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000020
Dimitris Papastamose6625ec2018-04-05 14:38:26 +010021- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for
22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep
23 the default value of 1 even on platforms that are unaffected by
24 CVE-2018-3639, in order to comply with the recommendation in the spec
25 regarding workaround discovery.
26
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010027- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for
28 `CVE-2018-3639`_. This build option should be set to 1 if the target
29 platform contains at least 1 CPU that requires dynamic mitigation.
30 Defaults to 0.
31
Douglas Raillardd7c21b72017-06-28 15:23:03 +010032CPU Errata Workarounds
33----------------------
34
Dan Handley610e7e12018-03-01 18:44:00 +000035TF-A exports a series of build flags which control the errata workarounds that
36are applied to each CPU by the reset handler. The errata details can be found
37in the CPU specific errata documents published by Arm:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010038
39- `Cortex-A53 MPCore Software Developers Errata Notice`_
40- `Cortex-A57 MPCore Software Developers Errata Notice`_
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +010041- `Cortex-A72 MPCore Software Developers Errata Notice`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +010042
43The errata workarounds are implemented for a particular revision or a set of
44processor revisions. This is checked by the reset handler at runtime. Each
45errata workaround is identified by its ``ID`` as specified in the processor's
46errata notice document. The format of the define used to enable/disable the
47errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name``
48is for example ``A57`` for the ``Cortex_A57`` CPU.
49
50Refer to the section *CPU errata status reporting* in
Eleanor Bonnici0c9bd272017-08-02 16:35:04 +010051`Firmware Design guide`_ for information on how to write errata workaround
52functions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010053
54All workarounds are disabled by default. The platform is responsible for
55enabling these workarounds according to its requirement by defining the
56errata workaround build flags in the platform specific makefile. In case
57these workarounds are enabled for the wrong CPU revision then the errata
58workaround is not applied. In the DEBUG build, this is indicated by
59printing a warning to the crash console.
60
61In the current implementation, a platform which has more than 1 variant
62with different revisions of a processor has no runtime mechanism available
63for it to specify which errata workarounds should be enabled or not.
64
John Tsichritzis4daa1de2018-07-23 09:11:59 +010065The value of the build flags is 0 by default, that is, disabled. A value of 1
66will enable it.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010067
Joel Hutton26d16762019-04-10 12:52:52 +010068For Cortex-A9, the following errata build flags are defined :
69
Louis Mayencourte6469d52019-04-18 12:11:25 +010070- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9
Joel Hutton26d16762019-04-10 12:52:52 +010071 CPU. This needs to be enabled for all revisions of the CPU.
72
Ambroise Vincentd4a51eb2019-03-04 16:56:26 +000073For Cortex-A15, the following errata build flags are defined :
74
75- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
76 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
77
Ambroise Vincent68b38122019-03-05 09:54:21 +000078- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15
79 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
80
Ambroise Vincent8cf9eef2019-02-28 16:23:53 +000081For Cortex-A17, the following errata build flags are defined :
82
83- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17
84 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
85
Ambroise Vincentfa5c9512019-03-04 13:20:56 +000086- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17
87 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
88
Louis Mayencourt8a061272019-04-05 16:25:25 +010089For Cortex-A35, the following errata build flags are defined :
90
91- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35
92 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.
93
John Tsichritzis4daa1de2018-07-23 09:11:59 +010094For Cortex-A53, the following errata build flags are defined :
Douglas Raillardd7c21b72017-06-28 15:23:03 +010095
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +000096- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all
97 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
98
99- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all
100 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
101
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100102- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
103 CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
104
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000105- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all
106 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
107
Douglas Raillardb52353a2017-07-17 14:14:52 +0100108- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
109 link time to Cortex-A53 CPU. This needs to be enabled for some variants of
110 revision <= r0p4. This workaround can lead the linker to create ``*.stub``
111 sections.
112
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100113- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53
114 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
115 r0p4 and onwards, this errata is enabled by default in hardware.
116
Douglas Raillardb52353a2017-07-17 14:14:52 +0100117- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time
118 to Cortex-A53 CPU. This needs to be enabled for some variants of revision
119 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections
120 which are 4kB aligned.
121
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100122- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53
123 CPUs. Though the erratum is present in every revision of the CPU,
124 this workaround is only applied to CPUs from r0p3 onwards, which feature
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100125 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100126 Earlier revisions of the CPU have other errata which require the same
127 workaround in software, so they should be covered anyway.
128
Ambroise Vincent7927fa02019-02-21 16:20:43 +0000129For Cortex-A55, the following errata build flags are defined :
130
131- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55
132 CPU. This needs to be enabled only for revision r0p0 of the CPU.
133
Ambroise Vincent6f319602019-02-21 16:25:37 +0000134- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55
135 CPU. This needs to be enabled only for revision r0p0 of the CPU.
136
Ambroise Vincent6a77f052019-02-21 16:27:34 +0000137- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55
138 CPU. This needs to be enabled only for revision r0p0 of the CPU.
139
Ambroise Vincentdd961f72019-02-21 16:29:16 +0000140- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55
141 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
142
Ambroise Vincenta1d64462019-02-21 16:29:50 +0000143- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55
144 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
145
Ambroise Vincentb72fe7a2019-05-28 09:52:48 +0100146- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55
147 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
148
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100149For Cortex-A57, the following errata build flags are defined :
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100150
151- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
152 CPU. This needs to be enabled only for revision r0p0 of the CPU.
153
154- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
155 CPU. This needs to be enabled only for revision r0p0 of the CPU.
156
157- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
158 CPU. This needs to be enabled only for revision r0p0 of the CPU.
159
Ambroise Vincent1b0db762019-02-21 16:35:07 +0000160- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
161 CPU. This needs to be enabled only for revision r0p0 of the CPU.
162
Ambroise Vincentaa2c0292019-02-21 16:35:49 +0000163- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57
164 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
165
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100166- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
167 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
168
169- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
170 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
171
172- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57
173 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
174
175- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57
176 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
177
178- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
179 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
180
Eleanor Bonnici0c9bd272017-08-02 16:35:04 +0100181- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
182 CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
183
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100184
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100185For Cortex-A72, the following errata build flags are defined :
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100186
187- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
188 CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
189
Louis Mayencourt4405de62019-02-21 16:38:16 +0000190For Cortex-A73, the following errata build flags are defined :
191
Louis Mayencourtd69722c2019-02-27 14:24:16 +0000192- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73
193 CPU. This needs to be enabled only for revision r0p0 of the CPU.
194
Louis Mayencourt4405de62019-02-21 16:38:16 +0000195- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73
196 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
197
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000198For Cortex-A75, the following errata build flags are defined :
199
200- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
201 CPU. This needs to be enabled only for revision r0p0 of the CPU.
202
Louis Mayencourt8d868702019-02-25 14:57:57 +0000203- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
204 CPU. This needs to be enabled only for revision r0p0 of the CPU.
205
Louis Mayencourt09924472019-02-21 17:35:07 +0000206For Cortex-A76, the following errata build flags are defined :
207
Louis Mayencourt59fa2182019-02-25 15:17:44 +0000208- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76
209 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
210
Louis Mayencourt09924472019-02-21 17:35:07 +0000211- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76
212 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
213
Louis Mayencourtadda9d42019-02-25 11:37:38 +0000214- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
215 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
216
Soby Mathew1d3ba1c2019-05-01 09:43:18 +0100217- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76
218 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
219
220- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76
221 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
222
223- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76
224 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
225
226- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
227 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
228
Andre Przywarab9347402019-05-20 14:57:06 +0100229- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
230 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
231
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100232DSU Errata Workarounds
233----------------------
234
235Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
236Shared Unit) errata. The DSU errata details can be found in the respective Arm
237documentation:
238
239- `Arm DSU Software Developers Errata Notice`_.
240
241Each erratum is identified by an ``ID``, as defined in the DSU errata notice
242document. Thus, the build flags which enable/disable the errata workarounds
243have the format ``ERRATA_DSU_<ID>``. The implementation and application logic
244of DSU errata workarounds are similar to `CPU errata workarounds`_.
245
246For DSU errata, the following build flags are defined:
247
Louis Mayencourt4498b152019-04-09 16:29:01 +0100248- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the
249 affected DSU configurations. This errata applies only for those DSUs that
250 revision is r0p0 (on r0p1 it is fixed). However, please note that this
251 workaround results in increased DSU power consumption on idle.
252
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100253- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the
254 affected DSU configurations. This errata applies only for those DSUs that
255 contain the ACP interface **and** the DSU revision is older than r2p0 (on
256 r2p0 it is fixed). However, please note that this workaround results in
257 increased DSU power consumption on idle.
258
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100259CPU Specific optimizations
260--------------------------
261
262This section describes some of the optimizations allowed by the CPU micro
263architecture that can be enabled by the platform as desired.
264
265- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the
266 Cortex-A57 cluster power down sequence by not flushing the Level 1 data
267 cache. The L1 data cache and the L2 unified cache are inclusive. A flush
268 of the L2 by set/way flushes any dirty lines from the L1 as well. This
269 is a known safe deviation from the Cortex-A57 TRM defined power down
270 sequence. Each Cortex-A57 based platform must make its own decision on
271 whether to use the optimization.
272
273- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal
274 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave
275 in a way most programmers expect, and will most probably result in a
Dan Handley610e7e12018-03-01 18:44:00 +0000276 significant speed degradation to any code that employs them. The Armv8-A
277 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100278 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this
279 flag enforces this behaviour. This needs to be enabled only for revisions
280 <= r0p3 of the CPU and is enabled by default.
281
282- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as
283 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be
284 enabled only for revisions <= r1p2 of the CPU and is enabled by default,
285 as recommended in section "4.7 Non-Temporal Loads/Stores" of the
286 `Cortex-A57 Software Optimization Guide`_.
287
288--------------
289
Joel Hutton26d16762019-04-10 12:52:52 +0100290*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100291
John Tsichritzis3eeac412018-09-04 10:56:53 +0100292.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
293.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
Paul Beesley2437ddc2019-02-08 16:43:05 +0000294.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
295.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100296.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100297.. _Firmware Design guide: firmware-design.rst
298.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100299.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html