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git01.mediatek.com / filogic / atf / 51b4a1f380884ee3b6d34f26b65b3a3dc33d7095 / . / plat / nvidia / tegra / include / t210 / tegra_def.h
blob: 02c5f135e01d0b3bed711858b1991316f7d2a019 [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]1/*
Varun Wadekar4538bfc2019-01-02 17:53:15 -0800[diff] [blame]2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]7#ifndef TEGRA_DEF_H
8#define TEGRA_DEF_H
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]10#include <lib/utils_def.h>
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]11
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]12/*******************************************************************************
Varun Wadekar81b13832015-07-03 16:31:28 +0530[diff] [blame]13 * Power down state IDs
14 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]15#define PSTATE_ID_CORE_POWERDN U(7)
16#define PSTATE_ID_CLUSTER_IDLE U(16)
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]17#define PSTATE_ID_SOC_POWERDN U(27)
Varun Wadekar81b13832015-07-03 16:31:28 +0530[diff] [blame]18
19/*******************************************************************************
20 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
21 * call as the `state-id` field in the 'power state' parameter.
22 ******************************************************************************/
23#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN
24
25/*******************************************************************************
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]26 * Platform power states (used by PSCI framework)
27 *
28 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
29 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
30 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]31#define PLAT_MAX_RET_STATE U(1)
32#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]33
34/*******************************************************************************
Steven Kao0cb8b332018-02-09 20:50:02 +0800[diff] [blame]35 * Chip specific page table and MMU setup constants
36 ******************************************************************************/
37#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
38#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
39
40/*******************************************************************************
Varun Wadekara6a357f2017-05-05 09:20:59 -0700[diff] [blame]41 * iRAM memory constants
42 ******************************************************************************/
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800[diff] [blame]43#define TEGRA_IRAM_BASE U(0x40000000)
44#define TEGRA_IRAM_SIZE U(40000) /* 256KB */
Varun Wadekara6a357f2017-05-05 09:20:59 -0700[diff] [blame]45
46/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]47 * GIC memory map
48 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]49#define TEGRA_GICD_BASE U(0x50041000)
50#define TEGRA_GICC_BASE U(0x50042000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]51
52/*******************************************************************************
Varun Wadekar4538bfc2019-01-02 17:53:15 -0800[diff] [blame]53 * Secure IRQ definitions
54 ******************************************************************************/
55#define TEGRA210_WDT_CPU_LEGACY_FIQ U(28)
56
57/*******************************************************************************
Varun Wadekarbc787442015-07-27 13:00:50 +0530[diff] [blame]58 * Tegra Memory Select Switch Controller constants
59 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]60#define TEGRA_MSELECT_BASE U(0x50060000)
Varun Wadekarbc787442015-07-27 13:00:50 +0530[diff] [blame]61
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]62#define MSELECT_CONFIG U(0x0)
63#define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29))
64#define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28))
65#define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27))
66#define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25))
67#define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24))
Varun Wadekarbc787442015-07-27 13:00:50 +0530[diff] [blame]68#define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \
69 UNSUPPORTED_TX_ERR_MASTER1_BIT)
70#define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \
71 ENABLE_WRAP_INCR_MASTER1_BIT | \
72 ENABLE_WRAP_INCR_MASTER0_BIT)
73
74/*******************************************************************************
Varun Wadekara6a357f2017-05-05 09:20:59 -0700[diff] [blame]75 * Tegra Resource Semaphore constants
76 ******************************************************************************/
77#define TEGRA_RES_SEMA_BASE 0x60001000UL
78#define STA_OFFSET 0UL
79#define SET_OFFSET 4UL
80#define CLR_OFFSET 8UL
81
82/*******************************************************************************
83 * Tegra Primary Interrupt Controller constants
84 ******************************************************************************/
85#define TEGRA_PRI_ICTLR_BASE 0x60004000UL
86#define CPU_IEP_FIR_SET 0x18UL
87
88/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]89 * Tegra micro-seconds timer constants
90 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]91#define TEGRA_TMRUS_BASE U(0x60005010)
92#define TEGRA_TMRUS_SIZE U(0x1000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]93
94/*******************************************************************************
95 * Tegra Clock and Reset Controller constants
96 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]97#define TEGRA_CAR_RESET_BASE U(0x60006000)
Varun Wadekara59a7c52017-04-26 08:31:50 -0700[diff] [blame]98#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
Jeetesh Burman48fef882018-01-22 15:40:08 +0530[diff] [blame]99#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290)
Varun Wadekara59a7c52017-04-26 08:31:50 -0700[diff] [blame]100#define GPU_RESET_BIT (U(1) << 24)
Jeetesh Burman48fef882018-01-22 15:40:08 +0530[diff] [blame]101#define GPU_SET_BIT (U(1) << 24)
Varun Wadekara6a357f2017-05-05 09:20:59 -0700[diff] [blame]102#define TEGRA_RST_DEV_CLR_V U(0x434)
103#define TEGRA_CLK_ENB_V U(0x440)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]104
Samuel Payne1e6bed42017-06-12 10:15:43 -0700[diff] [blame]105/* SE Clock Offsets */
106#define TEGRA_RST_DEVICES_V 0x358UL
107#define SE_RESET_BIT (0x1UL << 31)
108#define TEGRA_RST_DEVICES_W 0x35CUL
109#define ENTROPY_CLK_ENB_BIT (0x1UL << 21)
110#define TEGRA_CLK_OUT_ENB_V 0x360UL
111#define SE_CLK_ENB_BIT (0x1UL << 31)
112#define TEGRA_CLK_OUT_ENB_W 0x364UL
113#define ENTROPY_RESET_BIT (0x1UL << 21)
114
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]115/*******************************************************************************
116 * Tegra Flow Controller constants
117 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]118#define TEGRA_FLOWCTRL_BASE U(0x60007000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]119
120/*******************************************************************************
Marvin Hsu21eea972017-04-11 11:00:48 +0800[diff] [blame]121 * Tegra AHB arbitration controller
122 ******************************************************************************/
123#define TEGRA_AHB_ARB_BASE 0x6000C000UL
124
125/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]126 * Tegra Secure Boot Controller constants
127 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]128#define TEGRA_SB_BASE U(0x6000C200)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]129
130/*******************************************************************************
131 * Tegra Exception Vectors constants
132 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]133#define TEGRA_EVP_BASE U(0x6000F000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]134
135/*******************************************************************************
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]136 * Tegra Miscellaneous register constants
137 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]138#define TEGRA_MISC_BASE U(0x70000000)
139#define HARDWARE_REVISION_OFFSET U(0x804)
Varun Wadekarba313282018-02-13 20:31:12 -0800[diff] [blame]140#define PINMUX_AUX_DVFS_PWM U(0x3184)
141#define PINMUX_PWM_TRISTATE (U(1) << 4)
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]142
143/*******************************************************************************
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]144 * Tegra UART controller base addresses
145 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]146#define TEGRA_UARTA_BASE U(0x70006000)
147#define TEGRA_UARTB_BASE U(0x70006040)
148#define TEGRA_UARTC_BASE U(0x70006200)
149#define TEGRA_UARTD_BASE U(0x70006300)
150#define TEGRA_UARTE_BASE U(0x70006400)
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]151
152/*******************************************************************************
Marvin Hsu40d3a672017-04-11 11:00:48 +0800[diff] [blame]153 * Tegra Fuse Controller related constants
154 ******************************************************************************/
155#define TEGRA_FUSE_BASE 0x7000F800UL
156#define FUSE_BOOT_SECURITY_INFO 0x268UL
157#define FUSE_ATOMIC_SAVE_CARVEOUT_EN (0x1U << 7)
Samuel Payne69b0e4a2017-06-15 21:12:45 -0700[diff] [blame]158#define FUSE_JTAG_SECUREID_VALID (0x104UL)
159#define ECID_VALID (0x1UL)
Marvin Hsu40d3a672017-04-11 11:00:48 +0800[diff] [blame]160
161
162/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]163 * Tegra Power Mgmt Controller constants
164 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]165#define TEGRA_PMC_BASE U(0x7000E400)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]166
167/*******************************************************************************
Varun Wadekara6a357f2017-05-05 09:20:59 -0700[diff] [blame]168 * Tegra Atomics constants
169 ******************************************************************************/
170#define TEGRA_ATOMICS_BASE 0x70016000UL
171#define TRIGGER0_REG_OFFSET 0UL
172#define TRIGGER_WIDTH_SHIFT 4UL
173#define TRIGGER_ID_SHIFT 16UL
174#define RESULT0_REG_OFFSET 0xC00UL
175
176/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]177 * Tegra Memory Controller constants
178 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]179#define TEGRA_MC_BASE U(0x70019000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]180
Harvey Hsieh359be952017-08-21 15:01:53 +0800[diff] [blame]181/* Memory Controller Interrupt Status */
182#define MC_INTSTATUS 0x00U
183
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]184/* TZDRAM carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]185#define MC_SECURITY_CFG0_0 U(0x70)
186#define MC_SECURITY_CFG1_0 U(0x74)
187#define MC_SECURITY_CFG3_0 U(0x9BC)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]188
189/* Video Memory carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]190#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
191#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
192#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]193
Samuel Payneae1e0792017-06-12 16:38:23 -0700[diff] [blame]194/* SMMU configuration registers*/
Anthony Zhou0e07e452017-07-26 17:16:54 +0800[diff] [blame]195#define MC_SMMU_PPCS_ASID_0 0x270U
Samuel Payneae1e0792017-06-12 16:38:23 -0700[diff] [blame]196#define PPCS_SMMU_ENABLE (0x1U << 31)
197
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]198/*******************************************************************************
Varun Wadekarba313282018-02-13 20:31:12 -0800[diff] [blame]199 * Tegra CLDVFS constants
200 ******************************************************************************/
201#define TEGRA_CL_DVFS_BASE U(0x70110000)
202#define DVFS_DFLL_CTRL U(0x00)
203#define ENABLE_OPEN_LOOP U(1)
204#define ENABLE_CLOSED_LOOP U(2)
205#define DVFS_DFLL_OUTPUT_CFG U(0x20)
206#define DFLL_OUTPUT_CFG_I2C_EN_BIT (U(1) << 30)
207#define DFLL_OUTPUT_CFG_CLK_EN_BIT (U(1) << 6)
208
209/*******************************************************************************
Marvin Hsu21eea972017-04-11 11:00:48 +0800[diff] [blame]210 * Tegra SE constants
211 ******************************************************************************/
212#define TEGRA_SE1_BASE U(0x70012000)
213#define TEGRA_SE2_BASE U(0x70412000)
214#define TEGRA_PKA1_BASE U(0x70420000)
215#define TEGRA_SE2_RANGE_SIZE U(0x2000)
216#define SE_TZRAM_SECURITY U(0x4)
217
218/*******************************************************************************
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]219 * Tegra TZRAM constants
220 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]221#define TEGRA_TZRAM_BASE U(0x7C010000)
222#define TEGRA_TZRAM_SIZE U(0x10000)
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]223
Marvin Hsu40d3a672017-04-11 11:00:48 +0800[diff] [blame]224/*******************************************************************************
225 * Tegra TZRAM carveout constants
226 ******************************************************************************/
227#define TEGRA_TZRAM_CARVEOUT_BASE U(0x7C04C000)
228#define TEGRA_TZRAM_CARVEOUT_SIZE U(0x4000)
229
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]230#endif /* TEGRA_DEF_H */