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git01.mediatek.com / filogic / atf / fa3cf0bf903ad0d8320713870ca58410e1ab8758 / . / plat / nvidia / tegra / include / t210 / tegra_def.h
blob: 641585b14967042bbdd3ee2e5d54e88f640fa321 [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]1/*
Steven Kao4d160ac2016-12-23 16:05:13 +0800[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame^]4 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]5 */
6
7#ifndef __TEGRA_DEF_H__
8#define __TEGRA_DEF_H__
9
10#include <platform_def.h>
11
12/*******************************************************************************
Varun Wadekar81b13832015-07-03 16:31:28 +0530[diff] [blame]13 * Power down state IDs
14 ******************************************************************************/
15#define PSTATE_ID_CORE_POWERDN 7
16#define PSTATE_ID_CLUSTER_IDLE 16
17#define PSTATE_ID_CLUSTER_POWERDN 17
18#define PSTATE_ID_SOC_POWERDN 27
19
20/*******************************************************************************
21 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
22 * call as the `state-id` field in the 'power state' parameter.
23 ******************************************************************************/
24#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN
25
26/*******************************************************************************
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]27 * Platform power states (used by PSCI framework)
28 *
29 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
30 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
31 ******************************************************************************/
32#define PLAT_MAX_RET_STATE 1
33#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1)
34
35/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]36 * GIC memory map
37 ******************************************************************************/
38#define TEGRA_GICD_BASE 0x50041000
39#define TEGRA_GICC_BASE 0x50042000
40
41/*******************************************************************************
Varun Wadekarbc787442015-07-27 13:00:50 +0530[diff] [blame]42 * Tegra Memory Select Switch Controller constants
43 ******************************************************************************/
44#define TEGRA_MSELECT_BASE 0x50060000
45
46#define MSELECT_CONFIG 0x0
47#define ENABLE_WRAP_INCR_MASTER2_BIT (1 << 29)
48#define ENABLE_WRAP_INCR_MASTER1_BIT (1 << 28)
49#define ENABLE_WRAP_INCR_MASTER0_BIT (1 << 27)
50#define UNSUPPORTED_TX_ERR_MASTER2_BIT (1 << 25)
51#define UNSUPPORTED_TX_ERR_MASTER1_BIT (1 << 24)
52#define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \
53 UNSUPPORTED_TX_ERR_MASTER1_BIT)
54#define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \
55 ENABLE_WRAP_INCR_MASTER1_BIT | \
56 ENABLE_WRAP_INCR_MASTER0_BIT)
57
58/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]59 * Tegra micro-seconds timer constants
60 ******************************************************************************/
61#define TEGRA_TMRUS_BASE 0x60005010
Steven Kao4d160ac2016-12-23 16:05:13 +0800[diff] [blame]62#define TEGRA_TMRUS_SIZE 0x1000
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]63
64/*******************************************************************************
65 * Tegra Clock and Reset Controller constants
66 ******************************************************************************/
67#define TEGRA_CAR_RESET_BASE 0x60006000
68
69/*******************************************************************************
70 * Tegra Flow Controller constants
71 ******************************************************************************/
72#define TEGRA_FLOWCTRL_BASE 0x60007000
73
74/*******************************************************************************
75 * Tegra Secure Boot Controller constants
76 ******************************************************************************/
77#define TEGRA_SB_BASE 0x6000C200
78
79/*******************************************************************************
80 * Tegra Exception Vectors constants
81 ******************************************************************************/
82#define TEGRA_EVP_BASE 0x6000F000
83
84/*******************************************************************************
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]85 * Tegra Miscellaneous register constants
86 ******************************************************************************/
87#define TEGRA_MISC_BASE 0x70000000
88#define HARDWARE_REVISION_OFFSET 0x804
89
90/*******************************************************************************
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]91 * Tegra UART controller base addresses
92 ******************************************************************************/
93#define TEGRA_UARTA_BASE 0x70006000
94#define TEGRA_UARTB_BASE 0x70006040
95#define TEGRA_UARTC_BASE 0x70006200
96#define TEGRA_UARTD_BASE 0x70006300
97#define TEGRA_UARTE_BASE 0x70006400
98
99/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]100 * Tegra Power Mgmt Controller constants
101 ******************************************************************************/
102#define TEGRA_PMC_BASE 0x7000E400
103
104/*******************************************************************************
105 * Tegra Memory Controller constants
106 ******************************************************************************/
107#define TEGRA_MC_BASE 0x70019000
108
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]109/* TZDRAM carveout configuration registers */
110#define MC_SECURITY_CFG0_0 0x70
111#define MC_SECURITY_CFG1_0 0x74
112#define MC_SECURITY_CFG3_0 0x9BC
113
114/* Video Memory carveout configuration registers */
115#define MC_VIDEO_PROTECT_BASE_HI 0x978
116#define MC_VIDEO_PROTECT_BASE_LO 0x648
117#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
118
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]119/*******************************************************************************
120 * Tegra TZRAM constants
121 ******************************************************************************/
122#define TEGRA_TZRAM_BASE 0x7C010000
123#define TEGRA_TZRAM_SIZE 0x10000
124
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]125#endif /* __TEGRA_DEF_H__ */