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git01.mediatek.com / filogic / atf / 1e6bed49d50702f5845e80281a4ab6c9e2b85c94 / . / plat / nvidia / tegra / include / t210 / tegra_def.h
blob: ee76b66bd3ff9b55760669b3f394ea982253d1d9 [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]1/*
Steven Kao4d160ac2016-12-23 16:05:13 +0800[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]7#ifndef TEGRA_DEF_H
8#define TEGRA_DEF_H
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]10#include <lib/utils_def.h>
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]11
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]12/*******************************************************************************
Varun Wadekar81b13832015-07-03 16:31:28 +0530[diff] [blame]13 * Power down state IDs
14 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]15#define PSTATE_ID_CORE_POWERDN U(7)
16#define PSTATE_ID_CLUSTER_IDLE U(16)
17#define PSTATE_ID_CLUSTER_POWERDN U(17)
18#define PSTATE_ID_SOC_POWERDN U(27)
Varun Wadekar81b13832015-07-03 16:31:28 +0530[diff] [blame]19
20/*******************************************************************************
21 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
22 * call as the `state-id` field in the 'power state' parameter.
23 ******************************************************************************/
24#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN
25
26/*******************************************************************************
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]27 * Platform power states (used by PSCI framework)
28 *
29 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
30 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
31 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]32#define PLAT_MAX_RET_STATE U(1)
33#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]34
35/*******************************************************************************
Varun Wadekara6a357f2017-05-05 09:20:59 -0700[diff] [blame]36 * iRAM memory constants
37 ******************************************************************************/
Varun Wadekar08554a62017-06-12 16:47:16 -0700[diff] [blame]38#define TEGRA_IRAM_BASE 0x40000000
Varun Wadekara6a357f2017-05-05 09:20:59 -0700[diff] [blame]39
40/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]41 * GIC memory map
42 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]43#define TEGRA_GICD_BASE U(0x50041000)
44#define TEGRA_GICC_BASE U(0x50042000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]45
46/*******************************************************************************
Varun Wadekarbc787442015-07-27 13:00:50 +0530[diff] [blame]47 * Tegra Memory Select Switch Controller constants
48 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]49#define TEGRA_MSELECT_BASE U(0x50060000)
Varun Wadekarbc787442015-07-27 13:00:50 +0530[diff] [blame]50
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]51#define MSELECT_CONFIG U(0x0)
52#define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29))
53#define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28))
54#define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27))
55#define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25))
56#define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24))
Varun Wadekarbc787442015-07-27 13:00:50 +0530[diff] [blame]57#define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \
58 UNSUPPORTED_TX_ERR_MASTER1_BIT)
59#define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \
60 ENABLE_WRAP_INCR_MASTER1_BIT | \
61 ENABLE_WRAP_INCR_MASTER0_BIT)
62
63/*******************************************************************************
Varun Wadekara6a357f2017-05-05 09:20:59 -0700[diff] [blame]64 * Tegra Resource Semaphore constants
65 ******************************************************************************/
66#define TEGRA_RES_SEMA_BASE 0x60001000UL
67#define STA_OFFSET 0UL
68#define SET_OFFSET 4UL
69#define CLR_OFFSET 8UL
70
71/*******************************************************************************
72 * Tegra Primary Interrupt Controller constants
73 ******************************************************************************/
74#define TEGRA_PRI_ICTLR_BASE 0x60004000UL
75#define CPU_IEP_FIR_SET 0x18UL
76
77/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]78 * Tegra micro-seconds timer constants
79 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]80#define TEGRA_TMRUS_BASE U(0x60005010)
81#define TEGRA_TMRUS_SIZE U(0x1000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]82
83/*******************************************************************************
84 * Tegra Clock and Reset Controller constants
85 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]86#define TEGRA_CAR_RESET_BASE U(0x60006000)
Varun Wadekara59a7c52017-04-26 08:31:50 -0700[diff] [blame]87#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
88#define GPU_RESET_BIT (U(1) << 24)
Varun Wadekara6a357f2017-05-05 09:20:59 -0700[diff] [blame]89#define TEGRA_RST_DEV_CLR_V U(0x434)
90#define TEGRA_CLK_ENB_V U(0x440)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]91
Samuel Payne1e6bed42017-06-12 10:15:43 -0700[diff] [blame^]92/* SE Clock Offsets */
93#define TEGRA_RST_DEVICES_V 0x358UL
94#define SE_RESET_BIT (0x1UL << 31)
95#define TEGRA_RST_DEVICES_W 0x35CUL
96#define ENTROPY_CLK_ENB_BIT (0x1UL << 21)
97#define TEGRA_CLK_OUT_ENB_V 0x360UL
98#define SE_CLK_ENB_BIT (0x1UL << 31)
99#define TEGRA_CLK_OUT_ENB_W 0x364UL
100#define ENTROPY_RESET_BIT (0x1UL << 21)
101
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]102/*******************************************************************************
103 * Tegra Flow Controller constants
104 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]105#define TEGRA_FLOWCTRL_BASE U(0x60007000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]106
107/*******************************************************************************
Marvin Hsu21eea972017-04-11 11:00:48 +0800[diff] [blame]108 * Tegra AHB arbitration controller
109 ******************************************************************************/
110#define TEGRA_AHB_ARB_BASE 0x6000C000UL
111
112/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]113 * Tegra Secure Boot Controller constants
114 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]115#define TEGRA_SB_BASE U(0x6000C200)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]116
117/*******************************************************************************
118 * Tegra Exception Vectors constants
119 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]120#define TEGRA_EVP_BASE U(0x6000F000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]121
122/*******************************************************************************
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]123 * Tegra Miscellaneous register constants
124 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]125#define TEGRA_MISC_BASE U(0x70000000)
126#define HARDWARE_REVISION_OFFSET U(0x804)
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]127
128/*******************************************************************************
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]129 * Tegra UART controller base addresses
130 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]131#define TEGRA_UARTA_BASE U(0x70006000)
132#define TEGRA_UARTB_BASE U(0x70006040)
133#define TEGRA_UARTC_BASE U(0x70006200)
134#define TEGRA_UARTD_BASE U(0x70006300)
135#define TEGRA_UARTE_BASE U(0x70006400)
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]136
137/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]138 * Tegra Power Mgmt Controller constants
139 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]140#define TEGRA_PMC_BASE U(0x7000E400)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]141
142/*******************************************************************************
Varun Wadekara6a357f2017-05-05 09:20:59 -0700[diff] [blame]143 * Tegra Atomics constants
144 ******************************************************************************/
145#define TEGRA_ATOMICS_BASE 0x70016000UL
146#define TRIGGER0_REG_OFFSET 0UL
147#define TRIGGER_WIDTH_SHIFT 4UL
148#define TRIGGER_ID_SHIFT 16UL
149#define RESULT0_REG_OFFSET 0xC00UL
150
151/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]152 * Tegra Memory Controller constants
153 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]154#define TEGRA_MC_BASE U(0x70019000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]155
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]156/* TZDRAM carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]157#define MC_SECURITY_CFG0_0 U(0x70)
158#define MC_SECURITY_CFG1_0 U(0x74)
159#define MC_SECURITY_CFG3_0 U(0x9BC)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]160
161/* Video Memory carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]162#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
163#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
164#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]165
Samuel Payneae1e0792017-06-12 16:38:23 -0700[diff] [blame]166/* SMMU configuration registers*/
167#define MC_SMMU_PPCS_ASID_0 0x270UL
168#define PPCS_SMMU_ENABLE (0x1U << 31)
169
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]170/*******************************************************************************
Marvin Hsu21eea972017-04-11 11:00:48 +0800[diff] [blame]171 * Tegra SE constants
172 ******************************************************************************/
173#define TEGRA_SE1_BASE U(0x70012000)
174#define TEGRA_SE2_BASE U(0x70412000)
175#define TEGRA_PKA1_BASE U(0x70420000)
176#define TEGRA_SE2_RANGE_SIZE U(0x2000)
177#define SE_TZRAM_SECURITY U(0x4)
178
179/*******************************************************************************
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]180 * Tegra TZRAM constants
181 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]182#define TEGRA_TZRAM_BASE U(0x7C010000)
183#define TEGRA_TZRAM_SIZE U(0x10000)
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]184
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]185#endif /* TEGRA_DEF_H */