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Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Porting Guide
2=============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004Introduction
5------------
6
Dan Handley610e7e12018-03-01 18:44:00 +00007Porting Trusted Firmware-A (TF-A) to a new platform involves making some
Douglas Raillardd7c21b72017-06-28 15:23:03 +01008mandatory and optional modifications for both the cold and warm boot paths.
9Modifications consist of:
10
11- Implementing a platform-specific function or variable,
12- Setting up the execution context in a certain way, or
13- Defining certain constants (for example #defines).
14
15The platform-specific functions and variables are declared in
16`include/plat/common/platform.h`_. The firmware provides a default implementation
17of variables and functions to fulfill the optional requirements. These
18implementations are all weakly defined; they are provided to ease the porting
19effort. Each platform port can override them with its own implementation if the
20default implementation is inadequate.
21
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022Some modifications are common to all Boot Loader (BL) stages. Section 2
23discusses these in detail. The subsequent sections discuss the remaining
24modifications for each BL stage in detail.
25
Dan Handley610e7e12018-03-01 18:44:00 +000026This document should be read in conjunction with the TF-A `User Guide`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010027
Soby Mathew02bdbb92018-09-26 11:17:23 +010028Please refer to the `Platform compatibility policy`_ for the policy regarding
29compatibility and deprecation of these porting interfaces.
30
Antonio Nino Diaz645feb42019-02-13 14:07:38 +000031Only Arm development platforms (such as FVP and Juno) may use the
32functions/definitions in ``include/plat/arm/common/`` and the corresponding
33source files in ``plat/arm/common/``. This is done so that there are no
34dependencies between platforms maintained by different people/companies. If you
35want to use any of the functionality present in ``plat/arm`` files, please
36create a pull request that moves the code to ``plat/common`` so that it can be
37discussed.
38
Douglas Raillardd7c21b72017-06-28 15:23:03 +010039Common modifications
40--------------------
41
42This section covers the modifications that should be made by the platform for
43each BL stage to correctly port the firmware stack. They are categorized as
44either mandatory or optional.
45
46Common mandatory modifications
47------------------------------
48
49A platform port must enable the Memory Management Unit (MMU) as well as the
50instruction and data caches for each BL stage. Setting up the translation
51tables is the responsibility of the platform port because memory maps differ
52across platforms. A memory translation library (see ``lib/xlat_tables/``) is
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010053provided to help in this setup.
54
55Note that although this library supports non-identity mappings, this is intended
56only for re-mapping peripheral physical addresses and allows platforms with high
57I/O addresses to reduce their virtual address space. All other addresses
58corresponding to code and data must currently use an identity mapping.
59
Dan Handley610e7e12018-03-01 18:44:00 +000060Also, the only translation granule size supported in TF-A is 4KB, as various
61parts of the code assume that is the case. It is not possible to switch to
6216 KB or 64 KB granule sizes at the moment.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010063
Dan Handley610e7e12018-03-01 18:44:00 +000064In Arm standard platforms, each BL stage configures the MMU in the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010065platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses
66an identity mapping for all addresses.
67
68If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a
69block of identity mapped secure memory with Device-nGnRE attributes aligned to
70page boundary (4K) for each BL stage. All sections which allocate coherent
71memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a
72section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its
73possible for the firmware to place variables in it using the following C code
74directive:
75
76::
77
78 __section("bakery_lock")
79
80Or alternatively the following assembler code directive:
81
82::
83
84 .section bakery_lock
85
86The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are
87used to allocate any data structures that are accessed both when a CPU is
88executing with its MMU and caches enabled, and when it's running with its MMU
89and caches disabled. Examples are given below.
90
91The following variables, functions and constants must be defined by the platform
92for the firmware to work correctly.
93
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +010094File : platform_def.h [mandatory]
95~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +010096
97Each platform must ensure that a header file of this name is in the system
Antonio Nino Diaz50a4d1a2019-02-01 12:22:22 +000098include path with the following constants defined. This will require updating
99the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100100
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100101Platform ports may optionally use the file `include/plat/common/common_def.h`_,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100102which provides typical values for some of the constants below. These values are
103likely to be suitable for all platform ports.
104
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100105- **#define : PLATFORM_LINKER_FORMAT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100106
107 Defines the linker format used by the platform, for example
108 ``elf64-littleaarch64``.
109
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100110- **#define : PLATFORM_LINKER_ARCH**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100111
112 Defines the processor architecture for the linker by the platform, for
113 example ``aarch64``.
114
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100115- **#define : PLATFORM_STACK_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100116
117 Defines the normal stack memory available to each CPU. This constant is used
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100118 by `plat/common/aarch64/platform_mp_stack.S`_ and
119 `plat/common/aarch64/platform_up_stack.S`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100120
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100121- **define : CACHE_WRITEBACK_GRANULE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100122
123 Defines the size in bits of the largest cache line across all the cache
124 levels in the platform.
125
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100126- **#define : FIRMWARE_WELCOME_STR**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100127
128 Defines the character string printed by BL1 upon entry into the ``bl1_main()``
129 function.
130
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100131- **#define : PLATFORM_CORE_COUNT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100132
133 Defines the total number of CPUs implemented by the platform across all
134 clusters in the system.
135
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100136- **#define : PLAT_NUM_PWR_DOMAINS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100137
138 Defines the total number of nodes in the power domain topology
139 tree at all the power domain levels used by the platform.
140 This macro is used by the PSCI implementation to allocate
141 data structures to represent power domain topology.
142
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100143- **#define : PLAT_MAX_PWR_LVL**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100144
145 Defines the maximum power domain level that the power management operations
146 should apply to. More often, but not always, the power domain level
147 corresponds to affinity level. This macro allows the PSCI implementation
148 to know the highest power domain level that it should consider for power
149 management operations in the system that the platform implements. For
150 example, the Base AEM FVP implements two clusters with a configurable
151 number of CPUs and it reports the maximum power domain level as 1.
152
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100153- **#define : PLAT_MAX_OFF_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100154
155 Defines the local power state corresponding to the deepest power down
156 possible at every power domain level in the platform. The local power
157 states for each level may be sparsely allocated between 0 and this value
158 with 0 being reserved for the RUN state. The PSCI implementation uses this
159 value to initialize the local power states of the power domain nodes and
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100160 to specify the requested power state for a PSCI_CPU_OFF call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100162- **#define : PLAT_MAX_RET_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100163
164 Defines the local power state corresponding to the deepest retention state
165 possible at every power domain level in the platform. This macro should be
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100166 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100167 PSCI implementation to distinguish between retention and power down local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100168 power states within PSCI_CPU_SUSPEND call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100169
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100170- **#define : PLAT_MAX_PWR_LVL_STATES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100171
172 Defines the maximum number of local power states per power domain level
173 that the platform supports. The default value of this macro is 2 since
174 most platforms just support a maximum of two local power states at each
175 power domain level (power-down and retention). If the platform needs to
176 account for more local power states, then it must redefine this macro.
177
178 Currently, this macro is used by the Generic PSCI implementation to size
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100179 the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100180
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100181- **#define : BL1_RO_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100182
183 Defines the base address in secure ROM where BL1 originally lives. Must be
184 aligned on a page-size boundary.
185
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100186- **#define : BL1_RO_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100187
188 Defines the maximum address in secure ROM that BL1's actual content (i.e.
189 excluding any data section allocated at runtime) can occupy.
190
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100191- **#define : BL1_RW_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100192
193 Defines the base address in secure RAM where BL1's read-write data will live
194 at runtime. Must be aligned on a page-size boundary.
195
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100196- **#define : BL1_RW_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100197
198 Defines the maximum address in secure RAM that BL1's read-write data can
199 occupy at runtime.
200
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100201- **#define : BL2_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100202
203 Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000204 Must be aligned on a page-size boundary. This constant is not applicable
205 when BL2_IN_XIP_MEM is set to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100206
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100207- **#define : BL2_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100208
209 Defines the maximum address in secure RAM that the BL2 image can occupy.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000210 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'.
211
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100212- **#define : BL2_RO_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000213
214 Defines the base address in secure XIP memory where BL2 RO section originally
215 lives. Must be aligned on a page-size boundary. This constant is only needed
216 when BL2_IN_XIP_MEM is set to '1'.
217
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100218- **#define : BL2_RO_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000219
220 Defines the maximum address in secure XIP memory that BL2's actual content
221 (i.e. excluding any data section allocated at runtime) can occupy. This
222 constant is only needed when BL2_IN_XIP_MEM is set to '1'.
223
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100224- **#define : BL2_RW_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000225
226 Defines the base address in secure RAM where BL2's read-write data will live
227 at runtime. Must be aligned on a page-size boundary. This constant is only
228 needed when BL2_IN_XIP_MEM is set to '1'.
229
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100230- **#define : BL2_RW_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000231
232 Defines the maximum address in secure RAM that BL2's read-write data can
233 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set
234 to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100235
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100236- **#define : BL31_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100237
238 Defines the base address in secure RAM where BL2 loads the BL31 binary
239 image. Must be aligned on a page-size boundary.
240
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100241- **#define : BL31_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100242
243 Defines the maximum address in secure RAM that the BL31 image can occupy.
244
245For every image, the platform must define individual identifiers that will be
246used by BL1 or BL2 to load the corresponding image into memory from non-volatile
247storage. For the sake of performance, integer numbers will be used as
248identifiers. The platform will use those identifiers to return the relevant
249information about the image to be loaded (file handler, load address,
250authentication information, etc.). The following image identifiers are
251mandatory:
252
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100253- **#define : BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100254
255 BL2 image identifier, used by BL1 to load BL2.
256
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100257- **#define : BL31_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100258
259 BL31 image identifier, used by BL2 to load BL31.
260
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100261- **#define : BL33_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100262
263 BL33 image identifier, used by BL2 to load BL33.
264
265If Trusted Board Boot is enabled, the following certificate identifiers must
266also be defined:
267
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100268- **#define : TRUSTED_BOOT_FW_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100269
270 BL2 content certificate identifier, used by BL1 to load the BL2 content
271 certificate.
272
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100273- **#define : TRUSTED_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100274
275 Trusted key certificate identifier, used by BL2 to load the trusted key
276 certificate.
277
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100278- **#define : SOC_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100279
280 BL31 key certificate identifier, used by BL2 to load the BL31 key
281 certificate.
282
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100283- **#define : SOC_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100284
285 BL31 content certificate identifier, used by BL2 to load the BL31 content
286 certificate.
287
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100288- **#define : NON_TRUSTED_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100289
290 BL33 key certificate identifier, used by BL2 to load the BL33 key
291 certificate.
292
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100293- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100294
295 BL33 content certificate identifier, used by BL2 to load the BL33 content
296 certificate.
297
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100298- **#define : FWU_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100299
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100300 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100301 FWU content certificate.
302
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100303- **#define : PLAT_CRYPTOCELL_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100304
Dan Handley610e7e12018-03-01 18:44:00 +0000305 This defines the base address of Arm® TrustZone® CryptoCell and must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100306 defined if CryptoCell crypto driver is used for Trusted Board Boot. For
Dan Handley610e7e12018-03-01 18:44:00 +0000307 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100308 set.
309
310If the AP Firmware Updater Configuration image, BL2U is used, the following
311must also be defined:
312
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100313- **#define : BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100314
315 Defines the base address in secure memory where BL1 copies the BL2U binary
316 image. Must be aligned on a page-size boundary.
317
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100318- **#define : BL2U_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100319
320 Defines the maximum address in secure memory that the BL2U image can occupy.
321
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100322- **#define : BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100323
324 BL2U image identifier, used by BL1 to fetch an image descriptor
325 corresponding to BL2U.
326
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100327If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100328must also be defined:
329
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100330- **#define : SCP_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100331
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100332 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
333 corresponding to SCP_BL2U.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000334
335 .. note::
336 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100337
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100338If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100339also be defined:
340
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100341- **#define : NS_BL1U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100342
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100343 Defines the base address in non-secure ROM where NS_BL1U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100344 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000345
346 .. note::
347 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100348
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100349- **#define : NS_BL1U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100350
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100351 NS_BL1U image identifier, used by BL1 to fetch an image descriptor
352 corresponding to NS_BL1U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100353
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100354If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100355be defined:
356
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100357- **#define : NS_BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100358
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100359 Defines the base address in non-secure memory where NS_BL2U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100360 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000361
362 .. note::
363 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100364
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100365- **#define : NS_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100366
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100367 NS_BL2U image identifier, used by BL1 to fetch an image descriptor
368 corresponding to NS_BL2U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100369
370For the the Firmware update capability of TRUSTED BOARD BOOT, the following
371macros may also be defined:
372
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100373- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100374
375 Total number of images that can be loaded simultaneously. If the platform
376 doesn't specify any value, it defaults to 10.
377
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100378If a SCP_BL2 image is supported by the platform, the following constants must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100379also be defined:
380
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100381- **#define : SCP_BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100382
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100383 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000384 from platform storage before being transferred to the SCP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100385
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100386- **#define : SCP_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100387
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100388 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100389 certificate (mandatory when Trusted Board Boot is enabled).
390
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100391- **#define : SCP_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100392
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100393 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100394 content certificate (mandatory when Trusted Board Boot is enabled).
395
396If a BL32 image is supported by the platform, the following constants must
397also be defined:
398
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100399- **#define : BL32_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100400
401 BL32 image identifier, used by BL2 to load BL32.
402
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100403- **#define : TRUSTED_OS_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100404
405 BL32 key certificate identifier, used by BL2 to load the BL32 key
406 certificate (mandatory when Trusted Board Boot is enabled).
407
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100408- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100409
410 BL32 content certificate identifier, used by BL2 to load the BL32 content
411 certificate (mandatory when Trusted Board Boot is enabled).
412
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100413- **#define : BL32_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100414
415 Defines the base address in secure memory where BL2 loads the BL32 binary
416 image. Must be aligned on a page-size boundary.
417
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100418- **#define : BL32_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100419
420 Defines the maximum address that the BL32 image can occupy.
421
422If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
423platform, the following constants must also be defined:
424
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100425- **#define : TSP_SEC_MEM_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100426
427 Defines the base address of the secure memory used by the TSP image on the
428 platform. This must be at the same address or below ``BL32_BASE``.
429
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100430- **#define : TSP_SEC_MEM_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100431
432 Defines the size of the secure memory used by the BL32 image on the
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000433 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
434 accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
435 and ``BL32_LIMIT``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100436
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100437- **#define : TSP_IRQ_SEC_PHY_TIMER**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100438
439 Defines the ID of the secure physical generic timer interrupt used by the
440 TSP's interrupt handling code.
441
442If the platform port uses the translation table library code, the following
443constants must also be defined:
444
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100445- **#define : PLAT_XLAT_TABLES_DYNAMIC**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100446
447 Optional flag that can be set per-image to enable the dynamic allocation of
448 regions even when the MMU is enabled. If not defined, only static
449 functionality will be available, if defined and set to 1 it will also
450 include the dynamic functionality.
451
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100452- **#define : MAX_XLAT_TABLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100453
454 Defines the maximum number of translation tables that are allocated by the
455 translation table library code. To minimize the amount of runtime memory
456 used, choose the smallest value needed to map the required virtual addresses
457 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL
458 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
459 as well.
460
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100461- **#define : MAX_MMAP_REGIONS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100462
463 Defines the maximum number of regions that are allocated by the translation
464 table library code. A region consists of physical base address, virtual base
465 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
466 defined in the ``mmap_region_t`` structure. The platform defines the regions
467 that should be mapped. Then, the translation table library will create the
468 corresponding tables and descriptors at runtime. To minimize the amount of
469 runtime memory used, choose the smallest value needed to register the
470 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is
471 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
472 the dynamic regions as well.
473
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100474- **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100475
476 Defines the total size of the virtual address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000477 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100478
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100479- **#define : PLAT_PHY_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100480
481 Defines the total size of the physical address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000482 for a 32 bit physical address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100483
484If the platform port uses the IO storage framework, the following constants
485must also be defined:
486
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100487- **#define : MAX_IO_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100488
489 Defines the maximum number of registered IO devices. Attempting to register
490 more devices than this value using ``io_register_device()`` will fail with
491 -ENOMEM.
492
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100493- **#define : MAX_IO_HANDLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100494
495 Defines the maximum number of open IO handles. Attempting to open more IO
496 entities than this value using ``io_open()`` will fail with -ENOMEM.
497
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100498- **#define : MAX_IO_BLOCK_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100499
500 Defines the maximum number of registered IO block devices. Attempting to
501 register more devices this value using ``io_dev_open()`` will fail
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100502 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100503 With this macro, multiple block devices could be supported at the same
504 time.
505
506If the platform needs to allocate data within the per-cpu data framework in
507BL31, it should define the following macro. Currently this is only required if
508the platform decides not to use the coherent memory section by undefining the
509``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
510required memory within the the per-cpu data to minimize wastage.
511
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100512- **#define : PLAT_PCPU_DATA_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100513
514 Defines the memory (in bytes) to be reserved within the per-cpu data
515 structure for use by the platform layer.
516
517The following constants are optional. They should be defined when the platform
Dan Handley610e7e12018-03-01 18:44:00 +0000518memory layout implies some image overlaying like in Arm standard platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100519
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100520- **#define : BL31_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100521
522 Defines the maximum address in secure RAM that the BL31's progbits sections
523 can occupy.
524
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100525- **#define : TSP_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100526
527 Defines the maximum address that the TSP's progbits sections can occupy.
528
529If the platform port uses the PL061 GPIO driver, the following constant may
530optionally be defined:
531
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100532- **PLAT_PL061_MAX_GPIOS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100533 Maximum number of GPIOs required by the platform. This allows control how
534 much memory is allocated for PL061 GPIO controllers. The default value is
535
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100536 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100537
538If the platform port uses the partition driver, the following constant may
539optionally be defined:
540
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100541- **PLAT_PARTITION_MAX_ENTRIES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100542 Maximum number of partition entries required by the platform. This allows
543 control how much memory is allocated for partition entries. The default
544 value is 128.
545 `For example, define the build flag in platform.mk`_:
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100546 PLAT_PARTITION_MAX_ENTRIES := 12
547 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100548
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800549- **PLAT_PARTITION_BLOCK_SIZE**
550 The size of partition block. It could be either 512 bytes or 4096 bytes.
551 The default value is 512.
552 `For example, define the build flag in platform.mk`_:
553 PLAT_PARTITION_BLOCK_SIZE := 4096
554 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE))
555
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100556The following constant is optional. It should be defined to override the default
557behaviour of the ``assert()`` function (for example, to save memory).
558
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100559- **PLAT_LOG_LEVEL_ASSERT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100560 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
561 ``assert()`` prints the name of the file, the line number and the asserted
562 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
563 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it
564 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
565 defined, it defaults to ``LOG_LEVEL``.
566
Dimitris Papastamos60346db2017-12-13 10:54:37 +0000567If the platform port uses the Activity Monitor Unit, the following constants
568may be defined:
569
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100570- **PLAT_AMU_GROUP1_COUNTERS_MASK**
Dimitris Papastamos60346db2017-12-13 10:54:37 +0000571 This mask reflects the set of group counters that should be enabled. The
572 maximum number of group 1 counters supported by AMUv1 is 16 so the mask
573 can be at most 0xffff. If the platform does not define this mask, no group 1
574 counters are enabled. If the platform defines this mask, the following
575 constant needs to also be defined.
576
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100577- **PLAT_AMU_GROUP1_NR_COUNTERS**
Dimitris Papastamos60346db2017-12-13 10:54:37 +0000578 This value is used to allocate an array to save and restore the counters
579 specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend.
580 This value should be equal to the highest bit position set in the
581 mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16.
582
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100583File : plat_macros.S [mandatory]
584~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100585
586Each platform must ensure a file of this name is in the system include path with
Dan Handley610e7e12018-03-01 18:44:00 +0000587the following macro defined. In the Arm development platforms, this file is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100588found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
589
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100590- **Macro : plat_crash_print_regs**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100591
592 This macro allows the crash reporting routine to print relevant platform
593 registers in case of an unhandled exception in BL31. This aids in debugging
594 and this macro can be defined to be empty in case register reporting is not
595 desired.
596
597 For instance, GIC or interconnect registers may be helpful for
598 troubleshooting.
599
600Handling Reset
601--------------
602
603BL1 by default implements the reset vector where execution starts from a cold
604or warm boot. BL31 can be optionally set as a reset vector using the
605``RESET_TO_BL31`` make variable.
606
607For each CPU, the reset vector code is responsible for the following tasks:
608
609#. Distinguishing between a cold boot and a warm boot.
610
611#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
612 the CPU is placed in a platform-specific state until the primary CPU
613 performs the necessary steps to remove it from this state.
614
615#. In the case of a warm boot, ensuring that the CPU jumps to a platform-
616 specific address in the BL31 image in the same processor mode as it was
617 when released from reset.
618
619The following functions need to be implemented by the platform port to enable
620reset vector code to perform the above tasks.
621
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100622Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
623~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100624
625::
626
627 Argument : void
628 Return : uintptr_t
629
630This function is called with the MMU and caches disabled
631(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for
632distinguishing between a warm and cold reset for the current CPU using
633platform-specific means. If it's a warm reset, then it returns the warm
634reset entrypoint point provided to ``plat_setup_psci_ops()`` during
635BL31 initialization. If it's a cold reset then this function must return zero.
636
637This function does not follow the Procedure Call Standard used by the
Dan Handley610e7e12018-03-01 18:44:00 +0000638Application Binary Interface for the Arm 64-bit architecture. The caller should
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100639not assume that callee saved registers are preserved across a call to this
640function.
641
642This function fulfills requirement 1 and 3 listed above.
643
644Note that for platforms that support programming the reset address, it is
645expected that a CPU will start executing code directly at the right address,
646both on a cold and warm reset. In this case, there is no need to identify the
647type of reset nor to query the warm reset entrypoint. Therefore, implementing
648this function is not required on such platforms.
649
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100650Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
651~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100652
653::
654
655 Argument : void
656
657This function is called with the MMU and data caches disabled. It is responsible
658for placing the executing secondary CPU in a platform-specific state until the
659primary CPU performs the necessary actions to bring it out of that state and
660allow entry into the OS. This function must not return.
661
Dan Handley610e7e12018-03-01 18:44:00 +0000662In the Arm FVP port, when using the normal boot flow, each secondary CPU powers
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100663itself off. The primary CPU is responsible for powering up the secondary CPUs
664when normal world software requires them. When booting an EL3 payload instead,
665they stay powered on and are put in a holding pen until their mailbox gets
666populated.
667
668This function fulfills requirement 2 above.
669
670Note that for platforms that can't release secondary CPUs out of reset, only the
671primary CPU will execute the cold boot code. Therefore, implementing this
672function is not required on such platforms.
673
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100674Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
675~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100676
677::
678
679 Argument : void
680 Return : unsigned int
681
682This function identifies whether the current CPU is the primary CPU or a
683secondary CPU. A return value of zero indicates that the CPU is not the
684primary CPU, while a non-zero return value indicates that the CPU is the
685primary CPU.
686
687Note that for platforms that can't release secondary CPUs out of reset, only the
688primary CPU will execute the cold boot code. Therefore, there is no need to
689distinguish between primary and secondary CPUs and implementing this function is
690not required.
691
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100692Function : platform_mem_init() [mandatory]
693~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100694
695::
696
697 Argument : void
698 Return : void
699
700This function is called before any access to data is made by the firmware, in
701order to carry out any essential memory initialization.
702
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100703Function: plat_get_rotpk_info()
704~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100705
706::
707
708 Argument : void *, void **, unsigned int *, unsigned int *
709 Return : int
710
711This function is mandatory when Trusted Board Boot is enabled. It returns a
712pointer to the ROTPK stored in the platform (or a hash of it) and its length.
713The ROTPK must be encoded in DER format according to the following ASN.1
714structure:
715
716::
717
718 AlgorithmIdentifier ::= SEQUENCE {
719 algorithm OBJECT IDENTIFIER,
720 parameters ANY DEFINED BY algorithm OPTIONAL
721 }
722
723 SubjectPublicKeyInfo ::= SEQUENCE {
724 algorithm AlgorithmIdentifier,
725 subjectPublicKey BIT STRING
726 }
727
728In case the function returns a hash of the key:
729
730::
731
732 DigestInfo ::= SEQUENCE {
733 digestAlgorithm AlgorithmIdentifier,
734 digest OCTET STRING
735 }
736
737The function returns 0 on success. Any other value is treated as error by the
738Trusted Board Boot. The function also reports extra information related
739to the ROTPK in the flags parameter:
740
741::
742
743 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a
744 hash.
745 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK
746 verification while the platform ROTPK is not deployed.
747 When this flag is set, the function does not need to
748 return a platform ROTPK, and the authentication
749 framework uses the ROTPK in the certificate without
750 verifying it against the platform value. This flag
751 must not be used in a deployed production environment.
752
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100753Function: plat_get_nv_ctr()
754~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100755
756::
757
758 Argument : void *, unsigned int *
759 Return : int
760
761This function is mandatory when Trusted Board Boot is enabled. It returns the
762non-volatile counter value stored in the platform in the second argument. The
763cookie in the first argument may be used to select the counter in case the
764platform provides more than one (for example, on platforms that use the default
765TBBR CoT, the cookie will correspond to the OID values defined in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100766TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100767
768The function returns 0 on success. Any other value means the counter value could
769not be retrieved from the platform.
770
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100771Function: plat_set_nv_ctr()
772~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100773
774::
775
776 Argument : void *, unsigned int
777 Return : int
778
779This function is mandatory when Trusted Board Boot is enabled. It sets a new
780counter value in the platform. The cookie in the first argument may be used to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100781select the counter (as explained in plat_get_nv_ctr()). The second argument is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100782the updated counter value to be written to the NV counter.
783
784The function returns 0 on success. Any other value means the counter value could
785not be updated.
786
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100787Function: plat_set_nv_ctr2()
788~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100789
790::
791
792 Argument : void *, const auth_img_desc_t *, unsigned int
793 Return : int
794
795This function is optional when Trusted Board Boot is enabled. If this
796interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The
797first argument passed is a cookie and is typically used to
798differentiate between a Non Trusted NV Counter and a Trusted NV
799Counter. The second argument is a pointer to an authentication image
800descriptor and may be used to decide if the counter is allowed to be
801updated or not. The third argument is the updated counter value to
802be written to the NV counter.
803
804The function returns 0 on success. Any other value means the counter value
805either could not be updated or the authentication image descriptor indicates
806that it is not allowed to be updated.
807
808Common mandatory function modifications
809---------------------------------------
810
811The following functions are mandatory functions which need to be implemented
812by the platform port.
813
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100814Function : plat_my_core_pos()
815~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100816
817::
818
819 Argument : void
820 Return : unsigned int
821
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000822This function returns the index of the calling CPU which is used as a
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100823CPU-specific linear index into blocks of memory (for example while allocating
824per-CPU stacks). This function will be invoked very early in the
825initialization sequence which mandates that this function should be
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000826implemented in assembly and should not rely on the availability of a C
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100827runtime environment. This function can clobber x0 - x8 and must preserve
828x9 - x29.
829
830This function plays a crucial role in the power domain topology framework in
831PSCI and details of this can be found in `Power Domain Topology Design`_.
832
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100833Function : plat_core_pos_by_mpidr()
834~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100835
836::
837
838 Argument : u_register_t
839 Return : int
840
841This function validates the ``MPIDR`` of a CPU and converts it to an index,
842which can be used as a CPU-specific linear index into blocks of memory. In
843case the ``MPIDR`` is invalid, this function returns -1. This function will only
844be invoked by BL31 after the power domain topology is initialized and can
Dan Handley610e7e12018-03-01 18:44:00 +0000845utilize the C runtime environment. For further details about how TF-A
846represents the power domain topology and how this relates to the linear CPU
847index, please refer `Power Domain Topology Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100848
Ambroise Vincentd207f562019-04-10 12:50:27 +0100849Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1]
850~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
851
852::
853
854 Arguments : void **heap_addr, size_t *heap_size
855 Return : int
856
857This function is invoked during Mbed TLS library initialisation to get a heap,
858by means of a starting address and a size. This heap will then be used
859internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS
860must be able to provide a heap to it.
861
862A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in
863which a heap is statically reserved during compile time inside every image
864(i.e. every BL stage) that utilises Mbed TLS. In this default implementation,
865the function simply returns the address and size of this "pre-allocated" heap.
866For a platform to use this default implementation, only a call to the helper
867from inside plat_get_mbedtls_heap() body is enough and nothing else is needed.
868
869However, by writting their own implementation, platforms have the potential to
870optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is
871shared between BL1 and BL2 stages and, thus, the necessary space is not reserved
872twice.
873
874On success the function should return 0 and a negative error code otherwise.
875
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100876Common optional modifications
877-----------------------------
878
879The following are helper functions implemented by the firmware that perform
880common platform-specific tasks. A platform may choose to override these
881definitions.
882
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100883Function : plat_set_my_stack()
884~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100885
886::
887
888 Argument : void
889 Return : void
890
891This function sets the current stack pointer to the normal memory stack that
892has been allocated for the current CPU. For BL images that only require a
893stack for the primary CPU, the UP version of the function is used. The size
894of the stack allocated to each CPU is specified by the platform defined
895constant ``PLATFORM_STACK_SIZE``.
896
897Common implementations of this function for the UP and MP BL images are
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100898provided in `plat/common/aarch64/platform_up_stack.S`_ and
899`plat/common/aarch64/platform_mp_stack.S`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100900
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100901Function : plat_get_my_stack()
902~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100903
904::
905
906 Argument : void
907 Return : uintptr_t
908
909This function returns the base address of the normal memory stack that
910has been allocated for the current CPU. For BL images that only require a
911stack for the primary CPU, the UP version of the function is used. The size
912of the stack allocated to each CPU is specified by the platform defined
913constant ``PLATFORM_STACK_SIZE``.
914
915Common implementations of this function for the UP and MP BL images are
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100916provided in `plat/common/aarch64/platform_up_stack.S`_ and
917`plat/common/aarch64/platform_mp_stack.S`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100918
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100919Function : plat_report_exception()
920~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100921
922::
923
924 Argument : unsigned int
925 Return : void
926
927A platform may need to report various information about its status when an
928exception is taken, for example the current exception level, the CPU security
929state (secure/non-secure), the exception type, and so on. This function is
930called in the following circumstances:
931
932- In BL1, whenever an exception is taken.
933- In BL2, whenever an exception is taken.
934
935The default implementation doesn't do anything, to avoid making assumptions
936about the way the platform displays its status information.
937
938For AArch64, this function receives the exception type as its argument.
939Possible values for exceptions types are listed in the
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100940`include/common/bl_common.h`_ header file. Note that these constants are not
Dan Handley610e7e12018-03-01 18:44:00 +0000941related to any architectural exception code; they are just a TF-A convention.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100942
943For AArch32, this function receives the exception mode as its argument.
944Possible values for exception modes are listed in the
945`include/lib/aarch32/arch.h`_ header file.
946
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100947Function : plat_reset_handler()
948~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100949
950::
951
952 Argument : void
953 Return : void
954
955A platform may need to do additional initialization after reset. This function
956allows the platform to do the platform specific intializations. Platform
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000957specific errata workarounds could also be implemented here. The API should
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100958preserve the values of callee saved registers x19 to x29.
959
960The default implementation doesn't do anything. If a platform needs to override
961the default implementation, refer to the `Firmware Design`_ for general
962guidelines.
963
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100964Function : plat_disable_acp()
965~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100966
967::
968
969 Argument : void
970 Return : void
971
John Tsichritzis6dda9762018-07-23 09:18:04 +0100972This API allows a platform to disable the Accelerator Coherency Port (if
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100973present) during a cluster power down sequence. The default weak implementation
John Tsichritzis6dda9762018-07-23 09:18:04 +0100974doesn't do anything. Since this API is called during the power down sequence,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100975it has restrictions for stack usage and it can use the registers x0 - x17 as
976scratch registers. It should preserve the value in x18 register as it is used
977by the caller to store the return address.
978
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100979Function : plat_error_handler()
980~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100981
982::
983
984 Argument : int
985 Return : void
986
987This API is called when the generic code encounters an error situation from
988which it cannot continue. It allows the platform to perform error reporting or
989recovery actions (for example, reset the system). This function must not return.
990
991The parameter indicates the type of error using standard codes from ``errno.h``.
992Possible errors reported by the generic code are:
993
994- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted
995 Board Boot is enabled)
996- ``-ENOENT``: the requested image or certificate could not be found or an IO
997 error was detected
Dan Handley610e7e12018-03-01 18:44:00 +0000998- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this
999 error is usually an indication of an incorrect array size
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001000
1001The default implementation simply spins.
1002
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001003Function : plat_panic_handler()
1004~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001005
1006::
1007
1008 Argument : void
1009 Return : void
1010
1011This API is called when the generic code encounters an unexpected error
1012situation from which it cannot recover. This function must not return,
1013and must be implemented in assembly because it may be called before the C
1014environment is initialized.
1015
Paul Beesleyba3ed402019-03-13 16:20:44 +00001016.. note::
1017 The address from where it was called is stored in x30 (Link Register).
1018 The default implementation simply spins.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001019
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001020Function : plat_get_bl_image_load_info()
1021~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001022
1023::
1024
1025 Argument : void
1026 Return : bl_load_info_t *
1027
1028This function returns pointer to the list of images that the platform has
Soby Mathew97b1bff2018-09-27 16:46:41 +01001029populated to load. This function is invoked in BL2 to load the
1030BL3xx images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001031
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001032Function : plat_get_next_bl_params()
1033~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001034
1035::
1036
1037 Argument : void
1038 Return : bl_params_t *
1039
1040This function returns a pointer to the shared memory that the platform has
Dan Handley610e7e12018-03-01 18:44:00 +00001041kept aside to pass TF-A related information that next BL image needs. This
Soby Mathew97b1bff2018-09-27 16:46:41 +01001042function is invoked in BL2 to pass this information to the next BL
1043image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001044
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001045Function : plat_get_stack_protector_canary()
1046~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001047
1048::
1049
1050 Argument : void
1051 Return : u_register_t
1052
1053This function returns a random value that is used to initialize the canary used
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001054when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001055value will weaken the protection as the attacker could easily write the right
1056value as part of the attack most of the time. Therefore, it should return a
1057true random number.
1058
Paul Beesleyba3ed402019-03-13 16:20:44 +00001059.. warning::
1060 For the protection to be effective, the global data need to be placed at
1061 a lower address than the stack bases. Failure to do so would allow an
1062 attacker to overwrite the canary as part of the stack buffer overflow attack.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001063
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001064Function : plat_flush_next_bl_params()
1065~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001066
1067::
1068
1069 Argument : void
1070 Return : void
1071
1072This function flushes to main memory all the image params that are passed to
Soby Mathew97b1bff2018-09-27 16:46:41 +01001073next image. This function is invoked in BL2 to flush this information
1074to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001075
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001076Function : plat_log_get_prefix()
1077~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewaaf15f52017-09-04 11:49:29 +01001078
1079::
1080
1081 Argument : unsigned int
1082 Return : const char *
1083
1084This function defines the prefix string corresponding to the `log_level` to be
Dan Handley610e7e12018-03-01 18:44:00 +00001085prepended to all the log output from TF-A. The `log_level` (argument) will
1086correspond to one of the standard log levels defined in debug.h. The platform
1087can override the common implementation to define a different prefix string for
John Tsichritzis30f89642018-06-07 16:31:34 +01001088the log output. The implementation should be robust to future changes that
Dan Handley610e7e12018-03-01 18:44:00 +00001089increase the number of log levels.
Soby Mathewaaf15f52017-09-04 11:49:29 +01001090
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001091Modifications specific to a Boot Loader stage
1092---------------------------------------------
1093
1094Boot Loader Stage 1 (BL1)
1095-------------------------
1096
1097BL1 implements the reset vector where execution starts from after a cold or
1098warm boot. For each CPU, BL1 is responsible for the following tasks:
1099
1100#. Handling the reset as described in section 2.2
1101
1102#. In the case of a cold boot and the CPU being the primary CPU, ensuring that
1103 only this CPU executes the remaining BL1 code, including loading and passing
1104 control to the BL2 stage.
1105
1106#. Identifying and starting the Firmware Update process (if required).
1107
1108#. Loading the BL2 image from non-volatile storage into secure memory at the
1109 address specified by the platform defined constant ``BL2_BASE``.
1110
1111#. Populating a ``meminfo`` structure with the following information in memory,
1112 accessible by BL2 immediately upon entry.
1113
1114 ::
1115
1116 meminfo.total_base = Base address of secure RAM visible to BL2
1117 meminfo.total_size = Size of secure RAM visible to BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001118
Soby Mathew97b1bff2018-09-27 16:46:41 +01001119 By default, BL1 places this ``meminfo`` structure at the end of secure
1120 memory visible to BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001121
Soby Mathewb1bf0442018-02-16 14:52:52 +00001122 It is possible for the platform to decide where it wants to place the
1123 ``meminfo`` structure for BL2 or restrict the amount of memory visible to
1124 BL2 by overriding the weak default implementation of
1125 ``bl1_plat_handle_post_image_load`` API.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001126
1127The following functions need to be implemented by the platform port to enable
1128BL1 to perform the above tasks.
1129
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001130Function : bl1_early_platform_setup() [mandatory]
1131~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001132
1133::
1134
1135 Argument : void
1136 Return : void
1137
1138This function executes with the MMU and data caches disabled. It is only called
1139by the primary CPU.
1140
Dan Handley610e7e12018-03-01 18:44:00 +00001141On Arm standard platforms, this function:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001142
1143- Enables a secure instance of SP805 to act as the Trusted Watchdog.
1144
1145- Initializes a UART (PL011 console), which enables access to the ``printf``
1146 family of functions in BL1.
1147
1148- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
1149 the CCI slave interface corresponding to the cluster that includes the
1150 primary CPU.
1151
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001152Function : bl1_plat_arch_setup() [mandatory]
1153~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001154
1155::
1156
1157 Argument : void
1158 Return : void
1159
1160This function performs any platform-specific and architectural setup that the
1161platform requires. Platform-specific setup might include configuration of
1162memory controllers and the interconnect.
1163
Dan Handley610e7e12018-03-01 18:44:00 +00001164In Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001165
1166This function helps fulfill requirement 2 above.
1167
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001168Function : bl1_platform_setup() [mandatory]
1169~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001170
1171::
1172
1173 Argument : void
1174 Return : void
1175
1176This function executes with the MMU and data caches enabled. It is responsible
1177for performing any remaining platform-specific setup that can occur after the
1178MMU and data cache have been enabled.
1179
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001180if support for multiple boot sources is required, it initializes the boot
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001181sequence used by plat_try_next_boot_source().
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001182
Dan Handley610e7e12018-03-01 18:44:00 +00001183In Arm standard platforms, this function initializes the storage abstraction
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001184layer used to load the next bootloader image.
1185
1186This function helps fulfill requirement 4 above.
1187
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001188Function : bl1_plat_sec_mem_layout() [mandatory]
1189~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001190
1191::
1192
1193 Argument : void
1194 Return : meminfo *
1195
1196This function should only be called on the cold boot path. It executes with the
1197MMU and data caches enabled. The pointer returned by this function must point to
1198a ``meminfo`` structure containing the extents and availability of secure RAM for
1199the BL1 stage.
1200
1201::
1202
1203 meminfo.total_base = Base address of secure RAM visible to BL1
1204 meminfo.total_size = Size of secure RAM visible to BL1
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001205
1206This information is used by BL1 to load the BL2 image in secure RAM. BL1 also
1207populates a similar structure to tell BL2 the extents of memory available for
1208its own use.
1209
1210This function helps fulfill requirements 4 and 5 above.
1211
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001212Function : bl1_plat_prepare_exit() [optional]
1213~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001214
1215::
1216
1217 Argument : entry_point_info_t *
1218 Return : void
1219
1220This function is called prior to exiting BL1 in response to the
1221``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform
1222platform specific clean up or bookkeeping operations before transferring
1223control to the next image. It receives the address of the ``entry_point_info_t``
1224structure passed from BL2. This function runs with MMU disabled.
1225
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001226Function : bl1_plat_set_ep_info() [optional]
1227~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001228
1229::
1230
1231 Argument : unsigned int image_id, entry_point_info_t *ep_info
1232 Return : void
1233
1234This function allows platforms to override ``ep_info`` for the given ``image_id``.
1235
1236The default implementation just returns.
1237
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001238Function : bl1_plat_get_next_image_id() [optional]
1239~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001240
1241::
1242
1243 Argument : void
1244 Return : unsigned int
1245
1246This and the following function must be overridden to enable the FWU feature.
1247
1248BL1 calls this function after platform setup to identify the next image to be
1249loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds
1250with the normal boot sequence, which loads and executes BL2. If the platform
1251returns a different image id, BL1 assumes that Firmware Update is required.
1252
Dan Handley610e7e12018-03-01 18:44:00 +00001253The default implementation always returns ``BL2_IMAGE_ID``. The Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001254platforms override this function to detect if firmware update is required, and
1255if so, return the first image in the firmware update process.
1256
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001257Function : bl1_plat_get_image_desc() [optional]
1258~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001259
1260::
1261
1262 Argument : unsigned int image_id
1263 Return : image_desc_t *
1264
1265BL1 calls this function to get the image descriptor information ``image_desc_t``
1266for the provided ``image_id`` from the platform.
1267
Dan Handley610e7e12018-03-01 18:44:00 +00001268The default implementation always returns a common BL2 image descriptor. Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001269standard platforms return an image descriptor corresponding to BL2 or one of
1270the firmware update images defined in the Trusted Board Boot Requirements
1271specification.
1272
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001273Function : bl1_plat_handle_pre_image_load() [optional]
1274~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001275
1276::
1277
Soby Mathew2f38ce32018-02-08 17:45:12 +00001278 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001279 Return : int
1280
1281This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001282corresponding to ``image_id``. This function is invoked in BL1, both in cold
1283boot and FWU code path, before loading the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001284
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001285Function : bl1_plat_handle_post_image_load() [optional]
1286~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001287
1288::
1289
Soby Mathew2f38ce32018-02-08 17:45:12 +00001290 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001291 Return : int
1292
1293This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001294corresponding to ``image_id``. This function is invoked in BL1, both in cold
1295boot and FWU code path, after loading and authenticating the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001296
Soby Mathewb1bf0442018-02-16 14:52:52 +00001297The default weak implementation of this function calculates the amount of
1298Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t``
1299structure at the beginning of this free memory and populates it. The address
1300of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
1301information to BL2.
1302
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001303Function : bl1_plat_fwu_done() [optional]
1304~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001305
1306::
1307
1308 Argument : unsigned int image_id, uintptr_t image_src,
1309 unsigned int image_size
1310 Return : void
1311
1312BL1 calls this function when the FWU process is complete. It must not return.
1313The platform may override this function to take platform specific action, for
1314example to initiate the normal boot flow.
1315
1316The default implementation spins forever.
1317
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001318Function : bl1_plat_mem_check() [mandatory]
1319~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001320
1321::
1322
1323 Argument : uintptr_t mem_base, unsigned int mem_size,
1324 unsigned int flags
1325 Return : int
1326
1327BL1 calls this function while handling FWU related SMCs, more specifically when
1328copying or authenticating an image. Its responsibility is to ensure that the
1329region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and
1330that this memory corresponds to either a secure or non-secure memory region as
1331indicated by the security state of the ``flags`` argument.
1332
1333This function can safely assume that the value resulting from the addition of
1334``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not
1335overflow.
1336
1337This function must return 0 on success, a non-null error code otherwise.
1338
1339The default implementation of this function asserts therefore platforms must
1340override it when using the FWU feature.
1341
1342Boot Loader Stage 2 (BL2)
1343-------------------------
1344
1345The BL2 stage is executed only by the primary CPU, which is determined in BL1
1346using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
Soby Mathew97b1bff2018-09-27 16:46:41 +01001347``BL2_BASE``. BL2 executes in Secure EL1 and and invokes
1348``plat_get_bl_image_load_info()`` to retrieve the list of images to load from
1349non-volatile storage to secure/non-secure RAM. After all the images are loaded
1350then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable
1351images to be passed to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001352
1353The following functions must be implemented by the platform port to enable BL2
1354to perform the above tasks.
1355
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001356Function : bl2_early_platform_setup2() [mandatory]
1357~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001358
1359::
1360
Soby Mathew97b1bff2018-09-27 16:46:41 +01001361 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001362 Return : void
1363
1364This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001365by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments
1366are platform specific.
1367
1368On Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001369
Soby Mathew97b1bff2018-09-27 16:46:41 +01001370 arg0 - Points to load address of HW_CONFIG if present
1371
1372 arg1 - ``meminfo`` structure populated by BL1. The platform copies
1373 the contents of ``meminfo`` as it may be subsequently overwritten by BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001374
Dan Handley610e7e12018-03-01 18:44:00 +00001375On Arm standard platforms, this function also:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001376
1377- Initializes a UART (PL011 console), which enables access to the ``printf``
1378 family of functions in BL2.
1379
1380- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001381 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1382 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001383
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001384Function : bl2_plat_arch_setup() [mandatory]
1385~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001386
1387::
1388
1389 Argument : void
1390 Return : void
1391
1392This function executes with the MMU and data caches disabled. It is only called
1393by the primary CPU.
1394
1395The purpose of this function is to perform any architectural initialization
1396that varies across platforms.
1397
Dan Handley610e7e12018-03-01 18:44:00 +00001398On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001399
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001400Function : bl2_platform_setup() [mandatory]
1401~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001402
1403::
1404
1405 Argument : void
1406 Return : void
1407
1408This function may execute with the MMU and data caches enabled if the platform
1409port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only
1410called by the primary CPU.
1411
1412The purpose of this function is to perform any platform initialization
1413specific to BL2.
1414
Dan Handley610e7e12018-03-01 18:44:00 +00001415In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001416configuration of the TrustZone controller to allow non-secure masters access
1417to most of DRAM. Part of DRAM is reserved for secure world use.
1418
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001419Function : bl2_plat_handle_pre_image_load() [optional]
1420~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001421
1422::
1423
1424 Argument : unsigned int
1425 Return : int
1426
1427This function can be used by the platforms to update/use image information
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001428for given ``image_id``. This function is currently invoked in BL2 before
Soby Mathew97b1bff2018-09-27 16:46:41 +01001429loading each image.
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001430
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001431Function : bl2_plat_handle_post_image_load() [optional]
1432~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001433
1434::
1435
1436 Argument : unsigned int
1437 Return : int
1438
1439This function can be used by the platforms to update/use image information
1440for given ``image_id``. This function is currently invoked in BL2 after
Soby Mathew97b1bff2018-09-27 16:46:41 +01001441loading each image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001442
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001443Function : bl2_plat_preload_setup [optional]
1444~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001445
1446::
John Tsichritzisee10e792018-06-06 09:38:10 +01001447
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001448 Argument : void
1449 Return : void
1450
1451This optional function performs any BL2 platform initialization
1452required before image loading, that is not done later in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001453bl2_platform_setup(). Specifically, if support for multiple
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001454boot sources is required, it initializes the boot sequence used by
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001455plat_try_next_boot_source().
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001456
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001457Function : plat_try_next_boot_source() [optional]
1458~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001459
1460::
John Tsichritzisee10e792018-06-06 09:38:10 +01001461
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001462 Argument : void
1463 Return : int
1464
1465This optional function passes to the next boot source in the redundancy
1466sequence.
1467
1468This function moves the current boot redundancy source to the next
1469element in the boot sequence. If there are no more boot sources then it
1470must return 0, otherwise it must return 1. The default implementation
1471of this always returns 0.
1472
Roberto Vargasb1584272017-11-20 13:36:10 +00001473Boot Loader Stage 2 (BL2) at EL3
1474--------------------------------
1475
Dan Handley610e7e12018-03-01 18:44:00 +00001476When the platform has a non-TF-A Boot ROM it is desirable to jump
1477directly to BL2 instead of TF-A BL1. In this case BL2 is expected to
Roberto Vargasb1584272017-11-20 13:36:10 +00001478execute at EL3 instead of executing at EL1. Refer to the `Firmware
1479Design`_ for more information.
1480
1481All mandatory functions of BL2 must be implemented, except the functions
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001482bl2_early_platform_setup and bl2_el3_plat_arch_setup, because
1483their work is done now by bl2_el3_early_platform_setup and
1484bl2_el3_plat_arch_setup. These functions should generally implement
1485the bl1_plat_xxx() and bl2_plat_xxx() functionality combined.
Roberto Vargasb1584272017-11-20 13:36:10 +00001486
1487
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001488Function : bl2_el3_early_platform_setup() [mandatory]
1489~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001490
1491::
John Tsichritzisee10e792018-06-06 09:38:10 +01001492
Roberto Vargasb1584272017-11-20 13:36:10 +00001493 Argument : u_register_t, u_register_t, u_register_t, u_register_t
1494 Return : void
1495
1496This function executes with the MMU and data caches disabled. It is only called
1497by the primary CPU. This function receives four parameters which can be used
1498by the platform to pass any needed information from the Boot ROM to BL2.
1499
Dan Handley610e7e12018-03-01 18:44:00 +00001500On Arm standard platforms, this function does the following:
Roberto Vargasb1584272017-11-20 13:36:10 +00001501
1502- Initializes a UART (PL011 console), which enables access to the ``printf``
1503 family of functions in BL2.
1504
1505- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001506 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1507 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Roberto Vargasb1584272017-11-20 13:36:10 +00001508
1509- Initializes the private variables that define the memory layout used.
1510
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001511Function : bl2_el3_plat_arch_setup() [mandatory]
1512~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001513
1514::
John Tsichritzisee10e792018-06-06 09:38:10 +01001515
Roberto Vargasb1584272017-11-20 13:36:10 +00001516 Argument : void
1517 Return : void
1518
1519This function executes with the MMU and data caches disabled. It is only called
1520by the primary CPU.
1521
1522The purpose of this function is to perform any architectural initialization
1523that varies across platforms.
1524
Dan Handley610e7e12018-03-01 18:44:00 +00001525On Arm standard platforms, this function enables the MMU.
Roberto Vargasb1584272017-11-20 13:36:10 +00001526
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001527Function : bl2_el3_plat_prepare_exit() [optional]
1528~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001529
1530::
John Tsichritzisee10e792018-06-06 09:38:10 +01001531
Roberto Vargasb1584272017-11-20 13:36:10 +00001532 Argument : void
1533 Return : void
1534
1535This function is called prior to exiting BL2 and run the next image.
1536It should be used to perform platform specific clean up or bookkeeping
1537operations before transferring control to the next image. This function
1538runs with MMU disabled.
1539
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001540FWU Boot Loader Stage 2 (BL2U)
1541------------------------------
1542
1543The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU
1544process and is executed only by the primary CPU. BL1 passes control to BL2U at
1545``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
1546
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001547#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure
1548 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1.
1549 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U
1550 should be copied from. Subsequent handling of the SCP_BL2U image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001551 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
1552 If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
1553
1554#. Any platform specific setup required to perform the FWU process. For
Dan Handley610e7e12018-03-01 18:44:00 +00001555 example, Arm standard platforms initialize the TZC controller so that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001556 normal world can access DDR memory.
1557
1558The following functions must be implemented by the platform port to enable
1559BL2U to perform the tasks mentioned above.
1560
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001561Function : bl2u_early_platform_setup() [mandatory]
1562~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001563
1564::
1565
1566 Argument : meminfo *mem_info, void *plat_info
1567 Return : void
1568
1569This function executes with the MMU and data caches disabled. It is only
1570called by the primary CPU. The arguments to this function is the address
1571of the ``meminfo`` structure and platform specific info provided by BL1.
1572
1573The platform may copy the contents of the ``mem_info`` and ``plat_info`` into
1574private storage as the original memory may be subsequently overwritten by BL2U.
1575
Dan Handley610e7e12018-03-01 18:44:00 +00001576On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001577to extract SCP_BL2U image information, which is then copied into a private
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001578variable.
1579
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001580Function : bl2u_plat_arch_setup() [mandatory]
1581~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001582
1583::
1584
1585 Argument : void
1586 Return : void
1587
1588This function executes with the MMU and data caches disabled. It is only
1589called by the primary CPU.
1590
1591The purpose of this function is to perform any architectural initialization
1592that varies across platforms, for example enabling the MMU (since the memory
1593map differs across platforms).
1594
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001595Function : bl2u_platform_setup() [mandatory]
1596~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001597
1598::
1599
1600 Argument : void
1601 Return : void
1602
1603This function may execute with the MMU and data caches enabled if the platform
1604port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only
1605called by the primary CPU.
1606
1607The purpose of this function is to perform any platform initialization
1608specific to BL2U.
1609
Dan Handley610e7e12018-03-01 18:44:00 +00001610In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001611configuration of the TrustZone controller to allow non-secure masters access
1612to most of DRAM. Part of DRAM is reserved for secure world use.
1613
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001614Function : bl2u_plat_handle_scp_bl2u() [optional]
1615~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001616
1617::
1618
1619 Argument : void
1620 Return : int
1621
1622This function is used to perform any platform-specific actions required to
1623handle the SCP firmware. Typically it transfers the image into SCP memory using
1624a platform-specific protocol and waits until SCP executes it and signals to the
1625Application Processor (AP) for BL2U execution to continue.
1626
1627This function returns 0 on success, a negative error code otherwise.
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001628This function is included if SCP_BL2U_BASE is defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001629
1630Boot Loader Stage 3-1 (BL31)
1631----------------------------
1632
1633During cold boot, the BL31 stage is executed only by the primary CPU. This is
1634determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes
1635control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all
1636CPUs. BL31 executes at EL3 and is responsible for:
1637
1638#. Re-initializing all architectural and platform state. Although BL1 performs
1639 some of this initialization, BL31 remains resident in EL3 and must ensure
1640 that EL3 architectural and platform state is completely initialized. It
1641 should make no assumptions about the system state when it receives control.
1642
1643#. Passing control to a normal world BL image, pre-loaded at a platform-
Soby Mathew97b1bff2018-09-27 16:46:41 +01001644 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list
1645 populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001646
1647#. Providing runtime firmware services. Currently, BL31 only implements a
1648 subset of the Power State Coordination Interface (PSCI) API as a runtime
1649 service. See Section 3.3 below for details of porting the PSCI
1650 implementation.
1651
1652#. Optionally passing control to the BL32 image, pre-loaded at a platform-
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001653 specific address by BL2. BL31 exports a set of APIs that allow runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001654 services to specify the security state in which the next image should be
Soby Mathew97b1bff2018-09-27 16:46:41 +01001655 executed and run the corresponding image. On ARM platforms, BL31 uses the
1656 ``bl_params`` list populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001657
1658If BL31 is a reset vector, It also needs to handle the reset as specified in
1659section 2.2 before the tasks described above.
1660
1661The following functions must be implemented by the platform port to enable BL31
1662to perform the above tasks.
1663
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001664Function : bl31_early_platform_setup2() [mandatory]
1665~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001666
1667::
1668
Soby Mathew97b1bff2018-09-27 16:46:41 +01001669 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001670 Return : void
1671
1672This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001673by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are
1674platform specific.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001675
Soby Mathew97b1bff2018-09-27 16:46:41 +01001676In Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001677
Soby Mathew97b1bff2018-09-27 16:46:41 +01001678 arg0 - The pointer to the head of `bl_params_t` list
1679 which is list of executable images following BL31,
1680
1681 arg1 - Points to load address of SOC_FW_CONFIG if present
1682
1683 arg2 - Points to load address of HW_CONFIG if present
1684
1685 arg3 - A special value to verify platform parameters from BL2 to BL31. Not
1686 used in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001687
Soby Mathew97b1bff2018-09-27 16:46:41 +01001688The function runs through the `bl_param_t` list and extracts the entry point
1689information for BL32 and BL33. It also performs the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001690
1691- Initialize a UART (PL011 console), which enables access to the ``printf``
1692 family of functions in BL31.
1693
1694- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
1695 CCI slave interface corresponding to the cluster that includes the primary
1696 CPU.
1697
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001698Function : bl31_plat_arch_setup() [mandatory]
1699~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001700
1701::
1702
1703 Argument : void
1704 Return : void
1705
1706This function executes with the MMU and data caches disabled. It is only called
1707by the primary CPU.
1708
1709The purpose of this function is to perform any architectural initialization
1710that varies across platforms.
1711
Dan Handley610e7e12018-03-01 18:44:00 +00001712On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001713
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001714Function : bl31_platform_setup() [mandatory]
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001715~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1716
1717::
1718
1719 Argument : void
1720 Return : void
1721
1722This function may execute with the MMU and data caches enabled if the platform
1723port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only
1724called by the primary CPU.
1725
1726The purpose of this function is to complete platform initialization so that both
1727BL31 runtime services and normal world software can function correctly.
1728
Dan Handley610e7e12018-03-01 18:44:00 +00001729On Arm standard platforms, this function does the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001730
1731- Initialize the generic interrupt controller.
1732
1733 Depending on the GIC driver selected by the platform, the appropriate GICv2
1734 or GICv3 initialization will be done, which mainly consists of:
1735
1736 - Enable secure interrupts in the GIC CPU interface.
1737 - Disable the legacy interrupt bypass mechanism.
1738 - Configure the priority mask register to allow interrupts of all priorities
1739 to be signaled to the CPU interface.
1740 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure.
1741 - Target all secure SPIs to CPU0.
1742 - Enable these secure interrupts in the GIC distributor.
1743 - Configure all other interrupts as non-secure.
1744 - Enable signaling of secure interrupts in the GIC distributor.
1745
1746- Enable system-level implementation of the generic timer counter through the
1747 memory mapped interface.
1748
1749- Grant access to the system counter timer module
1750
1751- Initialize the power controller device.
1752
1753 In particular, initialise the locks that prevent concurrent accesses to the
1754 power controller device.
1755
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001756Function : bl31_plat_runtime_setup() [optional]
1757~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001758
1759::
1760
1761 Argument : void
1762 Return : void
1763
1764The purpose of this function is allow the platform to perform any BL31 runtime
1765setup just prior to BL31 exit during cold boot. The default weak
Julius Werneraae9bb12017-09-18 16:49:48 -07001766implementation of this function will invoke ``console_switch_state()`` to switch
1767console output to consoles marked for use in the ``runtime`` state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001768
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001769Function : bl31_plat_get_next_image_ep_info() [mandatory]
1770~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001771
1772::
1773
Sandrine Bailleux842117d2018-05-14 14:25:47 +02001774 Argument : uint32_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001775 Return : entry_point_info *
1776
1777This function may execute with the MMU and data caches enabled if the platform
1778port does the necessary initializations in ``bl31_plat_arch_setup()``.
1779
1780This function is called by ``bl31_main()`` to retrieve information provided by
1781BL2 for the next image in the security state specified by the argument. BL31
1782uses this information to pass control to that image in the specified security
1783state. This function must return a pointer to the ``entry_point_info`` structure
1784(that was copied during ``bl31_early_platform_setup()``) if the image exists. It
1785should return NULL otherwise.
1786
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01001787Function : bl31_plat_enable_mmu [optional]
1788~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1789
1790::
1791
1792 Argument : uint32_t
1793 Return : void
1794
1795This function enables the MMU. The boot code calls this function with MMU and
1796caches disabled. This function should program necessary registers to enable
1797translation, and upon return, the MMU on the calling PE must be enabled.
1798
1799The function must honor flags passed in the first argument. These flags are
1800defined by the translation library, and can be found in the file
1801``include/lib/xlat_tables/xlat_mmu_helpers.h``.
1802
1803On DynamIQ systems, this function must not use stack while enabling MMU, which
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001804is how the function in xlat table library version 2 is implemented.
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01001805
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001806Function : plat_init_apkey [optional]
1807~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00001808
1809::
1810
1811 Argument : void
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001812 Return : uint128_t
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00001813
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001814This function returns the 128-bit value which can be used to program ARMv8.3
1815pointer authentication keys.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00001816
1817The value should be obtained from a reliable source of randomness.
1818
1819This function is only needed if ARMv8.3 pointer authentication is used in the
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001820Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00001821
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001822Function : plat_get_syscnt_freq2() [mandatory]
1823~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001824
1825::
1826
1827 Argument : void
1828 Return : unsigned int
1829
1830This function is used by the architecture setup code to retrieve the counter
1831frequency for the CPU's generic timer. This value will be programmed into the
Dan Handley610e7e12018-03-01 18:44:00 +00001832``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001833of the system counter, which is retrieved from the first entry in the frequency
1834modes table.
1835
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001836#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
1837~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001838
1839When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
1840bytes) aligned to the cache line boundary that should be allocated per-cpu to
1841accommodate all the bakery locks.
1842
1843If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker
1844calculates the size of the ``bakery_lock`` input section, aligns it to the
1845nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT``
1846and stores the result in a linker symbol. This constant prevents a platform
1847from relying on the linker and provide a more efficient mechanism for
1848accessing per-cpu bakery lock information.
1849
1850If this constant is defined and its value is not equal to the value
1851calculated by the linker then a link time assertion is raised. A compile time
1852assertion is raised if the value of the constant is not aligned to the cache
1853line boundary.
1854
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001855SDEI porting requirements
1856~~~~~~~~~~~~~~~~~~~~~~~~~
1857
Paul Beesley606d8072019-03-13 13:58:02 +00001858The |SDEI| dispatcher requires the platform to provide the following macros
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001859and functions, of which some are optional, and some others mandatory.
1860
1861Macros
1862......
1863
1864Macro: PLAT_SDEI_NORMAL_PRI [mandatory]
1865^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1866
1867This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00001868Normal |SDEI| events on the platform. This must have a higher value
1869(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001870
1871Macro: PLAT_SDEI_CRITICAL_PRI [mandatory]
1872^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1873
1874This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00001875Critical |SDEI| events on the platform. This must have a lower value
1876(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001877
Paul Beesley606d8072019-03-13 13:58:02 +00001878**Note**: |SDEI| exception priorities must be the lowest among Secure
1879priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
1880be higher than Normal |SDEI| priority.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001881
1882Functions
1883.........
1884
1885Function: int plat_sdei_validate_entry_point(uintptr_t ep) [optional]
1886^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1887
1888::
1889
1890 Argument: uintptr_t
1891 Return: int
1892
1893This function validates the address of client entry points provided for both
Paul Beesley606d8072019-03-13 13:58:02 +00001894event registration and *Complete and Resume* |SDEI| calls. The function
1895takes one argument, which is the address of the handler the |SDEI| client
1896requested to register. The function must return ``0`` for successful validation,
1897or ``-1`` upon failure.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001898
Dan Handley610e7e12018-03-01 18:44:00 +00001899The default implementation always returns ``0``. On Arm platforms, this function
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001900is implemented to translate the entry point to physical address, and further to
1901ensure that the address is located in Non-secure DRAM.
1902
1903Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional]
1904^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1905
1906::
1907
1908 Argument: uint64_t
1909 Argument: unsigned int
1910 Return: void
1911
Paul Beesley606d8072019-03-13 13:58:02 +00001912|SDEI| specification requires that a PE comes out of reset with the events
1913masked. The client therefore is expected to call ``PE_UNMASK`` to unmask
1914|SDEI| events on the PE. No |SDEI| events can be dispatched until such
1915time.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001916
Paul Beesley606d8072019-03-13 13:58:02 +00001917Should a PE receive an interrupt that was bound to an |SDEI| event while the
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001918events are masked on the PE, the dispatcher implementation invokes the function
1919``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the
1920interrupt and the interrupt ID are passed as parameters.
1921
1922The default implementation only prints out a warning message.
1923
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001924Power State Coordination Interface (in BL31)
1925--------------------------------------------
1926
Dan Handley610e7e12018-03-01 18:44:00 +00001927The TF-A implementation of the PSCI API is based around the concept of a
1928*power domain*. A *power domain* is a CPU or a logical group of CPUs which
1929share some state on which power management operations can be performed as
1930specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is
1931a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The
1932*power domains* are arranged in a hierarchical tree structure and each
1933*power domain* can be identified in a system by the cpu index of any CPU that
1934is part of that domain and a *power domain level*. A processing element (for
1935example, a CPU) is at level 0. If the *power domain* node above a CPU is a
1936logical grouping of CPUs that share some state, then level 1 is that group of
1937CPUs (for example, a cluster), and level 2 is a group of clusters (for
1938example, the system). More details on the power domain topology and its
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001939organization can be found in `Power Domain Topology Design`_.
1940
1941BL31's platform initialization code exports a pointer to the platform-specific
1942power management operations required for the PSCI implementation to function
1943correctly. This information is populated in the ``plat_psci_ops`` structure. The
1944PSCI implementation calls members of the ``plat_psci_ops`` structure for performing
1945power management operations on the power domains. For example, the target
1946CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
1947handler (if present) is called for the CPU power domain.
1948
1949The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to
1950describe composite power states specific to a platform. The PSCI implementation
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00001951defines a generic representation of the power-state parameter, which is an
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001952array of local power states where each index corresponds to a power domain
1953level. Each entry contains the local power state the power domain at that power
1954level could enter. It depends on the ``validate_power_state()`` handler to
1955convert the power-state parameter (possibly encoding a composite power state)
1956passed in a PSCI ``CPU_SUSPEND`` call to this representation.
1957
1958The following functions form part of platform port of PSCI functionality.
1959
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001960Function : plat_psci_stat_accounting_start() [optional]
1961~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001962
1963::
1964
1965 Argument : const psci_power_state_t *
1966 Return : void
1967
1968This is an optional hook that platforms can implement for residency statistics
1969accounting before entering a low power state. The ``pwr_domain_state`` field of
1970``state_info`` (first argument) can be inspected if stat accounting is done
1971differently at CPU level versus higher levels. As an example, if the element at
1972index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
1973state, special hardware logic may be programmed in order to keep track of the
1974residency statistics. For higher levels (array indices > 0), the residency
1975statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
1976default implementation will use PMF to capture timestamps.
1977
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001978Function : plat_psci_stat_accounting_stop() [optional]
1979~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001980
1981::
1982
1983 Argument : const psci_power_state_t *
1984 Return : void
1985
1986This is an optional hook that platforms can implement for residency statistics
1987accounting after exiting from a low power state. The ``pwr_domain_state`` field
1988of ``state_info`` (first argument) can be inspected if stat accounting is done
1989differently at CPU level versus higher levels. As an example, if the element at
1990index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
1991state, special hardware logic may be programmed in order to keep track of the
1992residency statistics. For higher levels (array indices > 0), the residency
1993statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
1994default implementation will use PMF to capture timestamps.
1995
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001996Function : plat_psci_stat_get_residency() [optional]
1997~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001998
1999::
2000
2001 Argument : unsigned int, const psci_power_state_t *, int
2002 Return : u_register_t
2003
2004This is an optional interface that is is invoked after resuming from a low power
2005state and provides the time spent resident in that low power state by the power
2006domain at a particular power domain level. When a CPU wakes up from suspend,
2007all its parent power domain levels are also woken up. The generic PSCI code
2008invokes this function for each parent power domain that is resumed and it
2009identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
2010argument) describes the low power state that the power domain has resumed from.
2011The current CPU is the first CPU in the power domain to resume from the low
2012power state and the ``last_cpu_idx`` (third parameter) is the index of the last
2013CPU in the power domain to suspend and may be needed to calculate the residency
2014for that power domain.
2015
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002016Function : plat_get_target_pwr_state() [optional]
2017~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002018
2019::
2020
2021 Argument : unsigned int, const plat_local_state_t *, unsigned int
2022 Return : plat_local_state_t
2023
2024The PSCI generic code uses this function to let the platform participate in
2025state coordination during a power management operation. The function is passed
2026a pointer to an array of platform specific local power state ``states`` (second
2027argument) which contains the requested power state for each CPU at a particular
2028power domain level ``lvl`` (first argument) within the power domain. The function
2029is expected to traverse this array of upto ``ncpus`` (third argument) and return
2030a coordinated target power state by the comparing all the requested power
2031states. The target power state should not be deeper than any of the requested
2032power states.
2033
2034A weak definition of this API is provided by default wherein it assumes
2035that the platform assigns a local state value in order of increasing depth
2036of the power state i.e. for two power states X & Y, if X < Y
2037then X represents a shallower power state than Y. As a result, the
2038coordinated target local power state for a power domain will be the minimum
2039of the requested local power state values.
2040
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002041Function : plat_get_power_domain_tree_desc() [mandatory]
2042~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002043
2044::
2045
2046 Argument : void
2047 Return : const unsigned char *
2048
2049This function returns a pointer to the byte array containing the power domain
2050topology tree description. The format and method to construct this array are
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002051described in `Power Domain Topology Design`_. The BL31 PSCI initialization code
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002052requires this array to be described by the platform, either statically or
2053dynamically, to initialize the power domain topology tree. In case the array
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002054is populated dynamically, then plat_core_pos_by_mpidr() and
2055plat_my_core_pos() should also be implemented suitably so that the topology
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002056tree description matches the CPU indices returned by these APIs. These APIs
2057together form the platform interface for the PSCI topology framework.
2058
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002059Function : plat_setup_psci_ops() [mandatory]
2060~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002061
2062::
2063
2064 Argument : uintptr_t, const plat_psci_ops **
2065 Return : int
2066
2067This function may execute with the MMU and data caches enabled if the platform
2068port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
2069called by the primary CPU.
2070
2071This function is called by PSCI initialization code. Its purpose is to let
2072the platform layer know about the warm boot entrypoint through the
2073``sec_entrypoint`` (first argument) and to export handler routines for
2074platform-specific psci power management actions by populating the passed
2075pointer with a pointer to BL31's private ``plat_psci_ops`` structure.
2076
2077A description of each member of this structure is given below. Please refer to
Dan Handley610e7e12018-03-01 18:44:00 +00002078the Arm FVP specific implementation of these handlers in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002079`plat/arm/board/fvp/fvp_pm.c`_ as an example. For each PSCI function that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002080platform wants to support, the associated operation or operations in this
2081structure must be provided and implemented (Refer section 4 of
Dan Handley610e7e12018-03-01 18:44:00 +00002082`Firmware Design`_ for the PSCI API supported in TF-A). To disable a PSCI
2083function in a platform port, the operation should be removed from this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002084structure instead of providing an empty implementation.
2085
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002086plat_psci_ops.cpu_standby()
2087...........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002088
2089Perform the platform-specific actions to enter the standby state for a cpu
2090indicated by the passed argument. This provides a fast path for CPU standby
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002091wherein overheads of PSCI state management and lock acquisition is avoided.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002092For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
2093the suspend state type specified in the ``power-state`` parameter should be
2094STANDBY and the target power domain level specified should be the CPU. The
2095handler should put the CPU into a low power retention state (usually by
2096issuing a wfi instruction) and ensure that it can be woken up from that
2097state by a normal interrupt. The generic code expects the handler to succeed.
2098
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002099plat_psci_ops.pwr_domain_on()
2100.............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002101
2102Perform the platform specific actions to power on a CPU, specified
2103by the ``MPIDR`` (first argument). The generic code expects the platform to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002104return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002105
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002106plat_psci_ops.pwr_domain_off()
2107..............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002108
2109Perform the platform specific actions to prepare to power off the calling CPU
2110and its higher parent power domain levels as indicated by the ``target_state``
2111(first argument). It is called by the PSCI ``CPU_OFF`` API implementation.
2112
2113The ``target_state`` encodes the platform coordinated target local power states
2114for the CPU power domain and its parent power domain levels. The handler
2115needs to perform power management operation corresponding to the local state
2116at each power level.
2117
2118For this handler, the local power state for the CPU power domain will be a
2119power down state where as it could be either power down, retention or run state
2120for the higher power domain levels depending on the result of state
2121coordination. The generic code expects the handler to succeed.
2122
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002123plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
2124...........................................................
Varun Wadekarae87f4b2017-07-10 16:02:05 -07002125
2126This optional function may be used as a performance optimization to replace
2127or complement pwr_domain_suspend() on some platforms. Its calling semantics
2128are identical to pwr_domain_suspend(), except the PSCI implementation only
2129calls this function when suspending to a power down state, and it guarantees
2130that data caches are enabled.
2131
2132When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches
2133before calling pwr_domain_suspend(). If the target_state corresponds to a
2134power down state and it is safe to perform some or all of the platform
2135specific actions in that function with data caches enabled, it may be more
2136efficient to move those actions to this function. When HW_ASSISTED_COHERENCY
2137= 1, data caches remain enabled throughout, and so there is no advantage to
2138moving platform specific actions to this function.
2139
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002140plat_psci_ops.pwr_domain_suspend()
2141..................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002142
2143Perform the platform specific actions to prepare to suspend the calling
2144CPU and its higher parent power domain levels as indicated by the
2145``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND``
2146API implementation.
2147
2148The ``target_state`` has a similar meaning as described in
2149the ``pwr_domain_off()`` operation. It encodes the platform coordinated
2150target local power states for the CPU power domain and its parent
2151power domain levels. The handler needs to perform power management operation
2152corresponding to the local state at each power level. The generic code
2153expects the handler to succeed.
2154
Douglas Raillarda84996b2017-08-02 16:57:32 +01002155The difference between turning a power domain off versus suspending it is that
2156in the former case, the power domain is expected to re-initialize its state
2157when it is next powered on (see ``pwr_domain_on_finish()``). In the latter
2158case, the power domain is expected to save enough state so that it can resume
2159execution by restoring this state when its powered on (see
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002160``pwr_domain_suspend_finish()``).
2161
Douglas Raillarda84996b2017-08-02 16:57:32 +01002162When suspending a core, the platform can also choose to power off the GICv3
2163Redistributor and ITS through an implementation-defined sequence. To achieve
2164this safely, the ITS context must be saved first. The architectural part is
2165implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed
2166sequence is implementation defined and it is therefore the responsibility of
2167the platform code to implement the necessary sequence. Then the GIC
2168Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper.
2169Powering off the Redistributor requires the implementation to support it and it
2170is the responsibility of the platform code to execute the right implementation
2171defined sequence.
2172
2173When a system suspend is requested, the platform can also make use of the
2174``gicv3_distif_save()`` helper to save the context of the GIC Distributor after
2175it has saved the context of the Redistributors and ITS of all the cores in the
2176system. The context of the Distributor can be large and may require it to be
2177allocated in a special area if it cannot fit in the platform's global static
2178data, for example in DRAM. The Distributor can then be powered down using an
2179implementation-defined sequence.
2180
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002181plat_psci_ops.pwr_domain_pwr_down_wfi()
2182.......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002183
2184This is an optional function and, if implemented, is expected to perform
2185platform specific actions including the ``wfi`` invocation which allows the
2186CPU to powerdown. Since this function is invoked outside the PSCI locks,
2187the actions performed in this hook must be local to the CPU or the platform
2188must ensure that races between multiple CPUs cannot occur.
2189
2190The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
2191operation and it encodes the platform coordinated target local power states for
2192the CPU power domain and its parent power domain levels. This function must
2193not return back to the caller.
2194
2195If this function is not implemented by the platform, PSCI generic
2196implementation invokes ``psci_power_down_wfi()`` for power down.
2197
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002198plat_psci_ops.pwr_domain_on_finish()
2199....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002200
2201This function is called by the PSCI implementation after the calling CPU is
2202powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
2203It performs the platform-specific setup required to initialize enough state for
2204this CPU to enter the normal world and also provide secure runtime firmware
2205services.
2206
2207The ``target_state`` (first argument) is the prior state of the power domains
2208immediately before the CPU was turned on. It indicates which power domains
2209above the CPU might require initialization due to having previously been in
2210low power states. The generic code expects the handler to succeed.
2211
Madhukar Pappireddy33bd5142019-08-12 18:31:33 -05002212plat_psci_ops.pwr_domain_on_finish_late() [optional]
2213...........................................................
2214
2215This optional function is called by the PSCI implementation after the calling
2216CPU is fully powered on with respective data caches enabled. The calling CPU and
2217the associated cluster are guaranteed to be participating in coherency. This
2218function gives the flexibility to perform any platform-specific actions safely,
2219such as initialization or modification of shared data structures, without the
2220overhead of explicit cache maintainace operations.
2221
2222The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()``
2223operation. The generic code expects the handler to succeed.
2224
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002225plat_psci_ops.pwr_domain_suspend_finish()
2226.........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002227
2228This function is called by the PSCI implementation after the calling CPU is
2229powered on and released from reset in response to an asynchronous wakeup
2230event, for example a timer interrupt that was programmed by the CPU during the
2231``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
2232setup required to restore the saved state for this CPU to resume execution
2233in the normal world and also provide secure runtime firmware services.
2234
2235The ``target_state`` (first argument) has a similar meaning as described in
2236the ``pwr_domain_on_finish()`` operation. The generic code expects the platform
2237to succeed.
2238
Douglas Raillarda84996b2017-08-02 16:57:32 +01002239If the Distributor, Redistributors or ITS have been powered off as part of a
2240suspend, their context must be restored in this function in the reverse order
2241to how they were saved during suspend sequence.
2242
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002243plat_psci_ops.system_off()
2244..........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002245
2246This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
2247call. It performs the platform-specific system poweroff sequence after
2248notifying the Secure Payload Dispatcher.
2249
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002250plat_psci_ops.system_reset()
2251............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002252
2253This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
2254call. It performs the platform-specific system reset sequence after
2255notifying the Secure Payload Dispatcher.
2256
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002257plat_psci_ops.validate_power_state()
2258....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002259
2260This function is called by the PSCI implementation during the ``CPU_SUSPEND``
2261call to validate the ``power_state`` parameter of the PSCI API and if valid,
2262populate it in ``req_state`` (second argument) array as power domain level
2263specific local states. If the ``power_state`` is invalid, the platform must
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002264return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002265normal world PSCI client.
2266
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002267plat_psci_ops.validate_ns_entrypoint()
2268......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002269
2270This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
2271``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
2272parameter passed by the normal world. If the ``entry_point`` is invalid,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002273the platform must return PSCI_E_INVALID_ADDRESS as error, which is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002274propagated back to the normal world PSCI client.
2275
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002276plat_psci_ops.get_sys_suspend_power_state()
2277...........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002278
2279This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
2280call to get the ``req_state`` parameter from platform which encodes the power
2281domain level specific local states to suspend to system affinity level. The
2282``req_state`` will be utilized to do the PSCI state coordination and
2283``pwr_domain_suspend()`` will be invoked with the coordinated target state to
2284enter system suspend.
2285
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002286plat_psci_ops.get_pwr_lvl_state_idx()
2287.....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002288
2289This is an optional function and, if implemented, is invoked by the PSCI
2290implementation to convert the ``local_state`` (first argument) at a specified
2291``pwr_lvl`` (second argument) to an index between 0 and
2292``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform
2293supports more than two local power states at each power domain level, that is
2294``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
2295local power states.
2296
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002297plat_psci_ops.translate_power_state_by_mpidr()
2298..............................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002299
2300This is an optional function and, if implemented, verifies the ``power_state``
2301(second argument) parameter of the PSCI API corresponding to a target power
2302domain. The target power domain is identified by using both ``MPIDR`` (first
2303argument) and the power domain level encoded in ``power_state``. The power domain
2304level specific local states are to be extracted from ``power_state`` and be
2305populated in the ``output_state`` (third argument) array. The functionality
2306is similar to the ``validate_power_state`` function described above and is
2307envisaged to be used in case the validity of ``power_state`` depend on the
2308targeted power domain. If the ``power_state`` is invalid for the targeted power
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002309domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002310function is not implemented, then the generic implementation relies on
2311``validate_power_state`` function to translate the ``power_state``.
2312
2313This function can also be used in case the platform wants to support local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002314power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002315APIs as described in Section 5.18 of `PSCI`_.
2316
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002317plat_psci_ops.get_node_hw_state()
2318.................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002319
2320This is an optional function. If implemented this function is intended to return
2321the power state of a node (identified by the first parameter, the ``MPIDR``) in
2322the power domain topology (identified by the second parameter, ``power_level``),
2323as retrieved from a power controller or equivalent component on the platform.
2324Upon successful completion, the implementation must map and return the final
2325status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it
2326must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as
2327appropriate.
2328
2329Implementations are not expected to handle ``power_levels`` greater than
2330``PLAT_MAX_PWR_LVL``.
2331
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002332plat_psci_ops.system_reset2()
2333.............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002334
2335This is an optional function. If implemented this function is
2336called during the ``SYSTEM_RESET2`` call to perform a reset
2337based on the first parameter ``reset_type`` as specified in
2338`PSCI`_. The parameter ``cookie`` can be used to pass additional
2339reset information. If the ``reset_type`` is not supported, the
2340function must return ``PSCI_E_NOT_SUPPORTED``. For architectural
2341resets, all failures must return ``PSCI_E_INVALID_PARAMETERS``
2342and vendor reset can return other PSCI error codes as defined
2343in `PSCI`_. On success this function will not return.
2344
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002345plat_psci_ops.write_mem_protect()
2346.................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002347
2348This is an optional function. If implemented it enables or disables the
2349``MEM_PROTECT`` functionality based on the value of ``val``.
2350A non-zero value enables ``MEM_PROTECT`` and a value of zero
2351disables it. Upon encountering failures it must return a negative value
2352and on success it must return 0.
2353
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002354plat_psci_ops.read_mem_protect()
2355................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002356
2357This is an optional function. If implemented it returns the current
2358state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
2359failures it must return a negative value and on success it must
2360return 0.
2361
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002362plat_psci_ops.mem_protect_chk()
2363...............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002364
2365This is an optional function. If implemented it checks if a memory
2366region defined by a base address ``base`` and with a size of ``length``
2367bytes is protected by ``MEM_PROTECT``. If the region is protected
2368then it must return 0, otherwise it must return a negative number.
2369
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002370Interrupt Management framework (in BL31)
2371----------------------------------------
2372
2373BL31 implements an Interrupt Management Framework (IMF) to manage interrupts
2374generated in either security state and targeted to EL1 or EL2 in the non-secure
2375state or EL3/S-EL1 in the secure state. The design of this framework is
2376described in the `IMF Design Guide`_
2377
2378A platform should export the following APIs to support the IMF. The following
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002379text briefly describes each API and its implementation in Arm standard
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002380platforms. The API implementation depends upon the type of interrupt controller
Dan Handley610e7e12018-03-01 18:44:00 +00002381present in the platform. Arm standard platform layer supports both
2382`Arm Generic Interrupt Controller version 2.0 (GICv2)`_
2383and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the
2384FVP can be configured to use either GICv2 or GICv3 depending on the build flag
2385``FVP_USE_GIC_DRIVER`` (See FVP platform specific build options in
2386`User Guide`_ for more details).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002387
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002388See also: `Interrupt Controller Abstraction APIs`__.
2389
Paul Beesleyea225122019-02-11 17:54:45 +00002390.. __: ../design/platform-interrupt-controller-API.rst
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002391
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002392Function : plat_interrupt_type_to_line() [mandatory]
2393~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002394
2395::
2396
2397 Argument : uint32_t, uint32_t
2398 Return : uint32_t
2399
Dan Handley610e7e12018-03-01 18:44:00 +00002400The Arm processor signals an interrupt exception either through the IRQ or FIQ
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002401interrupt line. The specific line that is signaled depends on how the interrupt
2402controller (IC) reports different interrupt types from an execution context in
2403either security state. The IMF uses this API to determine which interrupt line
2404the platform IC uses to signal each type of interrupt supported by the framework
2405from a given security state. This API must be invoked at EL3.
2406
2407The first parameter will be one of the ``INTR_TYPE_*`` values (see
2408`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the
2409security state of the originating execution context. The return result is the
2410bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1,
2411FIQ=2.
2412
Dan Handley610e7e12018-03-01 18:44:00 +00002413In the case of Arm standard platforms using GICv2, S-EL1 interrupts are
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002414configured as FIQs and Non-secure interrupts as IRQs from either security
2415state.
2416
Dan Handley610e7e12018-03-01 18:44:00 +00002417In the case of Arm standard platforms using GICv3, the interrupt line to be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002418configured depends on the security state of the execution context when the
2419interrupt is signalled and are as follows:
2420
2421- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in
2422 NS-EL0/1/2 context.
2423- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ
2424 in the NS-EL0/1/2 context.
2425- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
2426 context.
2427
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002428Function : plat_ic_get_pending_interrupt_type() [mandatory]
2429~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002430
2431::
2432
2433 Argument : void
2434 Return : uint32_t
2435
2436This API returns the type of the highest priority pending interrupt at the
2437platform IC. The IMF uses the interrupt type to retrieve the corresponding
2438handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt
2439pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``,
2440``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3.
2441
Dan Handley610e7e12018-03-01 18:44:00 +00002442In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002443Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of
2444the pending interrupt. The type of interrupt depends upon the id value as
2445follows.
2446
2447#. id < 1022 is reported as a S-EL1 interrupt
2448#. id = 1022 is reported as a Non-secure interrupt.
2449#. id = 1023 is reported as an invalid interrupt type.
2450
Dan Handley610e7e12018-03-01 18:44:00 +00002451In the case of Arm standard platforms using GICv3, the system register
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002452``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
2453is read to determine the id of the pending interrupt. The type of interrupt
2454depends upon the id value as follows.
2455
2456#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt
2457#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt.
2458#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
2459#. All other interrupt id's are reported as EL3 interrupt.
2460
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002461Function : plat_ic_get_pending_interrupt_id() [mandatory]
2462~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002463
2464::
2465
2466 Argument : void
2467 Return : uint32_t
2468
2469This API returns the id of the highest priority pending interrupt at the
2470platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt
2471pending.
2472
Dan Handley610e7e12018-03-01 18:44:00 +00002473In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002474Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the
2475pending interrupt. The id that is returned by API depends upon the value of
2476the id read from the interrupt controller as follows.
2477
2478#. id < 1022. id is returned as is.
2479#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register*
2480 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
2481 This id is returned by the API.
2482#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned.
2483
Dan Handley610e7e12018-03-01 18:44:00 +00002484In the case of Arm standard platforms using GICv3, if the API is invoked from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002485EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt
2486group 0 Register*, is read to determine the id of the pending interrupt. The id
2487that is returned by API depends upon the value of the id read from the
2488interrupt controller as follows.
2489
2490#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is.
2491#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system
2492 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
2493 Register* is read to determine the id of the group 1 interrupt. This id
2494 is returned by the API as long as it is a valid interrupt id
2495#. If the id is any of the special interrupt identifiers,
2496 ``INTR_ID_UNAVAILABLE`` is returned.
2497
2498When the API invoked from S-EL1 for GICv3 systems, the id read from system
2499register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002500Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002501``INTR_ID_UNAVAILABLE`` is returned.
2502
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002503Function : plat_ic_acknowledge_interrupt() [mandatory]
2504~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002505
2506::
2507
2508 Argument : void
2509 Return : uint32_t
2510
2511This API is used by the CPU to indicate to the platform IC that processing of
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002512the highest pending interrupt has begun. It should return the raw, unmodified
2513value obtained from the interrupt controller when acknowledging an interrupt.
2514The actual interrupt number shall be extracted from this raw value using the API
2515`plat_ic_get_interrupt_id()`__.
2516
Paul Beesleyea225122019-02-11 17:54:45 +00002517.. __: ../design/platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002518
Dan Handley610e7e12018-03-01 18:44:00 +00002519This function in Arm standard platforms using GICv2, reads the *Interrupt
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002520Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
2521priority pending interrupt from pending to active in the interrupt controller.
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002522It returns the value read from the ``GICC_IAR``, unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002523
Dan Handley610e7e12018-03-01 18:44:00 +00002524In the case of Arm standard platforms using GICv3, if the API is invoked
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002525from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt
2526Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
2527reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register
2528group 1*. The read changes the state of the highest pending interrupt from
2529pending to active in the interrupt controller. The value read is returned
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002530unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002531
2532The TSP uses this API to start processing of the secure physical timer
2533interrupt.
2534
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002535Function : plat_ic_end_of_interrupt() [mandatory]
2536~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002537
2538::
2539
2540 Argument : uint32_t
2541 Return : void
2542
2543This API is used by the CPU to indicate to the platform IC that processing of
2544the interrupt corresponding to the id (passed as the parameter) has
2545finished. The id should be the same as the id returned by the
2546``plat_ic_acknowledge_interrupt()`` API.
2547
Dan Handley610e7e12018-03-01 18:44:00 +00002548Arm standard platforms write the id to the *End of Interrupt Register*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002549(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1``
2550system register in case of GICv3 depending on where the API is invoked from,
2551EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt
2552controller.
2553
2554The TSP uses this API to finish processing of the secure physical timer
2555interrupt.
2556
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002557Function : plat_ic_get_interrupt_type() [mandatory]
2558~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002559
2560::
2561
2562 Argument : uint32_t
2563 Return : uint32_t
2564
2565This API returns the type of the interrupt id passed as the parameter.
2566``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid
2567interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is
2568returned depending upon how the interrupt has been configured by the platform
2569IC. This API must be invoked at EL3.
2570
Dan Handley610e7e12018-03-01 18:44:00 +00002571Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002572and Non-secure interrupts as Group1 interrupts. It reads the group value
2573corresponding to the interrupt id from the relevant *Interrupt Group Register*
2574(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.
2575
Dan Handley610e7e12018-03-01 18:44:00 +00002576In the case of Arm standard platforms using GICv3, both the *Interrupt Group
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002577Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register*
2578(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured
2579as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt.
2580
2581Crash Reporting mechanism (in BL31)
2582-----------------------------------
2583
2584BL31 implements a crash reporting mechanism which prints the various registers
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002585of the CPU to enable quick crash analysis and debugging. This mechanism relies
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002586on the platform implementing ``plat_crash_console_init``,
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002587``plat_crash_console_putc`` and ``plat_crash_console_flush``.
2588
2589The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample
2590implementation of all of them. Platforms may include this file to their
2591makefiles in order to benefit from them. By default, they will cause the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07002592output to be routed over the normal console infrastructure and get printed on
2593consoles configured to output in crash state. ``console_set_scope()`` can be
2594used to control whether a console is used for crash output.
Paul Beesleyba3ed402019-03-13 16:20:44 +00002595
2596.. note::
2597 Platforms are responsible for making sure that they only mark consoles for
2598 use in the crash scope that are able to support this, i.e. that are written
2599 in assembly and conform with the register clobber rules for putc()
2600 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002601
Julius Werneraae9bb12017-09-18 16:49:48 -07002602In some cases (such as debugging very early crashes that happen before the
2603normal boot console can be set up), platforms may want to control crash output
Julius Werner1338c9c2018-11-19 14:25:55 -08002604more explicitly. These platforms may instead provide custom implementations for
2605these. They are executed outside of a C environment and without a stack. Many
2606console drivers provide functions named ``console_xxx_core_init/putc/flush``
2607that are designed to be used by these functions. See Arm platforms (like juno)
2608for an example of this.
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002609
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002610Function : plat_crash_console_init [mandatory]
2611~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002612
2613::
2614
2615 Argument : void
2616 Return : int
2617
2618This API is used by the crash reporting mechanism to initialize the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07002619console. It must only use the general purpose registers x0 through x7 to do the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002620initialization and returns 1 on success.
2621
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002622Function : plat_crash_console_putc [mandatory]
2623~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002624
2625::
2626
2627 Argument : int
2628 Return : int
2629
2630This API is used by the crash reporting mechanism to print a character on the
2631designated crash console. It must only use general purpose registers x1 and
2632x2 to do its work. The parameter and the return value are in general purpose
2633register x0.
2634
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002635Function : plat_crash_console_flush [mandatory]
2636~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002637
2638::
2639
2640 Argument : void
2641 Return : int
2642
2643This API is used by the crash reporting mechanism to force write of all buffered
2644data on the designated crash console. It should only use general purpose
Julius Werneraae9bb12017-09-18 16:49:48 -07002645registers x0 through x5 to do its work. The return value is 0 on successful
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002646completion; otherwise the return value is -1.
2647
Jeenu Viswambharane34bf582018-10-12 08:48:36 +01002648External Abort handling and RAS Support
2649---------------------------------------
Jeenu Viswambharanbf235bc2018-07-12 10:00:01 +01002650
2651Function : plat_ea_handler
2652~~~~~~~~~~~~~~~~~~~~~~~~~~
2653
2654::
2655
2656 Argument : int
2657 Argument : uint64_t
2658 Argument : void *
2659 Argument : void *
2660 Argument : uint64_t
2661 Return : void
2662
2663This function is invoked by the RAS framework for the platform to handle an
2664External Abort received at EL3. The intention of the function is to attempt to
2665resolve the cause of External Abort and return; if that's not possible, to
2666initiate orderly shutdown of the system.
2667
2668The first parameter (``int ea_reason``) indicates the reason for External Abort.
2669Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``.
2670
2671The second parameter (``uint64_t syndrome``) is the respective syndrome
2672presented to EL3 after having received the External Abort. Depending on the
2673nature of the abort (as can be inferred from the ``ea_reason`` parameter), this
2674can be the content of either ``ESR_EL3`` or ``DISR_EL1``.
2675
2676The third parameter (``void *cookie``) is unused for now. The fourth parameter
2677(``void *handle``) is a pointer to the preempted context. The fifth parameter
2678(``uint64_t flags``) indicates the preempted security state. These parameters
2679are received from the top-level exception handler.
2680
2681If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this
2682function iterates through RAS handlers registered by the platform. If any of the
2683RAS handlers resolve the External Abort, no further action is taken.
2684
2685If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers
2686could resolve the External Abort, the default implementation prints an error
2687message, and panics.
2688
2689Function : plat_handle_uncontainable_ea
2690~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2691
2692::
2693
2694 Argument : int
2695 Argument : uint64_t
2696 Return : void
2697
2698This function is invoked by the RAS framework when an External Abort of
2699Uncontainable type is received at EL3. Due to the critical nature of
2700Uncontainable errors, the intention of this function is to initiate orderly
2701shutdown of the system, and is not expected to return.
2702
2703This function must be implemented in assembly.
2704
2705The first and second parameters are the same as that of ``plat_ea_handler``.
2706
2707The default implementation of this function calls
2708``report_unhandled_exception``.
2709
2710Function : plat_handle_double_fault
2711~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2712
2713::
2714
2715 Argument : int
2716 Argument : uint64_t
2717 Return : void
2718
2719This function is invoked by the RAS framework when another External Abort is
2720received at EL3 while one is already being handled. I.e., a call to
2721``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of
2722this function is to initiate orderly shutdown of the system, and is not expected
2723recover or return.
2724
2725This function must be implemented in assembly.
2726
2727The first and second parameters are the same as that of ``plat_ea_handler``.
2728
2729The default implementation of this function calls
2730``report_unhandled_exception``.
2731
2732Function : plat_handle_el3_ea
2733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2734
2735::
2736
2737 Return : void
2738
2739This function is invoked when an External Abort is received while executing in
2740EL3. Due to its critical nature, the intention of this function is to initiate
2741orderly shutdown of the system, and is not expected recover or return.
2742
2743This function must be implemented in assembly.
2744
2745The default implementation of this function calls
2746``report_unhandled_exception``.
2747
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002748Build flags
2749-----------
2750
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002751There are some build flags which can be defined by the platform to control
2752inclusion or exclusion of certain BL stages from the FIP image. These flags
2753need to be defined in the platform makefile which will get included by the
2754build system.
2755
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002756- **NEED_BL33**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002757 By default, this flag is defined ``yes`` by the build system and ``BL33``
2758 build option should be supplied as a build option. The platform has the
2759 option of excluding the BL33 image in the ``fip`` image by defining this flag
2760 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
2761 are used, this flag will be set to ``no`` automatically.
2762
2763C Library
2764---------
2765
2766To avoid subtle toolchain behavioral dependencies, the header files provided
2767by the compiler are not used. The software is built with the ``-nostdinc`` flag
2768to ensure no headers are included from the toolchain inadvertently. Instead the
Dan Handley610e7e12018-03-01 18:44:00 +00002769required headers are included in the TF-A source tree. The library only
2770contains those C library definitions required by the local implementation. If
2771more functionality is required, the needed library functions will need to be
2772added to the local implementation.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002773
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01002774Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have
2775been written specifically for TF-A. Fome implementation files have been obtained
2776from `FreeBSD`_, others have been written specifically for TF-A as well. The
2777files can be found in ``include/lib/libc`` and ``lib/libc``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002778
Sandrine Bailleux6f0ecd72019-02-08 14:46:42 +01002779SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources
2780can be obtained from http://github.com/freebsd/freebsd.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002781
2782Storage abstraction layer
2783-------------------------
2784
Louis Mayencourtb5469002019-07-15 13:56:03 +01002785In order to improve platform independence and portability a storage abstraction
2786layer is used to load data from non-volatile platform storage. Currently
2787storage access is only required by BL1 and BL2 phases and performed inside the
2788``load_image()`` function in ``bl_common.c``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002789
Louis Mayencourtb5469002019-07-15 13:56:03 +01002790.. uml:: ../resources/diagrams/plantuml/io_framework_usage_overview.puml
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002791
Dan Handley610e7e12018-03-01 18:44:00 +00002792It is mandatory to implement at least one storage driver. For the Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002793development platforms the Firmware Image Package (FIP) driver is provided as
2794the default means to load data from storage (see the "Firmware Image Package"
2795section in the `User Guide`_). The storage layer is described in the header file
2796``include/drivers/io/io_storage.h``. The implementation of the common library
2797is in ``drivers/io/io_storage.c`` and the driver files are located in
2798``drivers/io/``.
2799
Louis Mayencourtb5469002019-07-15 13:56:03 +01002800.. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml
2801
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002802Each IO driver must provide ``io_dev_*`` structures, as described in
2803``drivers/io/io_driver.h``. These are returned via a mandatory registration
2804function that is called on platform initialization. The semi-hosting driver
2805implementation in ``io_semihosting.c`` can be used as an example.
2806
Louis Mayencourtb5469002019-07-15 13:56:03 +01002807Each platform should register devices and their drivers via the storage
2808abstraction layer. These drivers then need to be initialized by bootloader
2809phases as required in their respective ``blx_platform_setup()`` functions.
2810
2811.. uml:: ../resources/diagrams/plantuml/io_dev_registration.puml
2812
2813The storage abstraction layer provides mechanisms (``io_dev_init()``) to
2814initialize storage devices before IO operations are called.
2815
2816.. uml:: ../resources/diagrams/plantuml/io_dev_init_and_check.puml
2817
2818The basic operations supported by the layer
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002819include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``.
2820Drivers do not have to implement all operations, but each platform must
2821provide at least one driver for a device capable of supporting generic
2822operations such as loading a bootloader image.
2823
2824The current implementation only allows for known images to be loaded by the
2825firmware. These images are specified by using their identifiers, as defined in
Antonio Nino Diaz645feb42019-02-13 14:07:38 +00002826``include/plat/common/common_def.h`` (or a separate header file included from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002827there). The platform layer (``plat_get_image_source()``) then returns a reference
2828to a device and a driver-specific ``spec`` which will be understood by the driver
2829to allow access to the image data.
2830
2831The layer is designed in such a way that is it possible to chain drivers with
2832other drivers. For example, file-system drivers may be implemented on top of
2833physical block devices, both represented by IO devices with corresponding
2834drivers. In such a case, the file-system "binding" with the block device may
2835be deferred until the file-system device is initialised.
2836
2837The abstraction currently depends on structures being statically allocated
2838by the drivers and callers, as the system does not yet provide a means of
2839dynamically allocating memory. This may also have the affect of limiting the
2840amount of open resources per driver.
2841
2842--------------
2843
Antonio Nino Diaz645feb42019-02-13 14:07:38 +00002844*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002845
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002846.. _include/plat/common/platform.h: ../include/plat/common/platform.h
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002847.. _include/plat/arm/common/plat_arm.h: ../include/plat/arm/common/plat_arm.h%5D
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002848.. _User Guide: user-guide.rst
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002849.. _include/plat/common/common_def.h: ../include/plat/common/common_def.h
2850.. _include/plat/arm/common/arm_def.h: ../include/plat/arm/common/arm_def.h
2851.. _plat/common/aarch64/platform_mp_stack.S: ../plat/common/aarch64/platform_mp_stack.S
2852.. _plat/common/aarch64/platform_up_stack.S: ../plat/common/aarch64/platform_up_stack.S
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002853.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160
John Tsichritzis2fd3d922019-05-28 13:13:39 +01002854.. _Power Domain Topology Design: ../design/psci-pd-tree.rst
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002855.. _include/common/bl_common.h: ../include/common/bl_common.h
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002856.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h
John Tsichritzis2fd3d922019-05-28 13:13:39 +01002857.. _Firmware Design: ../design/firmware-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002858.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002859.. _plat/arm/board/fvp/fvp_pm.c: ../plat/arm/board/fvp/fvp_pm.c
John Tsichritzis2fd3d922019-05-28 13:13:39 +01002860.. _Platform compatibility policy: ../process/platform-compatibility-policy.rst
2861.. _IMF Design Guide: ../design/interrupt-framework-design.rst
Dan Handley610e7e12018-03-01 18:44:00 +00002862.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002863.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
Paul Beesley2437ddc2019-02-08 16:43:05 +00002864.. _FreeBSD: https://www.freebsd.org
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01002865.. _SCC: http://www.simple-cc.org/