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Dan Handley9df48042015-03-19 18:58:55 +00001/*
AlexeiFedorov334d2352022-12-29 15:57:40 +00002 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Yatharth Kocharf9a0f162016-09-13 17:07:57 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
9
10#include <platform_def.h>
11
Zelalem Aweke5085abd2021-07-13 17:19:54 -050012#include <arch_features.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <arch_helpers.h>
14#include <common/bl_common.h>
15#include <common/debug.h>
16#include <common/desc_image_load.h>
17#include <drivers/generic_delay_timer.h>
Manish V Badarkhedd6f2522021-02-22 17:30:17 +000018#include <drivers/partition/partition.h>
Louis Mayencourt81bd9162019-10-17 15:14:25 +010019#include <lib/fconf/fconf.h>
Manish V Badarkhe99a8e142020-06-11 22:32:11 +010020#include <lib/fconf/fconf_dyn_cfg_getter.h>
johpow019d134022021-06-16 17:57:28 -050021#include <lib/gpt_rme/gpt_rme.h>
Summer Qin9db8f2e2017-04-24 16:49:28 +010022#ifdef SPD_opteed
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000023#include <lib/optee_utils.h>
Summer Qin9db8f2e2017-04-24 16:49:28 +010024#endif
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000025#include <lib/utils.h>
AlexeiFedorov334d2352022-12-29 15:57:40 +000026#if ENABLE_RME
Zelalem Aweke5085abd2021-07-13 17:19:54 -050027#include <plat/arm/common/arm_pas_def.h>
AlexeiFedorov334d2352022-12-29 15:57:40 +000028#endif
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000029#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000030#include <plat/common/platform.h>
31
Dan Handley9df48042015-03-19 18:58:55 +000032/* Data structure which holds the extents of the trusted SRAM for BL2 */
33static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
34
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +010035/* Base address of fw_config received from BL1 */
Jimmy Brissond7297c72020-08-05 14:05:53 -050036static uintptr_t config_base;
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +010037
Soby Mathewc44110d2018-02-20 12:50:47 +000038/*
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010039 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is
Soby Mathewaf14b462018-06-01 16:53:38 +010040 * for `meminfo_t` data structure and fw_configs passed from BL1.
Soby Mathewc44110d2018-02-20 12:50:47 +000041 */
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010042CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
Soby Mathewc44110d2018-02-20 12:50:47 +000043
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010044/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7d5a2e72018-01-10 15:59:31 +000045#pragma weak bl2_early_platform_setup2
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010046#pragma weak bl2_platform_setup
47#pragma weak bl2_plat_arch_setup
48#pragma weak bl2_plat_sec_mem_layout
49
Zelalem Aweke65e92632021-07-12 22:33:55 -050050#if ENABLE_RME
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010051#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
52 bl2_tzram_layout.total_base, \
53 bl2_tzram_layout.total_size, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050054 MT_MEMORY | MT_RW | MT_ROOT)
55#else
56#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
57 bl2_tzram_layout.total_base, \
58 bl2_tzram_layout.total_size, \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010059 MT_MEMORY | MT_RW | MT_SECURE)
Zelalem Aweke65e92632021-07-12 22:33:55 -050060#endif /* ENABLE_RME */
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010061
Daniel Boulby07d26872018-06-27 16:45:48 +010062#pragma weak arm_bl2_plat_handle_post_image_load
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010063
Dan Handley9df48042015-03-19 18:58:55 +000064/*******************************************************************************
65 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
66 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
67 * Copy it to a safe location before its reclaimed by later BL2 functionality.
68 ******************************************************************************/
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010069void arm_bl2_early_platform_setup(uintptr_t fw_config,
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020070 struct meminfo *mem_layout)
Dan Handley9df48042015-03-19 18:58:55 +000071{
Govindraj Raja70154422023-10-24 14:50:23 -050072 int __maybe_unused ret;
73
Dan Handley9df48042015-03-19 18:58:55 +000074 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010075 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +000076
77 /* Setup the BL2 memory layout */
78 bl2_tzram_layout = *mem_layout;
79
Jimmy Brissond7297c72020-08-05 14:05:53 -050080 config_base = fw_config;
Louis Mayencourt81bd9162019-10-17 15:14:25 +010081
Dan Handley9df48042015-03-19 18:58:55 +000082 /* Initialise the IO layer and register platform IO devices */
83 plat_arm_io_setup();
Manish V Badarkhedd6f2522021-02-22 17:30:17 +000084
85 /* Load partition table */
86#if ARM_GPT_SUPPORT
Govindraj Raja70154422023-10-24 14:50:23 -050087 ret = gpt_partition_init();
88 if (ret != 0) {
89 ERROR("GPT partition initialisation failed!\n");
90 panic();
91 }
Manish V Badarkhedd6f2522021-02-22 17:30:17 +000092
Govindraj Raja70154422023-10-24 14:50:23 -050093#endif /* ARM_GPT_SUPPORT */
Dan Handley9df48042015-03-19 18:58:55 +000094}
95
Soby Mathew7d5a2e72018-01-10 15:59:31 +000096void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
Dan Handley9df48042015-03-19 18:58:55 +000097{
Soby Mathew96a1c6b2018-01-15 14:45:33 +000098 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
99
Soby Mathew1ced6b82017-06-12 12:37:10 +0100100 generic_delay_timer_init();
Dan Handley9df48042015-03-19 18:58:55 +0000101}
102
103/*
Soby Mathew45e39e22018-03-26 15:16:46 +0100104 * Perform BL2 preload setup. Currently we initialise the dynamic
105 * configuration here.
Dan Handley9df48042015-03-19 18:58:55 +0000106 */
Soby Mathew45e39e22018-03-26 15:16:46 +0100107void bl2_plat_preload_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000108{
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000109 arm_bl2_dyn_cfg_init();
Manish V Badarkhedd6f2522021-02-22 17:30:17 +0000110
Manish V Badarkhed2f0a7a2021-06-25 23:43:33 +0100111#if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT
112 /* Always use the FIP from bank 0 */
113 arm_set_fip_addr(0U);
114#endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */
Soby Mathew45e39e22018-03-26 15:16:46 +0100115}
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000116
Soby Mathew45e39e22018-03-26 15:16:46 +0100117/*
118 * Perform ARM standard platform setup.
119 */
120void arm_bl2_platform_setup(void)
121{
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500122#if !ENABLE_RME
Dan Handley9df48042015-03-19 18:58:55 +0000123 /* Initialize the secure environment */
124 plat_arm_security_setup();
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500125#endif
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100126
127#if defined(PLAT_ARM_MEM_PROT_ADDR)
Roberto Vargas550eb082018-01-05 16:00:05 +0000128 arm_nor_psci_do_static_mem_protect();
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100129#endif
Dan Handley9df48042015-03-19 18:58:55 +0000130}
131
132void bl2_platform_setup(void)
133{
134 arm_bl2_platform_setup();
135}
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500136
137#if ENABLE_RME
138static void arm_bl2_plat_gpt_setup(void)
139{
140 /*
141 * The GPT library might modify the gpt regions structure to optimize
142 * the layout, so the array cannot be constant.
143 */
144 pas_region_t pas_regions[] = {
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500145 ARM_PAS_KERNEL,
johpow019d134022021-06-16 17:57:28 -0500146 ARM_PAS_SECURE,
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500147 ARM_PAS_REALM,
148 ARM_PAS_EL3_DRAM,
AlexeiFedorovaa442492022-11-29 13:32:41 +0000149 ARM_PAS_GPTS,
150 ARM_PAS_KERNEL_1
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500151 };
152
johpow019d134022021-06-16 17:57:28 -0500153 /* Initialize entire protected space to GPT_GPI_ANY. */
AlexeiFedorovaa442492022-11-29 13:32:41 +0000154 if (gpt_init_l0_tables(GPCCR_PPS_64GB, ARM_L0_GPT_ADDR_BASE,
johpow019d134022021-06-16 17:57:28 -0500155 ARM_L0_GPT_SIZE) < 0) {
156 ERROR("gpt_init_l0_tables() failed!\n");
157 panic();
158 }
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500159
johpow019d134022021-06-16 17:57:28 -0500160 /* Carve out defined PAS ranges. */
161 if (gpt_init_pas_l1_tables(GPCCR_PGS_4K,
162 ARM_L1_GPT_ADDR_BASE,
163 ARM_L1_GPT_SIZE,
164 pas_regions,
165 (unsigned int)(sizeof(pas_regions) /
166 sizeof(pas_region_t))) < 0) {
167 ERROR("gpt_init_pas_l1_tables() failed!\n");
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500168 panic();
169 }
170
johpow019d134022021-06-16 17:57:28 -0500171 INFO("Enabling Granule Protection Checks\n");
172 if (gpt_enable() < 0) {
173 ERROR("gpt_enable() failed!\n");
174 panic();
175 }
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500176}
177#endif /* ENABLE_RME */
Dan Handley9df48042015-03-19 18:58:55 +0000178
179/*******************************************************************************
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500180 * Perform the very early platform specific architectural setup here.
181 * When RME is enabled the secure environment is initialised before
182 * initialising and enabling Granule Protection.
183 * This function initialises the MMU in a quick and dirty way.
Dan Handley9df48042015-03-19 18:58:55 +0000184 ******************************************************************************/
185void arm_bl2_plat_arch_setup(void)
186{
Soby Mathewb9856482018-09-18 11:42:42 +0100187#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
188 /*
189 * Ensure ARM platforms don't use coherent memory in BL2 unless
190 * cryptocell integration is enabled.
191 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100192 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
Dan Handley9df48042015-03-19 18:58:55 +0000193#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100194
195 const mmap_region_t bl_regions[] = {
196 MAP_BL2_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100197 ARM_MAP_BL_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100198#if USE_ROMLIB
199 ARM_MAP_ROMLIB_CODE,
200 ARM_MAP_ROMLIB_DATA,
201#endif
Soby Mathewb9856482018-09-18 11:42:42 +0100202#if ARM_CRYPTOCELL_INTEG
203 ARM_MAP_BL_COHERENT_RAM,
204#endif
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100205 ARM_MAP_BL_CONFIG_REGION,
Zelalem Awekec43c5632021-07-12 23:41:05 -0500206#if ENABLE_RME
207 ARM_MAP_L0_GPT_REGION,
208#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100209 {0}
210 };
211
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500212#if ENABLE_RME
213 /* Initialise the secure environment */
214 plat_arm_security_setup();
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500215#endif
Roberto Vargas344ff022018-10-19 16:44:18 +0100216 setup_page_tables(bl_regions, plat_arm_get_mmap());
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100217
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700218#ifdef __aarch64__
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500219#if ENABLE_RME
220 /* BL2 runs in EL3 when RME enabled. */
221 assert(get_armv9_2_feat_rme_support() != 0U);
222 enable_mmu_el3(0);
johpow019d134022021-06-16 17:57:28 -0500223
224 /* Initialise and enable granule protection after MMU. */
225 arm_bl2_plat_gpt_setup();
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500226#else
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100227 enable_mmu_el1(0);
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500228#endif
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700229#else
230 enable_mmu_svc_mon(0);
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100231#endif
Roberto Vargase3adc372018-05-23 09:27:06 +0100232
233 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000234}
235
236void bl2_plat_arch_setup(void)
237{
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100238 const struct dyn_cfg_dtb_info_t *tb_fw_config_info;
239
Dan Handley9df48042015-03-19 18:58:55 +0000240 arm_bl2_plat_arch_setup();
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100241
242 /* Fill the properties struct with the info from the config dtb */
Jimmy Brissond7297c72020-08-05 14:05:53 -0500243 fconf_populate("FW_CONFIG", config_base);
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100244
245 /* TB_FW_CONFIG was also loaded by BL1 */
246 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID);
247 assert(tb_fw_config_info != NULL);
248
249 fconf_populate("TB_FW", tb_fw_config_info->config_addr);
Dan Handley9df48042015-03-19 18:58:55 +0000250}
251
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000252int arm_bl2_handle_post_image_load(unsigned int image_id)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100253{
254 int err = 0;
255 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Summer Qin9db8f2e2017-04-24 16:49:28 +0100256#ifdef SPD_opteed
257 bl_mem_params_node_t *pager_mem_params = NULL;
258 bl_mem_params_node_t *paged_mem_params = NULL;
259#endif
Zelaleme8dadb12020-02-05 14:12:39 -0600260 assert(bl_mem_params != NULL);
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100261
262 switch (image_id) {
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700263#ifdef __aarch64__
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100264 case BL32_IMAGE_ID:
Summer Qin9db8f2e2017-04-24 16:49:28 +0100265#ifdef SPD_opteed
266 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
267 assert(pager_mem_params);
268
269 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
270 assert(paged_mem_params);
271
272 err = parse_optee_header(&bl_mem_params->ep_info,
273 &pager_mem_params->image_info,
274 &paged_mem_params->image_info);
275 if (err != 0) {
276 WARN("OPTEE header parse error.\n");
277 }
278#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100279 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
280 break;
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100281#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100282
283 case BL33_IMAGE_ID:
284 /* BL33 expects to receive the primary CPU MPID (through r0) */
285 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
286 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
287 break;
288
289#ifdef SCP_BL2_BASE
290 case SCP_BL2_IMAGE_ID:
291 /* The subsequent handling of SCP_BL2 is platform specific */
292 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
293 if (err) {
294 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
295 }
296 break;
297#endif
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000298 default:
299 /* Do nothing in default case */
300 break;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100301 }
302
303 return err;
304}
305
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000306/*******************************************************************************
307 * This function can be used by the platforms to update/use image
308 * information for given `image_id`.
309 ******************************************************************************/
Daniel Boulby07d26872018-06-27 16:45:48 +0100310int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000311{
Balint Dobszay719ba9c2021-03-26 16:23:18 +0100312#if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD
Manish Pandey1fa6ecb2020-02-25 11:38:19 +0000313 /* For Secure Partitions we don't need post processing */
314 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) &&
315 (image_id < MAX_NUMBER_IDS)) {
316 return 0;
317 }
318#endif
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000319 return arm_bl2_handle_post_image_load(image_id);
320}