Rework page table setup for varying number of mem regions
Change arm_setup_page_tables() to take a variable number of memory
regions. Remove coherent memory region from BL1, BL2 and BL2U as
their coherent memory region doesn't contain anything and
therefore has a size of 0. Add check to ensure this
doesn't change without us knowing.
Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 3aa99f8..88bf1e6 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -35,6 +35,11 @@
#pragma weak bl2_plat_arch_setup
#pragma weak bl2_plat_sec_mem_layout
+#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
+ bl2_tzram_layout.total_base, \
+ bl2_tzram_layout.total_size, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
#if LOAD_IMAGE_V2
#pragma weak bl2_plat_handle_post_image_load
@@ -231,17 +236,20 @@
******************************************************************************/
void arm_bl2_plat_arch_setup(void)
{
- arm_setup_page_tables(bl2_tzram_layout.total_base,
- bl2_tzram_layout.total_size,
- BL_CODE_BASE,
- BL_CODE_END,
- BL_RO_DATA_BASE,
- BL_RO_DATA_END
+
#if USE_COHERENT_MEM
- , BL_COHERENT_RAM_BASE,
- BL_COHERENT_RAM_END
+ /* Ensure ARM platforms dont use coherent memory in BL2 */
+ assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
#endif
- );
+
+ const mmap_region_t bl_regions[] = {
+ MAP_BL2_TOTAL,
+ ARM_MAP_BL_CODE,
+ ARM_MAP_BL_RO_DATA,
+ {0}
+ };
+
+ arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
#ifdef AARCH32
enable_mmu_secure(0);