blob: 3aa99f80562aa8affd90105842a8ae2f2fe2deb4 [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew7d5a2e72018-01-10 15:59:31 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <arch_helpers.h>
8#include <arm_def.h>
Yatharth Kocharf9a0f162016-09-13 17:07:57 +01009#include <assert.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <bl_common.h>
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010011#include <debug.h>
12#include <desc_image_load.h>
Soby Mathew1ced6b82017-06-12 12:37:10 +010013#include <generic_delay_timer.h>
Summer Qin9db8f2e2017-04-24 16:49:28 +010014#ifdef SPD_opteed
15#include <optee_utils.h>
16#endif
Dan Handley9df48042015-03-19 18:58:55 +000017#include <plat_arm.h>
dp-arm7f297ca2017-05-02 11:49:33 +010018#include <platform.h>
Isla Mitchelld2548792017-07-14 10:48:25 +010019#include <platform_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000020#include <string.h>
Douglas Raillarda8954fc2017-01-26 15:54:44 +000021#include <utils.h>
Dan Handley9df48042015-03-19 18:58:55 +000022
Dan Handley9df48042015-03-19 18:58:55 +000023/* Data structure which holds the extents of the trusted SRAM for BL2 */
24static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
25
Soby Mathewc44110d2018-02-20 12:50:47 +000026/*
Soby Mathewaf14b462018-06-01 16:53:38 +010027 * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is
28 * for `meminfo_t` data structure and fw_configs passed from BL1.
Soby Mathewc44110d2018-02-20 12:50:47 +000029 */
Soby Mathewaf14b462018-06-01 16:53:38 +010030CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
Soby Mathewc44110d2018-02-20 12:50:47 +000031
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010032/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7d5a2e72018-01-10 15:59:31 +000033#pragma weak bl2_early_platform_setup2
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010034#pragma weak bl2_platform_setup
35#pragma weak bl2_plat_arch_setup
36#pragma weak bl2_plat_sec_mem_layout
37
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010038#if LOAD_IMAGE_V2
39
40#pragma weak bl2_plat_handle_post_image_load
41
42#else /* LOAD_IMAGE_V2 */
43
Dan Handley9df48042015-03-19 18:58:55 +000044/*******************************************************************************
45 * This structure represents the superset of information that is passed to
Juan Castillo7d199412015-12-14 09:35:25 +000046 * BL31, e.g. while passing control to it from BL2, bl31_params
Dan Handley9df48042015-03-19 18:58:55 +000047 * and other platform specific params
48 ******************************************************************************/
49typedef struct bl2_to_bl31_params_mem {
50 bl31_params_t bl31_params;
51 image_info_t bl31_image_info;
52 image_info_t bl32_image_info;
53 image_info_t bl33_image_info;
54 entry_point_info_t bl33_ep_info;
55 entry_point_info_t bl32_ep_info;
56 entry_point_info_t bl31_ep_info;
57} bl2_to_bl31_params_mem_t;
58
59
60static bl2_to_bl31_params_mem_t bl31_params_mem;
61
62
63/* Weak definitions may be overridden in specific ARM standard platform */
Dan Handley9df48042015-03-19 18:58:55 +000064#pragma weak bl2_plat_get_bl31_params
65#pragma weak bl2_plat_get_bl31_ep_info
66#pragma weak bl2_plat_flush_bl31_params
67#pragma weak bl2_plat_set_bl31_ep_info
Juan Castilloa72b6472015-12-10 15:49:17 +000068#pragma weak bl2_plat_get_scp_bl2_meminfo
Dan Handley9df48042015-03-19 18:58:55 +000069#pragma weak bl2_plat_get_bl32_meminfo
70#pragma weak bl2_plat_set_bl32_ep_info
71#pragma weak bl2_plat_get_bl33_meminfo
72#pragma weak bl2_plat_set_bl33_ep_info
73
David Wang0ba499f2016-03-07 11:02:57 +080074#if ARM_BL31_IN_DRAM
75meminfo_t *bl2_plat_sec_mem_layout(void)
76{
77 static meminfo_t bl2_dram_layout
78 __aligned(CACHE_WRITEBACK_GRANULE) = {
79 .total_base = BL31_BASE,
80 .total_size = (ARM_AP_TZC_DRAM1_BASE +
81 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE,
82 .free_base = BL31_BASE,
83 .free_size = (ARM_AP_TZC_DRAM1_BASE +
84 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE
85 };
Dan Handley9df48042015-03-19 18:58:55 +000086
David Wang0ba499f2016-03-07 11:02:57 +080087 return &bl2_dram_layout;
88}
89#else
Dan Handley9df48042015-03-19 18:58:55 +000090meminfo_t *bl2_plat_sec_mem_layout(void)
91{
92 return &bl2_tzram_layout;
93}
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010094#endif /* ARM_BL31_IN_DRAM */
Dan Handley9df48042015-03-19 18:58:55 +000095
96/*******************************************************************************
97 * This function assigns a pointer to the memory that the platform has kept
98 * aside to pass platform specific and trusted firmware related information
99 * to BL31. This memory is allocated by allocating memory to
100 * bl2_to_bl31_params_mem_t structure which is a superset of all the
101 * structure whose information is passed to BL31
102 * NOTE: This function should be called only once and should be done
103 * before generating params to BL31
104 ******************************************************************************/
105bl31_params_t *bl2_plat_get_bl31_params(void)
106{
107 bl31_params_t *bl2_to_bl31_params;
108
109 /*
110 * Initialise the memory for all the arguments that needs to
Juan Castillo7d199412015-12-14 09:35:25 +0000111 * be passed to BL31
Dan Handley9df48042015-03-19 18:58:55 +0000112 */
Douglas Raillarda8954fc2017-01-26 15:54:44 +0000113 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t));
Dan Handley9df48042015-03-19 18:58:55 +0000114
115 /* Assign memory for TF related information */
116 bl2_to_bl31_params = &bl31_params_mem.bl31_params;
117 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
118
Juan Castillo7d199412015-12-14 09:35:25 +0000119 /* Fill BL31 related information */
Dan Handley9df48042015-03-19 18:58:55 +0000120 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
121 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
122 VERSION_1, 0);
123
Juan Castillo7d199412015-12-14 09:35:25 +0000124 /* Fill BL32 related information if it exists */
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100125#ifdef BL32_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000126 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
127 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
128 VERSION_1, 0);
129 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
130 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
131 VERSION_1, 0);
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100132#endif /* BL32_BASE */
Dan Handley9df48042015-03-19 18:58:55 +0000133
Juan Castillo7d199412015-12-14 09:35:25 +0000134 /* Fill BL33 related information */
Dan Handley9df48042015-03-19 18:58:55 +0000135 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
136 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
137 PARAM_EP, VERSION_1, 0);
138
Juan Castillo7d199412015-12-14 09:35:25 +0000139 /* BL33 expects to receive the primary CPU MPID (through x0) */
Dan Handley9df48042015-03-19 18:58:55 +0000140 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
141
142 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
143 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
144 VERSION_1, 0);
145
146 return bl2_to_bl31_params;
147}
148
149/* Flush the TF params and the TF plat params */
150void bl2_plat_flush_bl31_params(void)
151{
152 flush_dcache_range((unsigned long)&bl31_params_mem,
153 sizeof(bl2_to_bl31_params_mem_t));
154}
155
156/*******************************************************************************
157 * This function returns a pointer to the shared memory that the platform
158 * has kept to point to entry point information of BL31 to BL2
159 ******************************************************************************/
160struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
161{
162#if DEBUG
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000163 bl31_params_mem.bl31_ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL;
Dan Handley9df48042015-03-19 18:58:55 +0000164#endif
165
166 return &bl31_params_mem.bl31_ep_info;
167}
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100168#endif /* LOAD_IMAGE_V2 */
Dan Handley9df48042015-03-19 18:58:55 +0000169
170/*******************************************************************************
171 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
172 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
173 * Copy it to a safe location before its reclaimed by later BL2 functionality.
174 ******************************************************************************/
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000175void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, meminfo_t *mem_layout)
Dan Handley9df48042015-03-19 18:58:55 +0000176{
177 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100178 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +0000179
180 /* Setup the BL2 memory layout */
181 bl2_tzram_layout = *mem_layout;
182
183 /* Initialise the IO layer and register platform IO devices */
184 plat_arm_io_setup();
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000185
186#if LOAD_IMAGE_V2
Soby Mathewcc364842018-02-21 01:16:39 +0000187 if (tb_fw_config != 0U)
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000188 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config);
189#endif
Dan Handley9df48042015-03-19 18:58:55 +0000190}
191
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000192void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
Dan Handley9df48042015-03-19 18:58:55 +0000193{
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000194 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
195
Soby Mathew1ced6b82017-06-12 12:37:10 +0100196 generic_delay_timer_init();
Dan Handley9df48042015-03-19 18:58:55 +0000197}
198
199/*
Soby Mathew45e39e22018-03-26 15:16:46 +0100200 * Perform BL2 preload setup. Currently we initialise the dynamic
201 * configuration here.
Dan Handley9df48042015-03-19 18:58:55 +0000202 */
Soby Mathew45e39e22018-03-26 15:16:46 +0100203void bl2_plat_preload_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000204{
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000205#if LOAD_IMAGE_V2
206 arm_bl2_dyn_cfg_init();
207#endif
Soby Mathew45e39e22018-03-26 15:16:46 +0100208}
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000209
Soby Mathew45e39e22018-03-26 15:16:46 +0100210/*
211 * Perform ARM standard platform setup.
212 */
213void arm_bl2_platform_setup(void)
214{
Dan Handley9df48042015-03-19 18:58:55 +0000215 /* Initialize the secure environment */
216 plat_arm_security_setup();
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100217
218#if defined(PLAT_ARM_MEM_PROT_ADDR)
Roberto Vargas550eb082018-01-05 16:00:05 +0000219 arm_nor_psci_do_static_mem_protect();
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100220#endif
Dan Handley9df48042015-03-19 18:58:55 +0000221}
222
223void bl2_platform_setup(void)
224{
225 arm_bl2_platform_setup();
226}
227
228/*******************************************************************************
229 * Perform the very early platform specific architectural setup here. At the
230 * moment this is only initializes the mmu in a quick and dirty way.
231 ******************************************************************************/
232void arm_bl2_plat_arch_setup(void)
233{
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100234 arm_setup_page_tables(bl2_tzram_layout.total_base,
Dan Handley9df48042015-03-19 18:58:55 +0000235 bl2_tzram_layout.total_size,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100236 BL_CODE_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900237 BL_CODE_END,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100238 BL_RO_DATA_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900239 BL_RO_DATA_END
Dan Handley9df48042015-03-19 18:58:55 +0000240#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900241 , BL_COHERENT_RAM_BASE,
242 BL_COHERENT_RAM_END
Dan Handley9df48042015-03-19 18:58:55 +0000243#endif
244 );
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100245
246#ifdef AARCH32
247 enable_mmu_secure(0);
248#else
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100249 enable_mmu_el1(0);
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100250#endif
Dan Handley9df48042015-03-19 18:58:55 +0000251}
252
253void bl2_plat_arch_setup(void)
254{
255 arm_bl2_plat_arch_setup();
256}
257
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100258#if LOAD_IMAGE_V2
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000259int arm_bl2_handle_post_image_load(unsigned int image_id)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100260{
261 int err = 0;
262 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Summer Qin9db8f2e2017-04-24 16:49:28 +0100263#ifdef SPD_opteed
264 bl_mem_params_node_t *pager_mem_params = NULL;
265 bl_mem_params_node_t *paged_mem_params = NULL;
266#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100267 assert(bl_mem_params);
268
269 switch (image_id) {
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100270#ifdef AARCH64
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100271 case BL32_IMAGE_ID:
Summer Qin9db8f2e2017-04-24 16:49:28 +0100272#ifdef SPD_opteed
273 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
274 assert(pager_mem_params);
275
276 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
277 assert(paged_mem_params);
278
279 err = parse_optee_header(&bl_mem_params->ep_info,
280 &pager_mem_params->image_info,
281 &paged_mem_params->image_info);
282 if (err != 0) {
283 WARN("OPTEE header parse error.\n");
284 }
285#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100286 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
287 break;
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100288#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100289
290 case BL33_IMAGE_ID:
291 /* BL33 expects to receive the primary CPU MPID (through r0) */
292 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
293 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
294 break;
295
296#ifdef SCP_BL2_BASE
297 case SCP_BL2_IMAGE_ID:
298 /* The subsequent handling of SCP_BL2 is platform specific */
299 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
300 if (err) {
301 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
302 }
303 break;
304#endif
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000305 default:
306 /* Do nothing in default case */
307 break;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100308 }
309
310 return err;
311}
312
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000313/*******************************************************************************
314 * This function can be used by the platforms to update/use image
315 * information for given `image_id`.
316 ******************************************************************************/
317int bl2_plat_handle_post_image_load(unsigned int image_id)
318{
319 return arm_bl2_handle_post_image_load(image_id);
320}
321
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100322#else /* LOAD_IMAGE_V2 */
323
Dan Handley9df48042015-03-19 18:58:55 +0000324/*******************************************************************************
Juan Castilloa72b6472015-12-10 15:49:17 +0000325 * Populate the extents of memory available for loading SCP_BL2 (if used),
Dan Handley9df48042015-03-19 18:58:55 +0000326 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2.
327 ******************************************************************************/
Juan Castilloa72b6472015-12-10 15:49:17 +0000328void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
Dan Handley9df48042015-03-19 18:58:55 +0000329{
Juan Castilloa72b6472015-12-10 15:49:17 +0000330 *scp_bl2_meminfo = bl2_tzram_layout;
Dan Handley9df48042015-03-19 18:58:55 +0000331}
332
333/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000334 * Before calling this function BL31 is loaded in memory and its entrypoint
Dan Handley9df48042015-03-19 18:58:55 +0000335 * is set by load_image. This is a placeholder for the platform to change
Juan Castillo7d199412015-12-14 09:35:25 +0000336 * the entrypoint of BL31 and set SPSR and security state.
Dan Handley9df48042015-03-19 18:58:55 +0000337 * On ARM standard platforms we only set the security state of the entrypoint
338 ******************************************************************************/
339void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
340 entry_point_info_t *bl31_ep_info)
341{
342 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
343 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
344 DISABLE_ALL_EXCEPTIONS);
345}
346
347
348/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000349 * Before calling this function BL32 is loaded in memory and its entrypoint
Dan Handley9df48042015-03-19 18:58:55 +0000350 * is set by load_image. This is a placeholder for the platform to change
Juan Castillo7d199412015-12-14 09:35:25 +0000351 * the entrypoint of BL32 and set SPSR and security state.
Dan Handley9df48042015-03-19 18:58:55 +0000352 * On ARM standard platforms we only set the security state of the entrypoint
353 ******************************************************************************/
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100354#ifdef BL32_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000355void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
356 entry_point_info_t *bl32_ep_info)
357{
358 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
359 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry();
360}
361
362/*******************************************************************************
Dan Handley9df48042015-03-19 18:58:55 +0000363 * Populate the extents of memory available for loading BL32
364 ******************************************************************************/
365void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
366{
367 /*
368 * Populate the extents of memory available for loading BL32.
369 */
370 bl32_meminfo->total_base = BL32_BASE;
371 bl32_meminfo->free_base = BL32_BASE;
372 bl32_meminfo->total_size =
373 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
374 bl32_meminfo->free_size =
375 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
376}
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100377#endif /* BL32_BASE */
Dan Handley9df48042015-03-19 18:58:55 +0000378
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100379/*******************************************************************************
380 * Before calling this function BL33 is loaded in memory and its entrypoint
381 * is set by load_image. This is a placeholder for the platform to change
382 * the entrypoint of BL33 and set SPSR and security state.
383 * On ARM standard platforms we only set the security state of the entrypoint
384 ******************************************************************************/
385void bl2_plat_set_bl33_ep_info(image_info_t *image,
386 entry_point_info_t *bl33_ep_info)
387{
388 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
389 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry();
390}
Dan Handley9df48042015-03-19 18:58:55 +0000391
392/*******************************************************************************
393 * Populate the extents of memory available for loading BL33
394 ******************************************************************************/
395void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
396{
397 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE;
398 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE;
399 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE;
400 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE;
401}
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100402
403#endif /* LOAD_IMAGE_V2 */