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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
7#ifndef __ARCH_H__
8#define __ARCH_H__
9
Scott Brandenbf404c02017-04-10 11:45:52 -070010#include <utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010011
12/*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070015#define MIDR_IMPL_MASK U(0xff)
16#define MIDR_IMPL_SHIFT U(0x18)
17#define MIDR_VAR_SHIFT U(20)
18#define MIDR_VAR_BITS U(4)
19#define MIDR_VAR_MASK U(0xf)
20#define MIDR_REV_SHIFT U(0)
21#define MIDR_REV_BITS U(4)
22#define MIDR_REV_MASK U(0xf)
23#define MIDR_PN_MASK U(0xfff)
24#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010025
26/*******************************************************************************
27 * MPIDR macros
28 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070029#define MPIDR_MT_MASK (U(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010030#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekarc6a11f62017-05-25 18:04:48 -070031#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
32#define MPIDR_AFFINITY_BITS U(8)
33#define MPIDR_AFFLVL_MASK U(0xff)
34#define MPIDR_AFF0_SHIFT U(0)
35#define MPIDR_AFF1_SHIFT U(8)
36#define MPIDR_AFF2_SHIFT U(16)
37#define MPIDR_AFF3_SHIFT U(32)
38#define MPIDR_AFFINITY_MASK U(0xff00ffffff)
39#define MPIDR_AFFLVL_SHIFT U(3)
40#define MPIDR_AFFLVL0 U(0)
41#define MPIDR_AFFLVL1 U(1)
42#define MPIDR_AFFLVL2 U(2)
43#define MPIDR_AFFLVL3 U(3)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000044#define MPIDR_AFFLVL0_VAL(mpidr) \
45 ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
46#define MPIDR_AFFLVL1_VAL(mpidr) \
47 ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
48#define MPIDR_AFFLVL2_VAL(mpidr) \
49 ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
50#define MPIDR_AFFLVL3_VAL(mpidr) \
51 ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000052/*
53 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
54 * add one while using this macro to define array sizes.
55 * TODO: Support only the first 3 affinity levels for now.
56 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070057#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010058
59/* Constant to highlight the assumption that MPIDR allocation starts from 0 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070060#define FIRST_MPIDR U(0)
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
62/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010063 * Definitions for CPU system register interface to GICv3
64 ******************************************************************************/
65#define ICC_SRE_EL1 S3_0_C12_C12_5
66#define ICC_SRE_EL2 S3_4_C12_C9_5
67#define ICC_SRE_EL3 S3_6_C12_C12_5
68#define ICC_CTLR_EL1 S3_0_C12_C12_4
69#define ICC_CTLR_EL3 S3_6_C12_C12_4
70#define ICC_PMR_EL1 S3_0_C4_C6_0
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +010071#define ICC_RPR_EL1 S3_0_C12_C11_3
Achin Gupta92712a52015-09-03 14:18:02 +010072#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
73#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
74#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
75#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
76#define ICC_IAR0_EL1 S3_0_c12_c8_0
77#define ICC_IAR1_EL1 S3_0_c12_c12_0
78#define ICC_EOIR0_EL1 S3_0_c12_c8_1
79#define ICC_EOIR1_EL1 S3_0_c12_c12_1
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010080#define ICC_SGI0R_EL1 S3_0_c12_c11_7
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010081
82/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +000083 * Generic timer memory mapped registers & offsets
84 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070085#define CNTCR_OFF U(0x000)
86#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +000087
Varun Wadekarc6a11f62017-05-25 18:04:48 -070088#define CNTCR_EN (U(1) << 0)
89#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +010090#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +000091
92/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010093 * System register bit definitions
94 ******************************************************************************/
95/* CLIDR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070096#define LOUIS_SHIFT U(21)
97#define LOC_SHIFT U(24)
98#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +010099
100/* CSSELR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700101#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100102
103/* D$ set/way op type defines */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700104#define DCISW U(0x0)
105#define DCCISW U(0x1)
106#define DCCSW U(0x2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100107
108/* ID_AA64PFR0_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700109#define ID_AA64PFR0_EL0_SHIFT U(0)
110#define ID_AA64PFR0_EL1_SHIFT U(4)
111#define ID_AA64PFR0_EL2_SHIFT U(8)
112#define ID_AA64PFR0_EL3_SHIFT U(12)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100113#define ID_AA64PFR0_AMU_SHIFT U(44)
114#define ID_AA64PFR0_AMU_LENGTH U(4)
115#define ID_AA64PFR0_AMU_MASK U(0xf)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700116#define ID_AA64PFR0_ELX_MASK U(0xf)
David Cunadoce88eee2017-10-20 11:30:57 +0100117#define ID_AA64PFR0_SVE_SHIFT U(32)
118#define ID_AA64PFR0_SVE_MASK U(0xf)
119#define ID_AA64PFR0_SVE_LENGTH U(4)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000120#define ID_AA64PFR0_CSV2_SHIFT U(56)
121#define ID_AA64PFR0_CSV2_MASK U(0xf)
122#define ID_AA64PFR0_CSV2_LENGTH U(4)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100123
dp-armee3457b2017-05-23 09:32:49 +0100124/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
125#define ID_AA64DFR0_PMS_SHIFT U(32)
126#define ID_AA64DFR0_PMS_LENGTH U(4)
127#define ID_AA64DFR0_PMS_MASK U(0xf)
128
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700129#define EL_IMPL_NONE U(0)
130#define EL_IMPL_A64ONLY U(1)
131#define EL_IMPL_A64_A32 U(2)
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000132
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700133#define ID_AA64PFR0_GIC_SHIFT U(24)
134#define ID_AA64PFR0_GIC_WIDTH U(4)
135#define ID_AA64PFR0_GIC_MASK ((U(1) << ID_AA64PFR0_GIC_WIDTH) - 1)
Achin Gupta92712a52015-09-03 14:18:02 +0100136
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000137/* ID_AA64MMFR0_EL1 definitions */
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100138#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700139#define ID_AA64MMFR0_EL1_PARANGE_MASK U(0xf)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000140
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700141#define PARANGE_0000 U(32)
142#define PARANGE_0001 U(36)
143#define PARANGE_0010 U(40)
144#define PARANGE_0011 U(42)
145#define PARANGE_0100 U(44)
146#define PARANGE_0101 U(48)
Antonio Nino Diazb9ef6642017-11-17 09:52:53 +0000147#define PARANGE_0110 U(52)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000148
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100149#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
150#define ID_AA64MMFR0_EL1_TGRAN4_MASK U(0xf)
151#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED U(0x0)
152#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED U(0xf)
153
154#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
155#define ID_AA64MMFR0_EL1_TGRAN64_MASK U(0xf)
156#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED U(0x0)
157#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED U(0xf)
158
159#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
160#define ID_AA64MMFR0_EL1_TGRAN16_MASK U(0xf)
161#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED U(0x1)
162#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED U(0x0)
163
Achin Gupta4f6ad662013-10-25 09:08:21 +0100164/* ID_PFR1_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700165#define ID_PFR1_VIRTEXT_SHIFT U(12)
166#define ID_PFR1_VIRTEXT_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100167#define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \
168 & ID_PFR1_VIRTEXT_MASK)
169
170/* SCTLR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100171#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700172 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
173 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100174
David Cunadofee86532017-04-13 22:38:29 +0100175#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700176 (U(1) << 22) | (U(1) << 20) | (U(1) << 11))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200177#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700178 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
179 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200180
David Cunadofee86532017-04-13 22:38:29 +0100181#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
182 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
183 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
184
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700185#define SCTLR_M_BIT (U(1) << 0)
186#define SCTLR_A_BIT (U(1) << 1)
187#define SCTLR_C_BIT (U(1) << 2)
188#define SCTLR_SA_BIT (U(1) << 3)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100189#define SCTLR_SA0_BIT (U(1) << 4)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700190#define SCTLR_CP15BEN_BIT (U(1) << 5)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100191#define SCTLR_ITD_BIT (U(1) << 7)
192#define SCTLR_SED_BIT (U(1) << 8)
193#define SCTLR_UMA_BIT (U(1) << 9)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700194#define SCTLR_I_BIT (U(1) << 12)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100195#define SCTLR_V_BIT (U(1) << 13)
196#define SCTLR_DZE_BIT (U(1) << 14)
197#define SCTLR_UCT_BIT (U(1) << 15)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700198#define SCTLR_NTWI_BIT (U(1) << 16)
199#define SCTLR_NTWE_BIT (U(1) << 18)
200#define SCTLR_WXN_BIT (U(1) << 19)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100201#define SCTLR_UWXN_BIT (U(1) << 20)
202#define SCTLR_E0E_BIT (U(1) << 24)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700203#define SCTLR_EE_BIT (U(1) << 25)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100204#define SCTLR_UCI_BIT (U(1) << 26)
205#define SCTLR_TRE_BIT (U(1) << 28)
206#define SCTLR_AFE_BIT (U(1) << 29)
207#define SCTLR_TE_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100208#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100209
Achin Gupta4f6ad662013-10-25 09:08:21 +0100210/* CPACR_El1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700211#define CPACR_EL1_FPEN(x) ((x) << 20)
212#define CPACR_EL1_FP_TRAP_EL0 U(0x1)
213#define CPACR_EL1_FP_TRAP_ALL U(0x2)
214#define CPACR_EL1_FP_TRAP_NONE U(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100215
216/* SCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700217#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000218#define SCR_FIEN_BIT (U(1) << 21)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700219#define SCR_TWE_BIT (U(1) << 13)
220#define SCR_TWI_BIT (U(1) << 12)
221#define SCR_ST_BIT (U(1) << 11)
222#define SCR_RW_BIT (U(1) << 10)
223#define SCR_SIF_BIT (U(1) << 9)
224#define SCR_HCE_BIT (U(1) << 8)
225#define SCR_SMD_BIT (U(1) << 7)
226#define SCR_EA_BIT (U(1) << 3)
227#define SCR_FIQ_BIT (U(1) << 2)
228#define SCR_IRQ_BIT (U(1) << 1)
229#define SCR_NS_BIT (U(1) << 0)
230#define SCR_VALID_BIT_MASK U(0x2f8f)
David Cunadofee86532017-04-13 22:38:29 +0100231#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100232
David Cunadofee86532017-04-13 22:38:29 +0100233/* MDCR_EL3 definitions */
dp-arm595d0d52017-02-08 11:51:50 +0000234#define MDCR_SPD32(x) ((x) << 14)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700235#define MDCR_SPD32_LEGACY U(0x0)
236#define MDCR_SPD32_DISABLE U(0x2)
237#define MDCR_SPD32_ENABLE U(0x3)
238#define MDCR_SDD_BIT (U(1) << 16)
dp-armee3457b2017-05-23 09:32:49 +0100239#define MDCR_NSPB(x) ((x) << 12)
240#define MDCR_NSPB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100241#define MDCR_TDOSA_BIT (U(1) << 10)
242#define MDCR_TDA_BIT (U(1) << 9)
243#define MDCR_TPM_BIT (U(1) << 6)
244#define MDCR_EL3_RESET_VAL U(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000245
David Cunadofee86532017-04-13 22:38:29 +0100246#if !ERROR_DEPRECATED
dp-arm595d0d52017-02-08 11:51:50 +0000247#define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE))
David Cunadofee86532017-04-13 22:38:29 +0100248#endif
249
250/* MDCR_EL2 definitions */
dp-armee3457b2017-05-23 09:32:49 +0100251#define MDCR_EL2_TPMS (U(1) << 14)
252#define MDCR_EL2_E2PB(x) ((x) << 12)
253#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100254#define MDCR_EL2_TDRA_BIT (U(1) << 11)
255#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
256#define MDCR_EL2_TDA_BIT (U(1) << 9)
257#define MDCR_EL2_TDE_BIT (U(1) << 8)
258#define MDCR_EL2_HPME_BIT (U(1) << 7)
259#define MDCR_EL2_TPM_BIT (U(1) << 6)
260#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
261#define MDCR_EL2_RESET_VAL U(0x0)
262
263/* HSTR_EL2 definitions */
264#define HSTR_EL2_RESET_VAL U(0x0)
265#define HSTR_EL2_T_MASK U(0xff)
266
267/* CNTHP_CTL_EL2 definitions */
268#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
269#define CNTHP_CTL_RESET_VAL U(0x0)
270
271/* VTTBR_EL2 definitions */
272#define VTTBR_RESET_VAL ULL(0x0)
273#define VTTBR_VMID_MASK ULL(0xff)
274#define VTTBR_VMID_SHIFT U(48)
275#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
276#define VTTBR_BADDR_SHIFT U(0)
dp-arm595d0d52017-02-08 11:51:50 +0000277
Achin Gupta4f6ad662013-10-25 09:08:21 +0100278/* HCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700279#define HCR_RW_SHIFT U(31)
280#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
281#define HCR_AMO_BIT (U(1) << 5)
282#define HCR_IMO_BIT (U(1) << 4)
283#define HCR_FMO_BIT (U(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100284
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100285/* ISR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700286#define ISR_A_SHIFT U(8)
287#define ISR_I_SHIFT U(7)
288#define ISR_F_SHIFT U(6)
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100289
Achin Gupta4f6ad662013-10-25 09:08:21 +0100290/* CNTHCTL_EL2 definitions */
David Cunadofee86532017-04-13 22:38:29 +0100291#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700292#define EVNTEN_BIT (U(1) << 2)
293#define EL1PCEN_BIT (U(1) << 1)
294#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100295
296/* CNTKCTL_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700297#define EL0PTEN_BIT (U(1) << 9)
298#define EL0VTEN_BIT (U(1) << 8)
299#define EL0PCTEN_BIT (U(1) << 0)
300#define EL0VCTEN_BIT (U(1) << 1)
301#define EVNTEN_BIT (U(1) << 2)
302#define EVNTDIR_BIT (U(1) << 3)
303#define EVNTI_SHIFT U(4)
304#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100305
306/* CPTR_EL3 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700307#define TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100308#define TAM_BIT (U(1) << 30)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700309#define TTA_BIT (U(1) << 20)
310#define TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100311#define CPTR_EZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100312#define CPTR_EL3_RESET_VAL U(0x0)
313
314/* CPTR_EL2 definitions */
315#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
316#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100317#define CPTR_EL2_TAM_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100318#define CPTR_EL2_TTA_BIT (U(1) << 20)
319#define CPTR_EL2_TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100320#define CPTR_EL2_TZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100321#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100322
323/* CPSR/SPSR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700324#define DAIF_FIQ_BIT (U(1) << 0)
325#define DAIF_IRQ_BIT (U(1) << 1)
326#define DAIF_ABT_BIT (U(1) << 2)
327#define DAIF_DBG_BIT (U(1) << 3)
328#define SPSR_DAIF_SHIFT U(6)
329#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100330
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700331#define SPSR_AIF_SHIFT U(6)
332#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100333
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700334#define SPSR_E_SHIFT U(9)
335#define SPSR_E_MASK U(0x1)
336#define SPSR_E_LITTLE U(0x0)
337#define SPSR_E_BIG U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100338
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700339#define SPSR_T_SHIFT U(5)
340#define SPSR_T_MASK U(0x1)
341#define SPSR_T_ARM U(0x0)
342#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100343
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000344#define SPSR_M_SHIFT U(4)
345#define SPSR_M_MASK U(0x1)
346#define SPSR_M_AARCH64 U(0x0)
347#define SPSR_M_AARCH32 U(0x1)
348
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100349#define DISABLE_ALL_EXCEPTIONS \
350 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
351
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000352/*
353 * RMR_EL3 definitions
354 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700355#define RMR_EL3_RR_BIT (U(1) << 1)
356#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000357
358/*
359 * HI-VECTOR address for AArch32 state
360 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700361#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100362
363/*
364 * TCR defintions
365 */
Antonio Nino Diazf94e40d2017-09-14 15:57:44 +0100366#define TCR_EL3_RES1 ((U(1) << 31) | (U(1) << 23))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700367#define TCR_EL1_IPS_SHIFT U(32)
368#define TCR_EL3_PS_SHIFT U(16)
Lin Ma741a3822014-06-27 16:56:30 -0700369
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700370#define TCR_TxSZ_MIN U(16)
371#define TCR_TxSZ_MAX U(39)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100372
Lin Ma741a3822014-06-27 16:56:30 -0700373/* (internal) physical address size bits in EL3/EL1 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700374#define TCR_PS_BITS_4GB U(0x0)
375#define TCR_PS_BITS_64GB U(0x1)
376#define TCR_PS_BITS_1TB U(0x2)
377#define TCR_PS_BITS_4TB U(0x3)
378#define TCR_PS_BITS_16TB U(0x4)
379#define TCR_PS_BITS_256TB U(0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100380
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700381#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
382#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
383#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
384#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
385#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
386#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100387
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700388#define TCR_RGN_INNER_NC (U(0x0) << 8)
389#define TCR_RGN_INNER_WBA (U(0x1) << 8)
390#define TCR_RGN_INNER_WT (U(0x2) << 8)
391#define TCR_RGN_INNER_WBNA (U(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100392
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700393#define TCR_RGN_OUTER_NC (U(0x0) << 10)
394#define TCR_RGN_OUTER_WBA (U(0x1) << 10)
395#define TCR_RGN_OUTER_WT (U(0x2) << 10)
396#define TCR_RGN_OUTER_WBNA (U(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100397
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700398#define TCR_SH_NON_SHAREABLE (U(0x0) << 12)
399#define TCR_SH_OUTER_SHAREABLE (U(0x2) << 12)
400#define TCR_SH_INNER_SHAREABLE (U(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100401
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100402#define TCR_TG0_SHIFT U(14)
403#define TCR_TG0_MASK U(3)
404#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
405#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
406#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
407
408#define TCR_EPD0_BIT (U(1) << 7)
Antonio Nino Diazc8274a82017-09-15 10:30:34 +0100409#define TCR_EPD1_BIT (U(1) << 23)
410
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700411#define MODE_SP_SHIFT U(0x0)
412#define MODE_SP_MASK U(0x1)
413#define MODE_SP_EL0 U(0x0)
414#define MODE_SP_ELX U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100415
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700416#define MODE_RW_SHIFT U(0x4)
417#define MODE_RW_MASK U(0x1)
418#define MODE_RW_64 U(0x0)
419#define MODE_RW_32 U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100420
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700421#define MODE_EL_SHIFT U(0x2)
422#define MODE_EL_MASK U(0x3)
423#define MODE_EL3 U(0x3)
424#define MODE_EL2 U(0x2)
425#define MODE_EL1 U(0x1)
426#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100427
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700428#define MODE32_SHIFT U(0)
429#define MODE32_MASK U(0xf)
430#define MODE32_usr U(0x0)
431#define MODE32_fiq U(0x1)
432#define MODE32_irq U(0x2)
433#define MODE32_svc U(0x3)
434#define MODE32_mon U(0x6)
435#define MODE32_abt U(0x7)
436#define MODE32_hyp U(0xa)
437#define MODE32_und U(0xb)
438#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100439
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100440#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
441#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
442#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
443#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100444
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100445#define SPSR_64(el, sp, daif) \
Antonio Nino Diaze8811472018-04-17 15:10:18 +0100446 ((MODE_RW_64 << MODE_RW_SHIFT) | \
447 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
448 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
449 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT))
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100450
451#define SPSR_MODE32(mode, isa, endian, aif) \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700452 ((MODE_RW_32 << MODE_RW_SHIFT) | \
453 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
454 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
455 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
456 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100457
Dan Handley0cdebbd2015-03-30 17:15:16 +0100458/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100459 * TTBR Definitions
460 */
461#define TTBR_CNP_BIT 0x1
462
463/*
Dan Handley0cdebbd2015-03-30 17:15:16 +0100464 * CTR_EL0 definitions
465 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700466#define CTR_CWG_SHIFT U(24)
467#define CTR_CWG_MASK U(0xf)
468#define CTR_ERG_SHIFT U(20)
469#define CTR_ERG_MASK U(0xf)
470#define CTR_DMINLINE_SHIFT U(16)
471#define CTR_DMINLINE_MASK U(0xf)
472#define CTR_L1IP_SHIFT U(14)
473#define CTR_L1IP_MASK U(0x3)
474#define CTR_IMINLINE_SHIFT U(0)
475#define CTR_IMINLINE_MASK U(0xf)
Dan Handley0cdebbd2015-03-30 17:15:16 +0100476
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700477#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100478
Achin Gupta405406d2014-05-09 12:00:17 +0100479/* Physical timer control register bit fields shifts and masks */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700480#define CNTP_CTL_ENABLE_SHIFT U(0)
481#define CNTP_CTL_IMASK_SHIFT U(1)
482#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Gupta405406d2014-05-09 12:00:17 +0100483
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700484#define CNTP_CTL_ENABLE_MASK U(1)
485#define CNTP_CTL_IMASK_MASK U(1)
486#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Gupta405406d2014-05-09 12:00:17 +0100487
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700488#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
Achin Gupta405406d2014-05-09 12:00:17 +0100489 CNTP_CTL_ENABLE_MASK)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700490#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
Achin Gupta405406d2014-05-09 12:00:17 +0100491 CNTP_CTL_IMASK_MASK)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700492#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
Achin Gupta405406d2014-05-09 12:00:17 +0100493 CNTP_CTL_ISTATUS_MASK)
494
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700495#define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
496#define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
Achin Gupta405406d2014-05-09 12:00:17 +0100497
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700498#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
499#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
Achin Gupta405406d2014-05-09 12:00:17 +0100500
Achin Gupta4f6ad662013-10-25 09:08:21 +0100501/* Exception Syndrome register bits and bobs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700502#define ESR_EC_SHIFT U(26)
503#define ESR_EC_MASK U(0x3f)
504#define ESR_EC_LENGTH U(6)
505#define EC_UNKNOWN U(0x0)
506#define EC_WFE_WFI U(0x1)
507#define EC_AARCH32_CP15_MRC_MCR U(0x3)
508#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
509#define EC_AARCH32_CP14_MRC_MCR U(0x5)
510#define EC_AARCH32_CP14_LDC_STC U(0x6)
511#define EC_FP_SIMD U(0x7)
512#define EC_AARCH32_CP10_MRC U(0x8)
513#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
514#define EC_ILLEGAL U(0xe)
515#define EC_AARCH32_SVC U(0x11)
516#define EC_AARCH32_HVC U(0x12)
517#define EC_AARCH32_SMC U(0x13)
518#define EC_AARCH64_SVC U(0x15)
519#define EC_AARCH64_HVC U(0x16)
520#define EC_AARCH64_SMC U(0x17)
521#define EC_AARCH64_SYS U(0x18)
522#define EC_IABORT_LOWER_EL U(0x20)
523#define EC_IABORT_CUR_EL U(0x21)
524#define EC_PC_ALIGN U(0x22)
525#define EC_DABORT_LOWER_EL U(0x24)
526#define EC_DABORT_CUR_EL U(0x25)
527#define EC_SP_ALIGN U(0x26)
528#define EC_AARCH32_FP U(0x28)
529#define EC_AARCH64_FP U(0x2c)
530#define EC_SERROR U(0x2f)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100531
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000532/*
533 * External Abort bit in Instruction and Data Aborts synchronous exception
534 * syndromes.
535 */
536#define ESR_ISS_EABORT_EA_BIT U(9)
537
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700538#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100539
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800540/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700541#define RMR_RESET_REQUEST_SHIFT U(0x1)
542#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800543
Dan Handleyed6ff952014-05-14 17:44:19 +0100544/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000545 * Definitions of register offsets, fields and macros for CPU system
546 * instructions.
547 ******************************************************************************/
548
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700549#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000550#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
551#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
552
553/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +0100554 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
555 * system level implementation of the Generic Timer.
556 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700557#define CNTNSAR U(0x4)
558#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handleyed6ff952014-05-14 17:44:19 +0100559
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700560#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
561#define CNTACR_RPCT_SHIFT U(0x0)
562#define CNTACR_RVCT_SHIFT U(0x1)
563#define CNTACR_RFRQ_SHIFT U(0x2)
564#define CNTACR_RVOFF_SHIFT U(0x3)
565#define CNTACR_RWVT_SHIFT U(0x4)
566#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handleyed6ff952014-05-14 17:44:19 +0100567
David Cunado5f55e282016-10-31 17:37:34 +0000568/* PMCR_EL0 definitions */
David Cunado4168f2f2017-10-02 17:41:39 +0100569#define PMCR_EL0_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700570#define PMCR_EL0_N_SHIFT U(11)
571#define PMCR_EL0_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000572#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
David Cunado4168f2f2017-10-02 17:41:39 +0100573#define PMCR_EL0_LC_BIT (U(1) << 6)
574#define PMCR_EL0_DP_BIT (U(1) << 5)
575#define PMCR_EL0_X_BIT (U(1) << 4)
576#define PMCR_EL0_D_BIT (U(1) << 3)
David Cunado5f55e282016-10-31 17:37:34 +0000577
Isla Mitchell02c63072017-07-21 14:44:36 +0100578/*******************************************************************************
David Cunadoce88eee2017-10-20 11:30:57 +0100579 * Definitions for system register interface to SVE
580 ******************************************************************************/
581#define ZCR_EL3 S3_6_C1_C2_0
582#define ZCR_EL2 S3_4_C1_C2_0
583
584/* ZCR_EL3 definitions */
585#define ZCR_EL3_LEN_MASK U(0xf)
586
587/* ZCR_EL2 definitions */
588#define ZCR_EL2_LEN_MASK U(0xf)
589
590/*******************************************************************************
Isla Mitchell02c63072017-07-21 14:44:36 +0100591 * Definitions of MAIR encodings for device and normal memory
592 ******************************************************************************/
593/*
594 * MAIR encodings for device memory attributes.
595 */
596#define MAIR_DEV_nGnRnE ULL(0x0)
597#define MAIR_DEV_nGnRE ULL(0x4)
598#define MAIR_DEV_nGRE ULL(0x8)
599#define MAIR_DEV_GRE ULL(0xc)
600
601/*
602 * MAIR encodings for normal memory attributes.
603 *
604 * Cache Policy
605 * WT: Write Through
606 * WB: Write Back
607 * NC: Non-Cacheable
608 *
609 * Transient Hint
610 * NTR: Non-Transient
611 * TR: Transient
612 *
613 * Allocation Policy
614 * RA: Read Allocate
615 * WA: Write Allocate
616 * RWA: Read and Write Allocate
617 * NA: No Allocation
618 */
619#define MAIR_NORM_WT_TR_WA ULL(0x1)
620#define MAIR_NORM_WT_TR_RA ULL(0x2)
621#define MAIR_NORM_WT_TR_RWA ULL(0x3)
622#define MAIR_NORM_NC ULL(0x4)
623#define MAIR_NORM_WB_TR_WA ULL(0x5)
624#define MAIR_NORM_WB_TR_RA ULL(0x6)
625#define MAIR_NORM_WB_TR_RWA ULL(0x7)
626#define MAIR_NORM_WT_NTR_NA ULL(0x8)
627#define MAIR_NORM_WT_NTR_WA ULL(0x9)
628#define MAIR_NORM_WT_NTR_RA ULL(0xa)
629#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
630#define MAIR_NORM_WB_NTR_NA ULL(0xc)
631#define MAIR_NORM_WB_NTR_WA ULL(0xd)
632#define MAIR_NORM_WB_NTR_RA ULL(0xe)
633#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
634
635#define MAIR_NORM_OUTER_SHIFT 4
636
637#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
638
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100639/* PAR_EL1 fields */
640#define PAR_F_SHIFT 0
641#define PAR_F_MASK 1
642#define PAR_ADDR_SHIFT 12
643#define PAR_ADDR_MASK (BIT(40) - 1) /* 40-bits-wide page address */
644
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100645/*******************************************************************************
646 * Definitions for system register interface to SPE
647 ******************************************************************************/
648#define PMBLIMITR_EL1 S3_0_C9_C10_0
649
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100650/*******************************************************************************
651 * Definitions for system register interface to AMU for ARMv8.4 onwards
652 ******************************************************************************/
653#define AMCR_EL0 S3_3_C13_C2_0
654#define AMCFGR_EL0 S3_3_C13_C2_1
655#define AMCGCR_EL0 S3_3_C13_C2_2
656#define AMUSERENR_EL0 S3_3_C13_C2_3
657#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
658#define AMCNTENSET0_EL0 S3_3_C13_C2_5
659#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
660#define AMCNTENSET1_EL0 S3_3_C13_C3_1
661
662/* Activity Monitor Group 0 Event Counter Registers */
663#define AMEVCNTR00_EL0 S3_3_C13_C4_0
664#define AMEVCNTR01_EL0 S3_3_C13_C4_1
665#define AMEVCNTR02_EL0 S3_3_C13_C4_2
666#define AMEVCNTR03_EL0 S3_3_C13_C4_3
667
668/* Activity Monitor Group 0 Event Type Registers */
669#define AMEVTYPER00_EL0 S3_3_C13_C6_0
670#define AMEVTYPER01_EL0 S3_3_C13_C6_1
671#define AMEVTYPER02_EL0 S3_3_C13_C6_2
672#define AMEVTYPER03_EL0 S3_3_C13_C6_3
673
Dimitris Papastamos525c37a2017-11-13 09:49:45 +0000674/* Activity Monitor Group 1 Event Counter Registers */
675#define AMEVCNTR10_EL0 S3_3_C13_C12_0
676#define AMEVCNTR11_EL0 S3_3_C13_C12_1
677#define AMEVCNTR12_EL0 S3_3_C13_C12_2
678#define AMEVCNTR13_EL0 S3_3_C13_C12_3
679#define AMEVCNTR14_EL0 S3_3_C13_C12_4
680#define AMEVCNTR15_EL0 S3_3_C13_C12_5
681#define AMEVCNTR16_EL0 S3_3_C13_C12_6
682#define AMEVCNTR17_EL0 S3_3_C13_C12_7
683#define AMEVCNTR18_EL0 S3_3_C13_C13_0
684#define AMEVCNTR19_EL0 S3_3_C13_C13_1
685#define AMEVCNTR1A_EL0 S3_3_C13_C13_2
686#define AMEVCNTR1B_EL0 S3_3_C13_C13_3
687#define AMEVCNTR1C_EL0 S3_3_C13_C13_4
688#define AMEVCNTR1D_EL0 S3_3_C13_C13_5
689#define AMEVCNTR1E_EL0 S3_3_C13_C13_6
690#define AMEVCNTR1F_EL0 S3_3_C13_C13_7
691
692/* Activity Monitor Group 1 Event Type Registers */
693#define AMEVTYPER10_EL0 S3_3_C13_C14_0
694#define AMEVTYPER11_EL0 S3_3_C13_C14_1
695#define AMEVTYPER12_EL0 S3_3_C13_C14_2
696#define AMEVTYPER13_EL0 S3_3_C13_C14_3
697#define AMEVTYPER14_EL0 S3_3_C13_C14_4
698#define AMEVTYPER15_EL0 S3_3_C13_C14_5
699#define AMEVTYPER16_EL0 S3_3_C13_C14_6
700#define AMEVTYPER17_EL0 S3_3_C13_C14_7
701#define AMEVTYPER18_EL0 S3_3_C13_C15_0
702#define AMEVTYPER19_EL0 S3_3_C13_C15_1
703#define AMEVTYPER1A_EL0 S3_3_C13_C15_2
704#define AMEVTYPER1B_EL0 S3_3_C13_C15_3
705#define AMEVTYPER1C_EL0 S3_3_C13_C15_4
706#define AMEVTYPER1D_EL0 S3_3_C13_C15_5
707#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
708#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
709
710/* AMCGCR_EL0 definitions */
711#define AMCGCR_EL0_CG1NC_SHIFT U(8)
712#define AMCGCR_EL0_CG1NC_LENGTH U(8)
713#define AMCGCR_EL0_CG1NC_MASK U(0xff)
714
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100715/*******************************************************************************
716 * RAS system registers
717 *******************************************************************************/
718#define DISR_EL1 S3_0_C12_C1_1
719#define DISR_A_BIT 31
720
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000721#define ERRIDR_EL1 S3_0_C5_C3_0
722#define ERRIDR_MASK 0xffff
723
724#define ERRSELR_EL1 S3_0_C5_C3_1
725
726/* System register access to Standard Error Record registers */
727#define ERXFR_EL1 S3_0_C5_C4_0
728#define ERXCTLR_EL1 S3_0_C5_C4_1
729#define ERXSTATUS_EL1 S3_0_C5_C4_2
730#define ERXADDR_EL1 S3_0_C5_C4_3
731#define ERXMISC0_EL1 S3_0_C5_C4_4
732#define ERXMISC1_EL1 S3_0_C5_C4_5
733
Achin Gupta4f6ad662013-10-25 09:08:21 +0100734#endif /* __ARCH_H__ */