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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Alexei Fedorovd27febf2021-09-01 15:41:14 +01002 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2bd4ef22014-04-09 13:14:54 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Andre Przywaraf3e8cfc2022-11-17 16:42:09 +00009#include <arch_features.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <arch_helpers.h>
11#include <common/debug.h>
12#include <drivers/arm/gicv3.h>
Antonio Nino Diazf13d09a2019-01-23 21:50:09 +000013#include <drivers/arm/fvp/fvp_pwrc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/extensions/spe.h>
15#include <lib/mmio.h>
16#include <lib/psci/psci.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000017#include <plat/arm/common/arm_config.h>
18#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +000019#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020
Dan Handleyed6ff952014-05-14 17:44:19 +010021#include "fvp_private.h"
Ambroise Vincentb237bca2019-02-13 15:58:00 +000022#include "../drivers/arm/gic/v3/gicv3_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010023
Dan Handley2b6b5742015-03-19 19:17:53 +000024
Soby Mathew7799cf72015-04-16 14:49:09 +010025#if ARM_RECOM_STATE_ID_ENC
26/*
27 * The table storing the valid idle power states. Ensure that the
28 * array entries are populated in ascending order of state-id to
29 * enable us to use binary search during power state validation.
30 * The table must be terminated by a NULL entry.
31 */
32const unsigned int arm_pm_idle_states[] = {
33 /* State-id - 0x01 */
34 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET,
35 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
36 /* State-id - 0x02 */
37 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
38 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
39 /* State-id - 0x22 */
40 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
41 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
Soby Mathew9ca28062017-10-11 16:08:58 +010042 /* State-id - 0x222 */
43 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
44 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
Soby Mathew7799cf72015-04-16 14:49:09 +010045 0,
46};
47#endif
48
Achin Gupta4f6ad662013-10-25 09:08:21 +010049/*******************************************************************************
Achin Gupta85876392014-07-31 17:45:51 +010050 * Function which implements the common FVP specific operations to power down a
Achin Gupta85876392014-07-31 17:45:51 +010051 * cluster in response to a CPU_OFF or CPU_SUSPEND request.
52 ******************************************************************************/
Sandrine Bailleuxa64a8542015-03-05 10:54:34 +000053static void fvp_cluster_pwrdwn_common(void)
Achin Gupta85876392014-07-31 17:45:51 +010054{
55 uint64_t mpidr = read_mpidr_el1();
56
dp-armee3457b2017-05-23 09:32:49 +010057 /*
58 * On power down we need to disable statistical profiling extensions
59 * before exiting coherency.
60 */
Andre Przywaraf3e8cfc2022-11-17 16:42:09 +000061 if (is_feat_spe_supported()) {
62 spe_disable();
63 }
dp-armee3457b2017-05-23 09:32:49 +010064
Achin Gupta85876392014-07-31 17:45:51 +010065 /* Disable coherency if this cluster is to be turned off */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000066 fvp_interconnect_disable();
Achin Gupta85876392014-07-31 17:45:51 +010067
Madhukar Pappireddy90d65322019-10-30 14:24:39 -050068#if HW_ASSISTED_COHERENCY
69 uint32_t reg;
70
71 /*
72 * If we have determined this core to be the last man standing and we
73 * intend to power down the cluster proactively, we provide a hint to
74 * the power controller that cluster power is not required when all
75 * cores are powered down.
76 * Note that this is only an advisory to power controller and is supported
77 * by SoCs with DynamIQ Shared Units only.
78 */
79 reg = read_clusterpwrdn();
80
81 /* Clear and set bit 0 : Cluster power not required */
82 reg &= ~DSU_CLUSTER_PWR_MASK;
83 reg |= DSU_CLUSTER_PWR_OFF;
84 write_clusterpwrdn(reg);
85#endif
86
Achin Gupta85876392014-07-31 17:45:51 +010087 /* Program the power controller to turn the cluster off */
88 fvp_pwrc_write_pcoffr(mpidr);
89}
90
Soby Mathew9ca28062017-10-11 16:08:58 +010091/*
92 * Empty implementation of these hooks avoid setting the GICR_WAKER.Sleep bit
93 * on ARM GICv3 implementations on FVP. This is required, because FVP does not
94 * support SYSTEM_SUSPEND and it is `faked` in firmware. Hence, for wake up
95 * from `fake` system suspend the GIC must not be powered off.
96 */
Roberto Vargas1a6eed32018-02-12 12:36:17 +000097void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num)
Soby Mathew9ca28062017-10-11 16:08:58 +010098{}
99
Roberto Vargas1a6eed32018-02-12 12:36:17 +0000100void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num)
Soby Mathew9ca28062017-10-11 16:08:58 +0100101{}
102
Soby Mathew12012dd2015-10-26 14:01:53 +0000103static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state)
104{
105 unsigned long mpidr;
106
107 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
108 ARM_LOCAL_STATE_OFF);
109
110 /* Get the mpidr for this cpu */
111 mpidr = read_mpidr_el1();
112
113 /* Perform the common cluster specific operations */
114 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
115 ARM_LOCAL_STATE_OFF) {
116 /*
117 * This CPU might have woken up whilst the cluster was
118 * attempting to power down. In this case the FVP power
119 * controller will have a pending cluster power off request
120 * which needs to be cleared by writing to the PPONR register.
121 * This prevents the power controller from interpreting a
122 * subsequent entry of this cpu into a simple wfi as a power
123 * down request.
124 */
125 fvp_pwrc_write_pponr(mpidr);
126
127 /* Enable coherency if this cluster was off */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000128 fvp_interconnect_enable();
Soby Mathew12012dd2015-10-26 14:01:53 +0000129 }
Soby Mathew9ca28062017-10-11 16:08:58 +0100130 /* Perform the common system specific operations */
131 if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
132 ARM_LOCAL_STATE_OFF)
133 arm_system_pwr_domain_resume();
Soby Mathew12012dd2015-10-26 14:01:53 +0000134
135 /*
136 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
137 * with a cpu power down unless the bit is set again
138 */
139 fvp_pwrc_clr_wen(mpidr);
140}
141
Achin Gupta85876392014-07-31 17:45:51 +0100142/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100143 * FVP handler called when a CPU is about to enter standby.
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000144 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000145static void fvp_cpu_standby(plat_local_state_t cpu_state)
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000146{
Alexei Fedorovd27febf2021-09-01 15:41:14 +0100147 u_register_t scr = read_scr_el3();
Soby Mathewfec4eb72015-07-01 16:16:20 +0100148
149 assert(cpu_state == ARM_LOCAL_STATE_RET);
150
Andrew Thoelke42e75a72014-04-28 12:28:39 +0100151 /*
Alexei Fedorovd27febf2021-09-01 15:41:14 +0100152 * Enable the Non-secure interrupt to wake the CPU.
153 * In GICv3 affinity routing mode, the Non-secure Group 1 interrupts
154 * use Physical FIQ at EL3 whereas in GICv2, Physical IRQ is used.
155 * Enabling both the bits works for both GICv2 mode and GICv3 affinity
156 * routing mode.
157 */
158 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
159 isb();
160
161 /*
162 * Enter standby state.
163 * dsb is good practice before using wfi to enter low power states.
Andrew Thoelke42e75a72014-04-28 12:28:39 +0100164 */
165 dsb();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000166 wfi();
Alexei Fedorovd27febf2021-09-01 15:41:14 +0100167
168 /*
169 * Restore SCR_EL3 to the original value, synchronisation of SCR_EL3
170 * is done by eret in el3_exit() to save some execution cycles.
171 */
172 write_scr_el3(scr);
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000173}
174
175/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100176 * FVP handler called when a power domain is about to be turned on. The
177 * mpidr determines the CPU to be turned on.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100178 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000179static int fvp_pwr_domain_on(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100180{
181 int rc = PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100182 unsigned int psysr;
183
Achin Gupta4f6ad662013-10-25 09:08:21 +0100184 /*
Sandrine Bailleux7175bde2015-12-08 14:18:24 +0000185 * Ensure that we do not cancel an inflight power off request for the
186 * target cpu. That would leave it in a zombie wfi. Wait for it to power
187 * off and then program the power controller to turn that CPU on.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100188 */
189 do {
190 psysr = fvp_pwrc_read_psysr(mpidr);
Sathees Balya50905c72018-10-05 13:30:59 +0100191 } while ((psysr & PSYSR_AFF_L0) != 0U);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100192
Achin Gupta4f6ad662013-10-25 09:08:21 +0100193 fvp_pwrc_write_pponr(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100194 return rc;
195}
196
197/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100198 * FVP handler called when a power domain is about to be turned off. The
199 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100200 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000201static void fvp_pwr_domain_off(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100202{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100203 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
204 ARM_LOCAL_STATE_OFF);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100205
Achin Gupta85876392014-07-31 17:45:51 +0100206 /*
Soby Mathewfec4eb72015-07-01 16:16:20 +0100207 * If execution reaches this stage then this power domain will be
208 * suspended. Perform at least the cpu specific actions followed
209 * by the cluster specific operations if applicable.
Achin Gupta85876392014-07-31 17:45:51 +0100210 */
Jeenu Viswambharan6ad35482016-12-09 11:14:34 +0000211
212 /* Prevent interrupts from spuriously waking up this cpu */
213 plat_arm_gic_cpuif_disable();
214
215 /* Turn redistributor off */
216 plat_arm_gic_redistif_off();
217
218 /* Program the power controller to power off this cpu. */
219 fvp_pwrc_write_ppoffr(read_mpidr_el1());
Achin Gupta4f6ad662013-10-25 09:08:21 +0100220
Soby Mathewfec4eb72015-07-01 16:16:20 +0100221 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
222 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100223 fvp_cluster_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100224
Achin Gupta4f6ad662013-10-25 09:08:21 +0100225}
226
227/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100228 * FVP handler called when a power domain is about to be suspended. The
229 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100230 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000231static void fvp_pwr_domain_suspend(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100232{
Soby Mathewffb4ab12014-09-26 15:08:52 +0100233 unsigned long mpidr;
234
Soby Mathewfec4eb72015-07-01 16:16:20 +0100235 /*
236 * FVP has retention only at cpu level. Just return
237 * as nothing is to be done for retention.
238 */
239 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
240 ARM_LOCAL_STATE_RET)
Soby Mathew74e52a72014-10-02 16:56:51 +0100241 return;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100242
Soby Mathewfec4eb72015-07-01 16:16:20 +0100243 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
244 ARM_LOCAL_STATE_OFF);
245
Soby Mathewffb4ab12014-09-26 15:08:52 +0100246 /* Get the mpidr for this cpu */
247 mpidr = read_mpidr_el1();
248
Achin Gupta85876392014-07-31 17:45:51 +0100249 /* Program the power controller to enable wakeup interrupts. */
250 fvp_pwrc_set_wen(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100251
Jeenu Viswambharan6ad35482016-12-09 11:14:34 +0000252 /* Prevent interrupts from spuriously waking up this cpu */
253 plat_arm_gic_cpuif_disable();
254
255 /*
256 * The Redistributor is not powered off as it can potentially prevent
257 * wake up events reaching the CPUIF and/or might lead to losing
258 * register context.
259 */
260
Achin Gupta85876392014-07-31 17:45:51 +0100261 /* Perform the common cluster specific operations */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100262 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
263 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100264 fvp_cluster_pwrdwn_common();
Soby Mathew9ca28062017-10-11 16:08:58 +0100265
266 /* Perform the common system specific operations */
267 if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
268 ARM_LOCAL_STATE_OFF)
269 arm_system_pwr_domain_save();
270
271 /* Program the power controller to power off this cpu. */
272 fvp_pwrc_write_ppoffr(read_mpidr_el1());
Achin Gupta4f6ad662013-10-25 09:08:21 +0100273}
274
275/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100276 * FVP handler called when a power domain has just been powered on after
277 * being turned off earlier. The target_state encodes the low power state that
278 * each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100279 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000280static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100281{
Soby Mathew12012dd2015-10-26 14:01:53 +0000282 fvp_power_domain_on_finish_common(target_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100283
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500284}
285
286/*******************************************************************************
287 * FVP handler called when a power domain has just been powered on and the cpu
288 * and its cluster are fully participating in coherent transaction on the
289 * interconnect. Data cache must be enabled for CPU at this point.
290 ******************************************************************************/
291static void fvp_pwr_domain_on_finish_late(const psci_power_state_t *target_state)
292{
293 /* Program GIC per-cpu distributor or re-distributor interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000294 plat_arm_gic_pcpu_init();
295
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500296 /* Enable GIC CPU interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000297 plat_arm_gic_cpuif_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100298}
299
300/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100301 * FVP handler called when a power domain has just been powered on after
302 * having been suspended earlier. The target_state encodes the low power state
303 * that each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100304 * TODO: At the moment we reuse the on finisher and reinitialize the secure
305 * context. Need to implement a separate suspend finisher.
306 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000307static void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100308{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100309 /*
310 * Nothing to be done on waking up from retention from CPU level.
311 */
312 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
313 ARM_LOCAL_STATE_RET)
314 return;
315
Soby Mathew12012dd2015-10-26 14:01:53 +0000316 fvp_power_domain_on_finish_common(target_state);
317
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500318 /* Enable GIC CPU interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000319 plat_arm_gic_cpuif_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100320}
321
Juan Castillo4dc4a472014-08-12 11:17:06 +0100322/*******************************************************************************
323 * FVP handlers to shutdown/reboot the system
324 ******************************************************************************/
325static void __dead2 fvp_system_off(void)
326{
327 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000328 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
329 V2M_CFGCTRL_START |
330 V2M_CFGCTRL_RW |
331 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100332 wfi();
333 ERROR("FVP System Off: operation not handled.\n");
334 panic();
335}
336
337static void __dead2 fvp_system_reset(void)
338{
339 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000340 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
341 V2M_CFGCTRL_START |
342 V2M_CFGCTRL_RW |
343 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100344 wfi();
345 ERROR("FVP System Reset: operation not handled.\n");
346 panic();
347}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100348
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100349static int fvp_node_hw_state(u_register_t target_cpu,
350 unsigned int power_level)
351{
352 unsigned int psysr;
353 int ret;
354
355 /*
356 * The format of 'power_level' is implementation-defined, but 0 must
357 * mean a CPU. We also allow 1 to denote the cluster
358 */
Sathees Balya50905c72018-10-05 13:30:59 +0100359 if ((power_level != ARM_PWR_LVL0) && (power_level != ARM_PWR_LVL1))
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100360 return PSCI_E_INVALID_PARAMS;
361
362 /*
363 * Read the status of the given MPDIR from FVP power controller. The
364 * power controller only gives us on/off status, so map that to expected
365 * return values of the PSCI call
366 */
367 psysr = fvp_pwrc_read_psysr(target_cpu);
368 if (psysr == PSYSR_INVALID)
369 return PSCI_E_INVALID_PARAMS;
370
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000371 if (power_level == ARM_PWR_LVL0) {
Sathees Balya50905c72018-10-05 13:30:59 +0100372 ret = ((psysr & PSYSR_AFF_L0) != 0U) ? HW_ON : HW_OFF;
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000373 } else {
374 /* power_level == ARM_PWR_LVL1 */
Sathees Balya50905c72018-10-05 13:30:59 +0100375 ret = ((psysr & PSYSR_AFF_L1) != 0U) ? HW_ON : HW_OFF;
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100376 }
377
378 return ret;
379}
380
Soby Mathew9ca28062017-10-11 16:08:58 +0100381/*
382 * The FVP doesn't truly support power management at SYSTEM power domain. The
383 * SYSTEM_SUSPEND will be down-graded to the cluster level within the platform
384 * layer. The `fake` SYSTEM_SUSPEND allows us to validate some of the driver
385 * save and restore sequences on FVP.
386 */
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000387#if !ARM_BL31_IN_DRAM
388static void fvp_get_sys_suspend_power_state(psci_power_state_t *req_state)
Soby Mathew9ca28062017-10-11 16:08:58 +0100389{
390 unsigned int i;
391
392 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
393 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF;
394}
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000395#endif
Soby Mathew9ca28062017-10-11 16:08:58 +0100396
Achin Gupta4f6ad662013-10-25 09:08:21 +0100397/*******************************************************************************
Soby Mathew9ca28062017-10-11 16:08:58 +0100398 * Handler to filter PSCI requests.
399 ******************************************************************************/
400/*
401 * The system power domain suspend is only supported only via
402 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain
403 * will be downgraded to the lower level.
404 */
405static int fvp_validate_power_state(unsigned int power_state,
406 psci_power_state_t *req_state)
407{
408 int rc;
409 rc = arm_validate_power_state(power_state, req_state);
410
411 /*
412 * Ensure that the system power domain level is never suspended
413 * via PSCI CPU SUSPEND API. Currently system suspend is only
414 * supported via PSCI SYSTEM SUSPEND API.
415 */
416 req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN;
417 return rc;
418}
419
420/*
421 * Custom `translate_power_state_by_mpidr` handler for FVP. Unlike in the
422 * `fvp_validate_power_state`, we do not downgrade the system power
423 * domain level request in `power_state` as it will be used to query the
424 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level.
425 */
426static int fvp_translate_power_state_by_mpidr(u_register_t mpidr,
427 unsigned int power_state,
428 psci_power_state_t *output_state)
429{
430 return arm_validate_power_state(power_state, output_state);
431}
432
433/*******************************************************************************
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100434 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
435 * platform layer will take care of registering the handlers with PSCI.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100436 ******************************************************************************/
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100437plat_psci_ops_t plat_arm_psci_pm_ops = {
Soby Mathewfec4eb72015-07-01 16:16:20 +0100438 .cpu_standby = fvp_cpu_standby,
439 .pwr_domain_on = fvp_pwr_domain_on,
440 .pwr_domain_off = fvp_pwr_domain_off,
441 .pwr_domain_suspend = fvp_pwr_domain_suspend,
442 .pwr_domain_on_finish = fvp_pwr_domain_on_finish,
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500443 .pwr_domain_on_finish_late = fvp_pwr_domain_on_finish_late,
Soby Mathewfec4eb72015-07-01 16:16:20 +0100444 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish,
Juan Castillo4dc4a472014-08-12 11:17:06 +0100445 .system_off = fvp_system_off,
Soby Mathew74e52a72014-10-02 16:56:51 +0100446 .system_reset = fvp_system_reset,
Soby Mathew9ca28062017-10-11 16:08:58 +0100447 .validate_power_state = fvp_validate_power_state,
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100448 .validate_ns_entrypoint = arm_validate_psci_entrypoint,
Soby Mathew9ca28062017-10-11 16:08:58 +0100449 .translate_power_state_by_mpidr = fvp_translate_power_state_by_mpidr,
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100450 .get_node_hw_state = fvp_node_hw_state,
Antonio Nino Diaz0b6af832017-11-22 12:00:44 +0000451#if !ARM_BL31_IN_DRAM
452 /*
453 * The TrustZone Controller is set up during the warmboot sequence after
454 * resuming the CPU from a SYSTEM_SUSPEND. If BL31 is located in SRAM
455 * this is not a problem but, if it is in TZC-secured DRAM, it tries to
456 * reconfigure the same memory it is running on, causing an exception.
457 */
Soby Mathew9ca28062017-10-11 16:08:58 +0100458 .get_sys_suspend_power_state = fvp_get_sys_suspend_power_state,
Antonio Nino Diaz0b6af832017-11-22 12:00:44 +0000459#endif
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100460 .mem_protect_chk = arm_psci_mem_protect_chk,
461 .read_mem_protect = arm_psci_read_mem_protect,
462 .write_mem_protect = arm_nor_psci_write_mem_protect,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100463};
Chandni Cherukurie4bf6a02018-11-14 13:43:59 +0530464
465const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
466{
467 return ops;
468}