blob: faeb1b7775b586efea0f32a577fb93ba1cb05513 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Roberto Vargasa1c16b62017-08-03 09:16:43 +01002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Achin Gupta4f6ad662013-10-25 09:08:21 +01007#include <arch_helpers.h>
Dan Handley2b6b5742015-03-19 19:17:53 +00008#include <arm_config.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +01009#include <assert.h>
Juan Castillo4dc4a472014-08-12 11:17:06 +010010#include <debug.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000011#include <errno.h>
Soby Mathew9ca28062017-10-11 16:08:58 +010012#include <gicv3.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010013#include <mmio.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000014#include <plat_arm.h>
Isla Mitchelld2548792017-07-14 10:48:25 +010015#include <platform.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010016#include <psci.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000017#include <v2m_def.h>
Dan Handley4d2e49d2014-04-11 11:52:12 +010018#include "drivers/pwrc/fvp_pwrc.h"
Dan Handleyed6ff952014-05-14 17:44:19 +010019#include "fvp_def.h"
20#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010021
Dan Handley2b6b5742015-03-19 19:17:53 +000022
Soby Mathew7799cf72015-04-16 14:49:09 +010023#if ARM_RECOM_STATE_ID_ENC
24/*
25 * The table storing the valid idle power states. Ensure that the
26 * array entries are populated in ascending order of state-id to
27 * enable us to use binary search during power state validation.
28 * The table must be terminated by a NULL entry.
29 */
30const unsigned int arm_pm_idle_states[] = {
31 /* State-id - 0x01 */
32 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET,
33 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
34 /* State-id - 0x02 */
35 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
36 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
37 /* State-id - 0x22 */
38 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
39 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
Soby Mathew9ca28062017-10-11 16:08:58 +010040 /* State-id - 0x222 */
41 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
42 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
Soby Mathew7799cf72015-04-16 14:49:09 +010043 0,
44};
45#endif
46
Achin Gupta4f6ad662013-10-25 09:08:21 +010047/*******************************************************************************
Achin Gupta85876392014-07-31 17:45:51 +010048 * Function which implements the common FVP specific operations to power down a
Achin Gupta85876392014-07-31 17:45:51 +010049 * cluster in response to a CPU_OFF or CPU_SUSPEND request.
50 ******************************************************************************/
Sandrine Bailleuxa64a8542015-03-05 10:54:34 +000051static void fvp_cluster_pwrdwn_common(void)
Achin Gupta85876392014-07-31 17:45:51 +010052{
53 uint64_t mpidr = read_mpidr_el1();
54
dp-armee3457b2017-05-23 09:32:49 +010055#if ENABLE_SPE_FOR_LOWER_ELS
56 /*
57 * On power down we need to disable statistical profiling extensions
58 * before exiting coherency.
59 */
60 arm_disable_spe();
61#endif
62
Achin Gupta85876392014-07-31 17:45:51 +010063 /* Disable coherency if this cluster is to be turned off */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000064 fvp_interconnect_disable();
Achin Gupta85876392014-07-31 17:45:51 +010065
66 /* Program the power controller to turn the cluster off */
67 fvp_pwrc_write_pcoffr(mpidr);
68}
69
Soby Mathew9ca28062017-10-11 16:08:58 +010070/*
71 * Empty implementation of these hooks avoid setting the GICR_WAKER.Sleep bit
72 * on ARM GICv3 implementations on FVP. This is required, because FVP does not
73 * support SYSTEM_SUSPEND and it is `faked` in firmware. Hence, for wake up
74 * from `fake` system suspend the GIC must not be powered off.
75 */
76void arm_gicv3_distif_pre_save(unsigned int proc_num)
77{}
78
79void arm_gicv3_distif_post_restore(unsigned int proc_num)
80{}
81
Soby Mathew12012dd2015-10-26 14:01:53 +000082static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state)
83{
84 unsigned long mpidr;
85
86 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
87 ARM_LOCAL_STATE_OFF);
88
89 /* Get the mpidr for this cpu */
90 mpidr = read_mpidr_el1();
91
92 /* Perform the common cluster specific operations */
93 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
94 ARM_LOCAL_STATE_OFF) {
95 /*
96 * This CPU might have woken up whilst the cluster was
97 * attempting to power down. In this case the FVP power
98 * controller will have a pending cluster power off request
99 * which needs to be cleared by writing to the PPONR register.
100 * This prevents the power controller from interpreting a
101 * subsequent entry of this cpu into a simple wfi as a power
102 * down request.
103 */
104 fvp_pwrc_write_pponr(mpidr);
105
106 /* Enable coherency if this cluster was off */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000107 fvp_interconnect_enable();
Soby Mathew12012dd2015-10-26 14:01:53 +0000108 }
Soby Mathew9ca28062017-10-11 16:08:58 +0100109 /* Perform the common system specific operations */
110 if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
111 ARM_LOCAL_STATE_OFF)
112 arm_system_pwr_domain_resume();
Soby Mathew12012dd2015-10-26 14:01:53 +0000113
114 /*
115 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
116 * with a cpu power down unless the bit is set again
117 */
118 fvp_pwrc_clr_wen(mpidr);
119}
120
121
Achin Gupta85876392014-07-31 17:45:51 +0100122/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100123 * FVP handler called when a CPU is about to enter standby.
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000124 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100125void fvp_cpu_standby(plat_local_state_t cpu_state)
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000126{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100127
128 assert(cpu_state == ARM_LOCAL_STATE_RET);
129
Andrew Thoelke42e75a72014-04-28 12:28:39 +0100130 /*
131 * Enter standby state
132 * dsb is good practice before using wfi to enter low power states
133 */
134 dsb();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000135 wfi();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000136}
137
138/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100139 * FVP handler called when a power domain is about to be turned on. The
140 * mpidr determines the CPU to be turned on.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100141 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100142int fvp_pwr_domain_on(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100143{
144 int rc = PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100145 unsigned int psysr;
146
Achin Gupta4f6ad662013-10-25 09:08:21 +0100147 /*
Sandrine Bailleux7175bde2015-12-08 14:18:24 +0000148 * Ensure that we do not cancel an inflight power off request for the
149 * target cpu. That would leave it in a zombie wfi. Wait for it to power
150 * off and then program the power controller to turn that CPU on.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100151 */
152 do {
153 psysr = fvp_pwrc_read_psysr(mpidr);
154 } while (psysr & PSYSR_AFF_L0);
155
Achin Gupta4f6ad662013-10-25 09:08:21 +0100156 fvp_pwrc_write_pponr(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100157 return rc;
158}
159
160/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100161 * FVP handler called when a power domain is about to be turned off. The
162 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100163 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100164void fvp_pwr_domain_off(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100165{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100166 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
167 ARM_LOCAL_STATE_OFF);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100168
Achin Gupta85876392014-07-31 17:45:51 +0100169 /*
Soby Mathewfec4eb72015-07-01 16:16:20 +0100170 * If execution reaches this stage then this power domain will be
171 * suspended. Perform at least the cpu specific actions followed
172 * by the cluster specific operations if applicable.
Achin Gupta85876392014-07-31 17:45:51 +0100173 */
Jeenu Viswambharan6ad35482016-12-09 11:14:34 +0000174
175 /* Prevent interrupts from spuriously waking up this cpu */
176 plat_arm_gic_cpuif_disable();
177
178 /* Turn redistributor off */
179 plat_arm_gic_redistif_off();
180
181 /* Program the power controller to power off this cpu. */
182 fvp_pwrc_write_ppoffr(read_mpidr_el1());
Achin Gupta4f6ad662013-10-25 09:08:21 +0100183
Soby Mathewfec4eb72015-07-01 16:16:20 +0100184 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
185 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100186 fvp_cluster_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100187
Achin Gupta4f6ad662013-10-25 09:08:21 +0100188}
189
190/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100191 * FVP handler called when a power domain is about to be suspended. The
192 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100193 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100194void fvp_pwr_domain_suspend(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100195{
Soby Mathewffb4ab12014-09-26 15:08:52 +0100196 unsigned long mpidr;
197
Soby Mathewfec4eb72015-07-01 16:16:20 +0100198 /*
199 * FVP has retention only at cpu level. Just return
200 * as nothing is to be done for retention.
201 */
202 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
203 ARM_LOCAL_STATE_RET)
Soby Mathew74e52a72014-10-02 16:56:51 +0100204 return;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100205
Soby Mathewfec4eb72015-07-01 16:16:20 +0100206 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
207 ARM_LOCAL_STATE_OFF);
208
Soby Mathewffb4ab12014-09-26 15:08:52 +0100209 /* Get the mpidr for this cpu */
210 mpidr = read_mpidr_el1();
211
Achin Gupta85876392014-07-31 17:45:51 +0100212 /* Program the power controller to enable wakeup interrupts. */
213 fvp_pwrc_set_wen(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100214
Jeenu Viswambharan6ad35482016-12-09 11:14:34 +0000215 /* Prevent interrupts from spuriously waking up this cpu */
216 plat_arm_gic_cpuif_disable();
217
218 /*
219 * The Redistributor is not powered off as it can potentially prevent
220 * wake up events reaching the CPUIF and/or might lead to losing
221 * register context.
222 */
223
Achin Gupta85876392014-07-31 17:45:51 +0100224 /* Perform the common cluster specific operations */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100225 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
226 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100227 fvp_cluster_pwrdwn_common();
Soby Mathew9ca28062017-10-11 16:08:58 +0100228
229 /* Perform the common system specific operations */
230 if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
231 ARM_LOCAL_STATE_OFF)
232 arm_system_pwr_domain_save();
233
234 /* Program the power controller to power off this cpu. */
235 fvp_pwrc_write_ppoffr(read_mpidr_el1());
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236}
237
238/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100239 * FVP handler called when a power domain has just been powered on after
240 * being turned off earlier. The target_state encodes the low power state that
241 * each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100242 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100243void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100244{
Soby Mathew12012dd2015-10-26 14:01:53 +0000245 fvp_power_domain_on_finish_common(target_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100246
Achin Gupta85876392014-07-31 17:45:51 +0100247 /* Enable the gic cpu interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000248 plat_arm_gic_pcpu_init();
249
250 /* Program the gic per-cpu distributor or re-distributor interface */
251 plat_arm_gic_cpuif_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100252}
253
254/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100255 * FVP handler called when a power domain has just been powered on after
256 * having been suspended earlier. The target_state encodes the low power state
257 * that each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100258 * TODO: At the moment we reuse the on finisher and reinitialize the secure
259 * context. Need to implement a separate suspend finisher.
260 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100261void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100262{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100263 /*
264 * Nothing to be done on waking up from retention from CPU level.
265 */
266 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
267 ARM_LOCAL_STATE_RET)
268 return;
269
Soby Mathew12012dd2015-10-26 14:01:53 +0000270 fvp_power_domain_on_finish_common(target_state);
271
272 /* Enable the gic cpu interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000273 plat_arm_gic_cpuif_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100274}
275
Juan Castillo4dc4a472014-08-12 11:17:06 +0100276/*******************************************************************************
277 * FVP handlers to shutdown/reboot the system
278 ******************************************************************************/
279static void __dead2 fvp_system_off(void)
280{
281 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000282 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
283 V2M_CFGCTRL_START |
284 V2M_CFGCTRL_RW |
285 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100286 wfi();
287 ERROR("FVP System Off: operation not handled.\n");
288 panic();
289}
290
291static void __dead2 fvp_system_reset(void)
292{
293 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000294 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
295 V2M_CFGCTRL_START |
296 V2M_CFGCTRL_RW |
297 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100298 wfi();
299 ERROR("FVP System Reset: operation not handled.\n");
300 panic();
301}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100302
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100303static int fvp_node_hw_state(u_register_t target_cpu,
304 unsigned int power_level)
305{
306 unsigned int psysr;
307 int ret;
308
309 /*
310 * The format of 'power_level' is implementation-defined, but 0 must
311 * mean a CPU. We also allow 1 to denote the cluster
312 */
313 if (power_level != ARM_PWR_LVL0 && power_level != ARM_PWR_LVL1)
314 return PSCI_E_INVALID_PARAMS;
315
316 /*
317 * Read the status of the given MPDIR from FVP power controller. The
318 * power controller only gives us on/off status, so map that to expected
319 * return values of the PSCI call
320 */
321 psysr = fvp_pwrc_read_psysr(target_cpu);
322 if (psysr == PSYSR_INVALID)
323 return PSCI_E_INVALID_PARAMS;
324
325 switch (power_level) {
326 case ARM_PWR_LVL0:
327 ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF;
328 break;
329 case ARM_PWR_LVL1:
330 ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF;
331 break;
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100332 }
333
334 return ret;
335}
336
Soby Mathew9ca28062017-10-11 16:08:58 +0100337/*
338 * The FVP doesn't truly support power management at SYSTEM power domain. The
339 * SYSTEM_SUSPEND will be down-graded to the cluster level within the platform
340 * layer. The `fake` SYSTEM_SUSPEND allows us to validate some of the driver
341 * save and restore sequences on FVP.
342 */
343void fvp_get_sys_suspend_power_state(psci_power_state_t *req_state)
344{
345 unsigned int i;
346
347 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
348 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF;
349}
350
Achin Gupta4f6ad662013-10-25 09:08:21 +0100351/*******************************************************************************
Soby Mathew9ca28062017-10-11 16:08:58 +0100352 * Handler to filter PSCI requests.
353 ******************************************************************************/
354/*
355 * The system power domain suspend is only supported only via
356 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain
357 * will be downgraded to the lower level.
358 */
359static int fvp_validate_power_state(unsigned int power_state,
360 psci_power_state_t *req_state)
361{
362 int rc;
363 rc = arm_validate_power_state(power_state, req_state);
364
365 /*
366 * Ensure that the system power domain level is never suspended
367 * via PSCI CPU SUSPEND API. Currently system suspend is only
368 * supported via PSCI SYSTEM SUSPEND API.
369 */
370 req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN;
371 return rc;
372}
373
374/*
375 * Custom `translate_power_state_by_mpidr` handler for FVP. Unlike in the
376 * `fvp_validate_power_state`, we do not downgrade the system power
377 * domain level request in `power_state` as it will be used to query the
378 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level.
379 */
380static int fvp_translate_power_state_by_mpidr(u_register_t mpidr,
381 unsigned int power_state,
382 psci_power_state_t *output_state)
383{
384 return arm_validate_power_state(power_state, output_state);
385}
386
387/*******************************************************************************
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100388 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
389 * platform layer will take care of registering the handlers with PSCI.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100390 ******************************************************************************/
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100391plat_psci_ops_t plat_arm_psci_pm_ops = {
Soby Mathewfec4eb72015-07-01 16:16:20 +0100392 .cpu_standby = fvp_cpu_standby,
393 .pwr_domain_on = fvp_pwr_domain_on,
394 .pwr_domain_off = fvp_pwr_domain_off,
395 .pwr_domain_suspend = fvp_pwr_domain_suspend,
396 .pwr_domain_on_finish = fvp_pwr_domain_on_finish,
397 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish,
Juan Castillo4dc4a472014-08-12 11:17:06 +0100398 .system_off = fvp_system_off,
Soby Mathew74e52a72014-10-02 16:56:51 +0100399 .system_reset = fvp_system_reset,
Soby Mathew9ca28062017-10-11 16:08:58 +0100400 .validate_power_state = fvp_validate_power_state,
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100401 .validate_ns_entrypoint = arm_validate_ns_entrypoint,
Soby Mathew9ca28062017-10-11 16:08:58 +0100402 .translate_power_state_by_mpidr = fvp_translate_power_state_by_mpidr,
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100403 .get_node_hw_state = fvp_node_hw_state,
Soby Mathew9ca28062017-10-11 16:08:58 +0100404 .get_sys_suspend_power_state = fvp_get_sys_suspend_power_state,
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100405/*
406 * mem_protect is not supported in RESET_TO_BL31 and RESET_TO_SP_MIN,
407 * as that would require mapping in all of NS DRAM into BL31 or BL32.
408 */
409#if !RESET_TO_BL31 && !RESET_TO_SP_MIN
410 .mem_protect_chk = arm_psci_mem_protect_chk,
411 .read_mem_protect = arm_psci_read_mem_protect,
412 .write_mem_protect = arm_nor_psci_write_mem_protect,
413#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100414};