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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handley2b6b5742015-03-19 19:17:53 +00002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#include <arch_helpers.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000032#include <arm_config.h>
Dan Handleyfb42b122014-06-20 09:43:15 +010033#include <arm_gic.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010034#include <assert.h>
Juan Castillo4dc4a472014-08-12 11:17:06 +010035#include <debug.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000036#include <errno.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010037#include <mmio.h>
38#include <platform.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000039#include <plat_arm.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010040#include <psci.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000041#include <v2m_def.h>
Dan Handley4d2e49d2014-04-11 11:52:12 +010042#include "drivers/pwrc/fvp_pwrc.h"
Dan Handleyed6ff952014-05-14 17:44:19 +010043#include "fvp_def.h"
44#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010045
Dan Handley2b6b5742015-03-19 19:17:53 +000046
Soby Mathew7799cf72015-04-16 14:49:09 +010047#if ARM_RECOM_STATE_ID_ENC
48/*
49 * The table storing the valid idle power states. Ensure that the
50 * array entries are populated in ascending order of state-id to
51 * enable us to use binary search during power state validation.
52 * The table must be terminated by a NULL entry.
53 */
54const unsigned int arm_pm_idle_states[] = {
55 /* State-id - 0x01 */
56 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET,
57 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
58 /* State-id - 0x02 */
59 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
60 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
61 /* State-id - 0x22 */
62 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
63 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
64 0,
65};
66#endif
67
Achin Gupta4f6ad662013-10-25 09:08:21 +010068/*******************************************************************************
Achin Gupta85876392014-07-31 17:45:51 +010069 * Function which implements the common FVP specific operations to power down a
70 * cpu in response to a CPU_OFF or CPU_SUSPEND request.
71 ******************************************************************************/
Sandrine Bailleuxa64a8542015-03-05 10:54:34 +000072static void fvp_cpu_pwrdwn_common(void)
Achin Gupta85876392014-07-31 17:45:51 +010073{
Achin Gupta85876392014-07-31 17:45:51 +010074 /* Prevent interrupts from spuriously waking up this cpu */
75 arm_gic_cpuif_deactivate();
76
77 /* Program the power controller to power off this cpu. */
78 fvp_pwrc_write_ppoffr(read_mpidr_el1());
79}
80
81/*******************************************************************************
82 * Function which implements the common FVP specific operations to power down a
83 * cluster in response to a CPU_OFF or CPU_SUSPEND request.
84 ******************************************************************************/
Sandrine Bailleuxa64a8542015-03-05 10:54:34 +000085static void fvp_cluster_pwrdwn_common(void)
Achin Gupta85876392014-07-31 17:45:51 +010086{
87 uint64_t mpidr = read_mpidr_el1();
88
89 /* Disable coherency if this cluster is to be turned off */
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000090 fvp_cci_disable();
Achin Gupta85876392014-07-31 17:45:51 +010091
92 /* Program the power controller to turn the cluster off */
93 fvp_pwrc_write_pcoffr(mpidr);
94}
95
96/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +010097 * FVP handler called when a CPU is about to enter standby.
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +000098 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +010099void fvp_cpu_standby(plat_local_state_t cpu_state)
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000100{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100101
102 assert(cpu_state == ARM_LOCAL_STATE_RET);
103
Andrew Thoelke42e75a72014-04-28 12:28:39 +0100104 /*
105 * Enter standby state
106 * dsb is good practice before using wfi to enter low power states
107 */
108 dsb();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000109 wfi();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000110}
111
112/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100113 * FVP handler called when a power domain is about to be turned on. The
114 * mpidr determines the CPU to be turned on.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100115 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100116int fvp_pwr_domain_on(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100117{
118 int rc = PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100119 unsigned int psysr;
120
Achin Gupta4f6ad662013-10-25 09:08:21 +0100121 /*
Achin Gupta4f6ad662013-10-25 09:08:21 +0100122 * Ensure that we do not cancel an inflight power off request
123 * for the target cpu. That would leave it in a zombie wfi.
124 * Wait for it to power off, program the jump address for the
125 * target cpu and then program the power controller to turn
126 * that cpu on
127 */
128 do {
129 psysr = fvp_pwrc_read_psysr(mpidr);
130 } while (psysr & PSYSR_AFF_L0);
131
Achin Gupta4f6ad662013-10-25 09:08:21 +0100132 fvp_pwrc_write_pponr(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100133 return rc;
134}
135
136/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100137 * FVP handler called when a power domain is about to be turned off. The
138 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100139 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100140void fvp_pwr_domain_off(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100141{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100142 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
143 ARM_LOCAL_STATE_OFF);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144
Achin Gupta85876392014-07-31 17:45:51 +0100145 /*
Soby Mathewfec4eb72015-07-01 16:16:20 +0100146 * If execution reaches this stage then this power domain will be
147 * suspended. Perform at least the cpu specific actions followed
148 * by the cluster specific operations if applicable.
Achin Gupta85876392014-07-31 17:45:51 +0100149 */
150 fvp_cpu_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100151
Soby Mathewfec4eb72015-07-01 16:16:20 +0100152 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
153 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100154 fvp_cluster_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100155
Achin Gupta4f6ad662013-10-25 09:08:21 +0100156}
157
158/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100159 * FVP handler called when a power domain is about to be suspended. The
160 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100161 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100162void fvp_pwr_domain_suspend(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100163{
Soby Mathewffb4ab12014-09-26 15:08:52 +0100164 unsigned long mpidr;
165
Soby Mathewfec4eb72015-07-01 16:16:20 +0100166 /*
167 * FVP has retention only at cpu level. Just return
168 * as nothing is to be done for retention.
169 */
170 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
171 ARM_LOCAL_STATE_RET)
Soby Mathew74e52a72014-10-02 16:56:51 +0100172 return;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100173
Soby Mathewfec4eb72015-07-01 16:16:20 +0100174 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
175 ARM_LOCAL_STATE_OFF);
176
Soby Mathewffb4ab12014-09-26 15:08:52 +0100177 /* Get the mpidr for this cpu */
178 mpidr = read_mpidr_el1();
179
Achin Gupta85876392014-07-31 17:45:51 +0100180 /* Program the power controller to enable wakeup interrupts. */
181 fvp_pwrc_set_wen(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100182
Achin Gupta85876392014-07-31 17:45:51 +0100183 /* Perform the common cpu specific operations */
184 fvp_cpu_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100185
Achin Gupta85876392014-07-31 17:45:51 +0100186 /* Perform the common cluster specific operations */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100187 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
188 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100189 fvp_cluster_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100190}
191
192/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100193 * FVP handler called when a power domain has just been powered on after
194 * being turned off earlier. The target_state encodes the low power state that
195 * each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100196 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100197void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100198{
Soby Mathewffb4ab12014-09-26 15:08:52 +0100199 unsigned long mpidr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100200
Soby Mathewfec4eb72015-07-01 16:16:20 +0100201 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
202 ARM_LOCAL_STATE_OFF);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100203
Soby Mathewffb4ab12014-09-26 15:08:52 +0100204 /* Get the mpidr for this cpu */
205 mpidr = read_mpidr_el1();
206
Achin Gupta85876392014-07-31 17:45:51 +0100207 /* Perform the common cluster specific operations */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100208 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
209 ARM_LOCAL_STATE_OFF) {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100210 /*
Achin Gupta85876392014-07-31 17:45:51 +0100211 * This CPU might have woken up whilst the cluster was
212 * attempting to power down. In this case the FVP power
213 * controller will have a pending cluster power off request
214 * which needs to be cleared by writing to the PPONR register.
215 * This prevents the power controller from interpreting a
216 * subsequent entry of this cpu into a simple wfi as a power
217 * down request.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100218 */
Achin Gupta85876392014-07-31 17:45:51 +0100219 fvp_pwrc_write_pponr(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100220
Achin Gupta85876392014-07-31 17:45:51 +0100221 /* Enable coherency if this cluster was off */
222 fvp_cci_enable();
223 }
Achin Guptab127cdb2013-11-12 16:40:00 +0000224
Achin Gupta85876392014-07-31 17:45:51 +0100225 /*
Achin Gupta85876392014-07-31 17:45:51 +0100226 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
227 * with a cpu power down unless the bit is set again
228 */
229 fvp_pwrc_clr_wen(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100230
Achin Gupta85876392014-07-31 17:45:51 +0100231 /* Enable the gic cpu interface */
232 arm_gic_cpuif_setup();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100233
Achin Gupta85876392014-07-31 17:45:51 +0100234 /* TODO: This setup is needed only after a cold boot */
235 arm_gic_pcpu_distif_setup();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236}
237
238/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100239 * FVP handler called when a power domain has just been powered on after
240 * having been suspended earlier. The target_state encodes the low power state
241 * that each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100242 * TODO: At the moment we reuse the on finisher and reinitialize the secure
243 * context. Need to implement a separate suspend finisher.
244 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +0100245void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100246{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100247 /*
248 * Nothing to be done on waking up from retention from CPU level.
249 */
250 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
251 ARM_LOCAL_STATE_RET)
252 return;
253
254 fvp_pwr_domain_on_finish(target_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100255}
256
Juan Castillo4dc4a472014-08-12 11:17:06 +0100257/*******************************************************************************
258 * FVP handlers to shutdown/reboot the system
259 ******************************************************************************/
260static void __dead2 fvp_system_off(void)
261{
262 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000263 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
264 V2M_CFGCTRL_START |
265 V2M_CFGCTRL_RW |
266 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100267 wfi();
268 ERROR("FVP System Off: operation not handled.\n");
269 panic();
270}
271
272static void __dead2 fvp_system_reset(void)
273{
274 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000275 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
276 V2M_CFGCTRL_START |
277 V2M_CFGCTRL_RW |
278 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100279 wfi();
280 ERROR("FVP System Reset: operation not handled.\n");
281 panic();
282}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100283
284/*******************************************************************************
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100285 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
286 * platform layer will take care of registering the handlers with PSCI.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100287 ******************************************************************************/
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100288const plat_psci_ops_t plat_arm_psci_pm_ops = {
Soby Mathewfec4eb72015-07-01 16:16:20 +0100289 .cpu_standby = fvp_cpu_standby,
290 .pwr_domain_on = fvp_pwr_domain_on,
291 .pwr_domain_off = fvp_pwr_domain_off,
292 .pwr_domain_suspend = fvp_pwr_domain_suspend,
293 .pwr_domain_on_finish = fvp_pwr_domain_on_finish,
294 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish,
Juan Castillo4dc4a472014-08-12 11:17:06 +0100295 .system_off = fvp_system_off,
Soby Mathew74e52a72014-10-02 16:56:51 +0100296 .system_reset = fvp_system_reset,
Soby Mathew0d9e8522015-07-15 13:36:24 +0100297 .validate_power_state = arm_validate_power_state,
298 .validate_ns_entrypoint = arm_validate_ns_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +0100299};