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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -05002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2bd4ef22014-04-09 13:14:54 +01007#include <assert.h>
Dan Handley2b6b5742015-03-19 19:17:53 +00008#include <errno.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <arch_helpers.h>
11#include <common/debug.h>
12#include <drivers/arm/gicv3.h>
Antonio Nino Diazf13d09a2019-01-23 21:50:09 +000013#include <drivers/arm/fvp/fvp_pwrc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/extensions/spe.h>
15#include <lib/mmio.h>
16#include <lib/psci/psci.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000017#include <plat/arm/common/arm_config.h>
18#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019#include <plat/common/platform.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +000020#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021
Dan Handleyed6ff952014-05-14 17:44:19 +010022#include "fvp_private.h"
Ambroise Vincentb237bca2019-02-13 15:58:00 +000023#include "../drivers/arm/gic/v3/gicv3_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010024
Dan Handley2b6b5742015-03-19 19:17:53 +000025
Soby Mathew7799cf72015-04-16 14:49:09 +010026#if ARM_RECOM_STATE_ID_ENC
27/*
28 * The table storing the valid idle power states. Ensure that the
29 * array entries are populated in ascending order of state-id to
30 * enable us to use binary search during power state validation.
31 * The table must be terminated by a NULL entry.
32 */
33const unsigned int arm_pm_idle_states[] = {
34 /* State-id - 0x01 */
35 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET,
36 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
37 /* State-id - 0x02 */
38 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
39 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
40 /* State-id - 0x22 */
41 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
42 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
Soby Mathew9ca28062017-10-11 16:08:58 +010043 /* State-id - 0x222 */
44 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
45 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
Soby Mathew7799cf72015-04-16 14:49:09 +010046 0,
47};
48#endif
49
Achin Gupta4f6ad662013-10-25 09:08:21 +010050/*******************************************************************************
Achin Gupta85876392014-07-31 17:45:51 +010051 * Function which implements the common FVP specific operations to power down a
Achin Gupta85876392014-07-31 17:45:51 +010052 * cluster in response to a CPU_OFF or CPU_SUSPEND request.
53 ******************************************************************************/
Sandrine Bailleuxa64a8542015-03-05 10:54:34 +000054static void fvp_cluster_pwrdwn_common(void)
Achin Gupta85876392014-07-31 17:45:51 +010055{
56 uint64_t mpidr = read_mpidr_el1();
57
dp-armee3457b2017-05-23 09:32:49 +010058#if ENABLE_SPE_FOR_LOWER_ELS
59 /*
60 * On power down we need to disable statistical profiling extensions
61 * before exiting coherency.
62 */
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010063 spe_disable();
dp-armee3457b2017-05-23 09:32:49 +010064#endif
65
Achin Gupta85876392014-07-31 17:45:51 +010066 /* Disable coherency if this cluster is to be turned off */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000067 fvp_interconnect_disable();
Achin Gupta85876392014-07-31 17:45:51 +010068
69 /* Program the power controller to turn the cluster off */
70 fvp_pwrc_write_pcoffr(mpidr);
71}
72
Soby Mathew9ca28062017-10-11 16:08:58 +010073/*
74 * Empty implementation of these hooks avoid setting the GICR_WAKER.Sleep bit
75 * on ARM GICv3 implementations on FVP. This is required, because FVP does not
76 * support SYSTEM_SUSPEND and it is `faked` in firmware. Hence, for wake up
77 * from `fake` system suspend the GIC must not be powered off.
78 */
Roberto Vargas1a6eed32018-02-12 12:36:17 +000079void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num)
Soby Mathew9ca28062017-10-11 16:08:58 +010080{}
81
Roberto Vargas1a6eed32018-02-12 12:36:17 +000082void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num)
Soby Mathew9ca28062017-10-11 16:08:58 +010083{}
84
Soby Mathew12012dd2015-10-26 14:01:53 +000085static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state)
86{
87 unsigned long mpidr;
88
89 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
90 ARM_LOCAL_STATE_OFF);
91
92 /* Get the mpidr for this cpu */
93 mpidr = read_mpidr_el1();
94
95 /* Perform the common cluster specific operations */
96 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
97 ARM_LOCAL_STATE_OFF) {
98 /*
99 * This CPU might have woken up whilst the cluster was
100 * attempting to power down. In this case the FVP power
101 * controller will have a pending cluster power off request
102 * which needs to be cleared by writing to the PPONR register.
103 * This prevents the power controller from interpreting a
104 * subsequent entry of this cpu into a simple wfi as a power
105 * down request.
106 */
107 fvp_pwrc_write_pponr(mpidr);
108
109 /* Enable coherency if this cluster was off */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000110 fvp_interconnect_enable();
Soby Mathew12012dd2015-10-26 14:01:53 +0000111 }
Soby Mathew9ca28062017-10-11 16:08:58 +0100112 /* Perform the common system specific operations */
113 if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
114 ARM_LOCAL_STATE_OFF)
115 arm_system_pwr_domain_resume();
Soby Mathew12012dd2015-10-26 14:01:53 +0000116
117 /*
118 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
119 * with a cpu power down unless the bit is set again
120 */
121 fvp_pwrc_clr_wen(mpidr);
122}
123
124
Achin Gupta85876392014-07-31 17:45:51 +0100125/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100126 * FVP handler called when a CPU is about to enter standby.
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000127 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000128static void fvp_cpu_standby(plat_local_state_t cpu_state)
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000129{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100130
131 assert(cpu_state == ARM_LOCAL_STATE_RET);
132
Andrew Thoelke42e75a72014-04-28 12:28:39 +0100133 /*
134 * Enter standby state
135 * dsb is good practice before using wfi to enter low power states
136 */
137 dsb();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000138 wfi();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000139}
140
141/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100142 * FVP handler called when a power domain is about to be turned on. The
143 * mpidr determines the CPU to be turned on.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000145static int fvp_pwr_domain_on(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100146{
147 int rc = PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100148 unsigned int psysr;
149
Achin Gupta4f6ad662013-10-25 09:08:21 +0100150 /*
Sandrine Bailleux7175bde2015-12-08 14:18:24 +0000151 * Ensure that we do not cancel an inflight power off request for the
152 * target cpu. That would leave it in a zombie wfi. Wait for it to power
153 * off and then program the power controller to turn that CPU on.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100154 */
155 do {
156 psysr = fvp_pwrc_read_psysr(mpidr);
Sathees Balya50905c72018-10-05 13:30:59 +0100157 } while ((psysr & PSYSR_AFF_L0) != 0U);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100158
Achin Gupta4f6ad662013-10-25 09:08:21 +0100159 fvp_pwrc_write_pponr(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100160 return rc;
161}
162
163/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100164 * FVP handler called when a power domain is about to be turned off. The
165 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100166 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000167static void fvp_pwr_domain_off(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100168{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100169 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
170 ARM_LOCAL_STATE_OFF);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100171
Achin Gupta85876392014-07-31 17:45:51 +0100172 /*
Soby Mathewfec4eb72015-07-01 16:16:20 +0100173 * If execution reaches this stage then this power domain will be
174 * suspended. Perform at least the cpu specific actions followed
175 * by the cluster specific operations if applicable.
Achin Gupta85876392014-07-31 17:45:51 +0100176 */
Jeenu Viswambharan6ad35482016-12-09 11:14:34 +0000177
178 /* Prevent interrupts from spuriously waking up this cpu */
179 plat_arm_gic_cpuif_disable();
180
181 /* Turn redistributor off */
182 plat_arm_gic_redistif_off();
183
184 /* Program the power controller to power off this cpu. */
185 fvp_pwrc_write_ppoffr(read_mpidr_el1());
Achin Gupta4f6ad662013-10-25 09:08:21 +0100186
Soby Mathewfec4eb72015-07-01 16:16:20 +0100187 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
188 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100189 fvp_cluster_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100190
Achin Gupta4f6ad662013-10-25 09:08:21 +0100191}
192
193/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100194 * FVP handler called when a power domain is about to be suspended. The
195 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100196 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000197static void fvp_pwr_domain_suspend(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100198{
Soby Mathewffb4ab12014-09-26 15:08:52 +0100199 unsigned long mpidr;
200
Soby Mathewfec4eb72015-07-01 16:16:20 +0100201 /*
202 * FVP has retention only at cpu level. Just return
203 * as nothing is to be done for retention.
204 */
205 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
206 ARM_LOCAL_STATE_RET)
Soby Mathew74e52a72014-10-02 16:56:51 +0100207 return;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100208
Soby Mathewfec4eb72015-07-01 16:16:20 +0100209 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
210 ARM_LOCAL_STATE_OFF);
211
Soby Mathewffb4ab12014-09-26 15:08:52 +0100212 /* Get the mpidr for this cpu */
213 mpidr = read_mpidr_el1();
214
Achin Gupta85876392014-07-31 17:45:51 +0100215 /* Program the power controller to enable wakeup interrupts. */
216 fvp_pwrc_set_wen(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100217
Jeenu Viswambharan6ad35482016-12-09 11:14:34 +0000218 /* Prevent interrupts from spuriously waking up this cpu */
219 plat_arm_gic_cpuif_disable();
220
221 /*
222 * The Redistributor is not powered off as it can potentially prevent
223 * wake up events reaching the CPUIF and/or might lead to losing
224 * register context.
225 */
226
Achin Gupta85876392014-07-31 17:45:51 +0100227 /* Perform the common cluster specific operations */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100228 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
229 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100230 fvp_cluster_pwrdwn_common();
Soby Mathew9ca28062017-10-11 16:08:58 +0100231
232 /* Perform the common system specific operations */
233 if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
234 ARM_LOCAL_STATE_OFF)
235 arm_system_pwr_domain_save();
236
237 /* Program the power controller to power off this cpu. */
238 fvp_pwrc_write_ppoffr(read_mpidr_el1());
Achin Gupta4f6ad662013-10-25 09:08:21 +0100239}
240
241/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100242 * FVP handler called when a power domain has just been powered on after
243 * being turned off earlier. The target_state encodes the low power state that
244 * each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100245 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000246static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100247{
Soby Mathew12012dd2015-10-26 14:01:53 +0000248 fvp_power_domain_on_finish_common(target_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100249
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500250}
251
252/*******************************************************************************
253 * FVP handler called when a power domain has just been powered on and the cpu
254 * and its cluster are fully participating in coherent transaction on the
255 * interconnect. Data cache must be enabled for CPU at this point.
256 ******************************************************************************/
257static void fvp_pwr_domain_on_finish_late(const psci_power_state_t *target_state)
258{
259 /* Program GIC per-cpu distributor or re-distributor interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000260 plat_arm_gic_pcpu_init();
261
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500262 /* Enable GIC CPU interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000263 plat_arm_gic_cpuif_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100264}
265
266/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100267 * FVP handler called when a power domain has just been powered on after
268 * having been suspended earlier. The target_state encodes the low power state
269 * that each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100270 * TODO: At the moment we reuse the on finisher and reinitialize the secure
271 * context. Need to implement a separate suspend finisher.
272 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000273static void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100274{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100275 /*
276 * Nothing to be done on waking up from retention from CPU level.
277 */
278 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
279 ARM_LOCAL_STATE_RET)
280 return;
281
Soby Mathew12012dd2015-10-26 14:01:53 +0000282 fvp_power_domain_on_finish_common(target_state);
283
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500284 /* Enable GIC CPU interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000285 plat_arm_gic_cpuif_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100286}
287
Juan Castillo4dc4a472014-08-12 11:17:06 +0100288/*******************************************************************************
289 * FVP handlers to shutdown/reboot the system
290 ******************************************************************************/
291static void __dead2 fvp_system_off(void)
292{
293 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000294 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
295 V2M_CFGCTRL_START |
296 V2M_CFGCTRL_RW |
297 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100298 wfi();
299 ERROR("FVP System Off: operation not handled.\n");
300 panic();
301}
302
303static void __dead2 fvp_system_reset(void)
304{
305 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000306 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
307 V2M_CFGCTRL_START |
308 V2M_CFGCTRL_RW |
309 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100310 wfi();
311 ERROR("FVP System Reset: operation not handled.\n");
312 panic();
313}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100314
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100315static int fvp_node_hw_state(u_register_t target_cpu,
316 unsigned int power_level)
317{
318 unsigned int psysr;
319 int ret;
320
321 /*
322 * The format of 'power_level' is implementation-defined, but 0 must
323 * mean a CPU. We also allow 1 to denote the cluster
324 */
Sathees Balya50905c72018-10-05 13:30:59 +0100325 if ((power_level != ARM_PWR_LVL0) && (power_level != ARM_PWR_LVL1))
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100326 return PSCI_E_INVALID_PARAMS;
327
328 /*
329 * Read the status of the given MPDIR from FVP power controller. The
330 * power controller only gives us on/off status, so map that to expected
331 * return values of the PSCI call
332 */
333 psysr = fvp_pwrc_read_psysr(target_cpu);
334 if (psysr == PSYSR_INVALID)
335 return PSCI_E_INVALID_PARAMS;
336
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000337 if (power_level == ARM_PWR_LVL0) {
Sathees Balya50905c72018-10-05 13:30:59 +0100338 ret = ((psysr & PSYSR_AFF_L0) != 0U) ? HW_ON : HW_OFF;
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000339 } else {
340 /* power_level == ARM_PWR_LVL1 */
Sathees Balya50905c72018-10-05 13:30:59 +0100341 ret = ((psysr & PSYSR_AFF_L1) != 0U) ? HW_ON : HW_OFF;
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100342 }
343
344 return ret;
345}
346
Soby Mathew9ca28062017-10-11 16:08:58 +0100347/*
348 * The FVP doesn't truly support power management at SYSTEM power domain. The
349 * SYSTEM_SUSPEND will be down-graded to the cluster level within the platform
350 * layer. The `fake` SYSTEM_SUSPEND allows us to validate some of the driver
351 * save and restore sequences on FVP.
352 */
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000353#if !ARM_BL31_IN_DRAM
354static void fvp_get_sys_suspend_power_state(psci_power_state_t *req_state)
Soby Mathew9ca28062017-10-11 16:08:58 +0100355{
356 unsigned int i;
357
358 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
359 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF;
360}
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000361#endif
Soby Mathew9ca28062017-10-11 16:08:58 +0100362
Achin Gupta4f6ad662013-10-25 09:08:21 +0100363/*******************************************************************************
Soby Mathew9ca28062017-10-11 16:08:58 +0100364 * Handler to filter PSCI requests.
365 ******************************************************************************/
366/*
367 * The system power domain suspend is only supported only via
368 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain
369 * will be downgraded to the lower level.
370 */
371static int fvp_validate_power_state(unsigned int power_state,
372 psci_power_state_t *req_state)
373{
374 int rc;
375 rc = arm_validate_power_state(power_state, req_state);
376
377 /*
378 * Ensure that the system power domain level is never suspended
379 * via PSCI CPU SUSPEND API. Currently system suspend is only
380 * supported via PSCI SYSTEM SUSPEND API.
381 */
382 req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN;
383 return rc;
384}
385
386/*
387 * Custom `translate_power_state_by_mpidr` handler for FVP. Unlike in the
388 * `fvp_validate_power_state`, we do not downgrade the system power
389 * domain level request in `power_state` as it will be used to query the
390 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level.
391 */
392static int fvp_translate_power_state_by_mpidr(u_register_t mpidr,
393 unsigned int power_state,
394 psci_power_state_t *output_state)
395{
396 return arm_validate_power_state(power_state, output_state);
397}
398
399/*******************************************************************************
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100400 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
401 * platform layer will take care of registering the handlers with PSCI.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100402 ******************************************************************************/
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100403plat_psci_ops_t plat_arm_psci_pm_ops = {
Soby Mathewfec4eb72015-07-01 16:16:20 +0100404 .cpu_standby = fvp_cpu_standby,
405 .pwr_domain_on = fvp_pwr_domain_on,
406 .pwr_domain_off = fvp_pwr_domain_off,
407 .pwr_domain_suspend = fvp_pwr_domain_suspend,
408 .pwr_domain_on_finish = fvp_pwr_domain_on_finish,
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500409 .pwr_domain_on_finish_late = fvp_pwr_domain_on_finish_late,
Soby Mathewfec4eb72015-07-01 16:16:20 +0100410 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish,
Juan Castillo4dc4a472014-08-12 11:17:06 +0100411 .system_off = fvp_system_off,
Soby Mathew74e52a72014-10-02 16:56:51 +0100412 .system_reset = fvp_system_reset,
Soby Mathew9ca28062017-10-11 16:08:58 +0100413 .validate_power_state = fvp_validate_power_state,
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100414 .validate_ns_entrypoint = arm_validate_psci_entrypoint,
Soby Mathew9ca28062017-10-11 16:08:58 +0100415 .translate_power_state_by_mpidr = fvp_translate_power_state_by_mpidr,
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100416 .get_node_hw_state = fvp_node_hw_state,
Antonio Nino Diaz0b6af832017-11-22 12:00:44 +0000417#if !ARM_BL31_IN_DRAM
418 /*
419 * The TrustZone Controller is set up during the warmboot sequence after
420 * resuming the CPU from a SYSTEM_SUSPEND. If BL31 is located in SRAM
421 * this is not a problem but, if it is in TZC-secured DRAM, it tries to
422 * reconfigure the same memory it is running on, causing an exception.
423 */
Soby Mathew9ca28062017-10-11 16:08:58 +0100424 .get_sys_suspend_power_state = fvp_get_sys_suspend_power_state,
Antonio Nino Diaz0b6af832017-11-22 12:00:44 +0000425#endif
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100426 .mem_protect_chk = arm_psci_mem_protect_chk,
427 .read_mem_protect = arm_psci_read_mem_protect,
428 .write_mem_protect = arm_nor_psci_write_mem_protect,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100429};
Chandni Cherukurie4bf6a02018-11-14 13:43:59 +0530430
431const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
432{
433 return ops;
434}