Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
Varun Wadekar | 2909fa3 | 2020-01-09 08:52:10 -0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Varun Wadekar | 2909fa3 | 2020-01-09 08:52:10 -0800 | [diff] [blame] | 7 | #ifndef TEGRA_DEF_H |
| 8 | #define TEGRA_DEF_H |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | /******************************************************************************* |
anzhou | 508d20d | 2020-07-21 16:22:44 +0800 | [diff] [blame] | 13 | * Platform BL31 specific defines. |
| 14 | ******************************************************************************/ |
| 15 | #define BL31_SIZE U(0x40000) |
| 16 | |
| 17 | /******************************************************************************* |
Anthony Zhou | 7534c20 | 2019-03-11 15:50:32 +0800 | [diff] [blame] | 18 | * Chip specific cluster and cpu numbers |
| 19 | ******************************************************************************/ |
| 20 | #define PLATFORM_CLUSTER_COUNT U(4) |
| 21 | #define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) |
| 22 | |
| 23 | /******************************************************************************* |
Steven Kao | 0e6dce6 | 2018-02-09 21:01:49 +0800 | [diff] [blame] | 24 | * Chip specific page table and MMU setup constants |
| 25 | ******************************************************************************/ |
| 26 | #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40) |
| 27 | #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40) |
| 28 | |
| 29 | /******************************************************************************* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 30 | * These values are used by the PSCI implementation during the `CPU_SUSPEND` |
| 31 | * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' |
| 32 | * parameter. |
| 33 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 34 | #define PSTATE_ID_CORE_IDLE U(6) |
| 35 | #define PSTATE_ID_CORE_POWERDN U(7) |
| 36 | #define PSTATE_ID_SOC_POWERDN U(2) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 37 | |
| 38 | /******************************************************************************* |
| 39 | * Platform power states (used by PSCI framework) |
| 40 | * |
| 41 | * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID |
| 42 | * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID |
| 43 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 44 | #define PLAT_MAX_RET_STATE U(1) |
| 45 | #define PLAT_MAX_OFF_STATE U(8) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 46 | |
| 47 | /******************************************************************************* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 48 | * Secure IRQ definitions |
| 49 | ******************************************************************************/ |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 50 | #define TEGRA194_MAX_SEC_IRQS U(2) |
| 51 | #define TEGRA194_TOP_WDT_IRQ U(49) |
| 52 | #define TEGRA194_AON_WDT_IRQ U(50) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 53 | |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 54 | #define TEGRA194_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */ |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 55 | |
| 56 | /******************************************************************************* |
Varun Wadekar | e55c27b | 2018-09-13 08:47:43 -0700 | [diff] [blame] | 57 | * Clock identifier for the SE device |
| 58 | ******************************************************************************/ |
| 59 | #define TEGRA194_CLK_SE U(124) |
| 60 | #define TEGRA_CLK_SE TEGRA194_CLK_SE |
| 61 | |
| 62 | /******************************************************************************* |
Elyes Haouas | 2be03c0 | 2023-02-13 09:14:48 +0100 | [diff] [blame^] | 63 | * Tegra Miscellaneous register constants |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 64 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 65 | #define TEGRA_MISC_BASE U(0x00100000) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 66 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 67 | #define HARDWARE_REVISION_OFFSET U(0x4) |
| 68 | #define MISCREG_EMU_REVID U(0x3160) |
| 69 | #define BOARD_MASK_BITS U(0xFF) |
| 70 | #define BOARD_SHIFT_BITS U(24) |
| 71 | #define MISCREG_PFCFG U(0x200C) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 72 | |
| 73 | /******************************************************************************* |
Varun Wadekar | 602cf7e | 2018-04-03 13:10:48 -0700 | [diff] [blame] | 74 | * Tegra General Purpose Centralised DMA constants |
| 75 | ******************************************************************************/ |
| 76 | #define TEGRA_GPCDMA_BASE U(0x02610000) |
| 77 | |
| 78 | /******************************************************************************* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 79 | * Tegra Memory Controller constants |
| 80 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 81 | #define TEGRA_MC_STREAMID_BASE U(0x02C00000) |
| 82 | #define TEGRA_MC_BASE U(0x02C10000) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 83 | |
Varun Wadekar | 07897a9 | 2017-02-13 09:00:04 -0800 | [diff] [blame] | 84 | /* General Security Carveout register macros */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 85 | #define MC_GSC_CONFIG_REGS_SIZE U(0x40) |
| 86 | #define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1) |
| 87 | #define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0) |
| 88 | #define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27) |
| 89 | #define MC_GSC_BASE_LO_SHIFT U(12) |
| 90 | #define MC_GSC_BASE_LO_MASK U(0xFFFFF) |
| 91 | #define MC_GSC_BASE_HI_SHIFT U(0) |
| 92 | #define MC_GSC_BASE_HI_MASK U(3) |
Varun Wadekar | 4309d7b | 2017-10-03 15:25:44 -0700 | [diff] [blame] | 93 | #define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31) |
Varun Wadekar | 07897a9 | 2017-02-13 09:00:04 -0800 | [diff] [blame] | 94 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 95 | /* TZDRAM carveout configuration registers */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 96 | #define MC_SECURITY_CFG0_0 U(0x70) |
| 97 | #define MC_SECURITY_CFG1_0 U(0x74) |
| 98 | #define MC_SECURITY_CFG3_0 U(0x9BC) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 99 | |
Harvey Hsieh | 53fc032 | 2017-08-09 16:26:33 +0800 | [diff] [blame] | 100 | #define MC_SECURITY_BOM_MASK (U(0xFFF) << 20) |
| 101 | #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) |
| 102 | #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) |
| 103 | |
Steven Kao | ee93ed1 | 2017-11-14 19:12:58 +0800 | [diff] [blame] | 104 | #define MC_SECURITY_CFG_REG_CTRL_0 U(0x154) |
| 105 | #define SECURITY_CFG_WRITE_ACCESS_BIT (U(0x1) << 0) |
Steven Kao | b2b4305 | 2017-11-30 11:53:29 +0800 | [diff] [blame] | 106 | #define SECURITY_CFG_WRITE_ACCESS_ENABLE U(0x0) |
| 107 | #define SECURITY_CFG_WRITE_ACCESS_DISABLE U(0x1) |
Steven Kao | ee93ed1 | 2017-11-14 19:12:58 +0800 | [diff] [blame] | 108 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 109 | /* Video Memory carveout configuration registers */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 110 | #define MC_VIDEO_PROTECT_BASE_HI U(0x978) |
| 111 | #define MC_VIDEO_PROTECT_BASE_LO U(0x648) |
| 112 | #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) |
Anthony Zhou | 41eac8a | 2019-12-04 14:58:23 +0800 | [diff] [blame] | 113 | #define MC_VIDEO_PROTECT_REG_CTRL U(0x650) |
| 114 | #define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 115 | |
Varun Wadekar | 07897a9 | 2017-02-13 09:00:04 -0800 | [diff] [blame] | 116 | /* |
| 117 | * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the |
| 118 | * non-overlapping Video memory region |
| 119 | */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 120 | #define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0) |
| 121 | #define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4) |
| 122 | #define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8) |
| 123 | #define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC) |
| 124 | #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0) |
Varun Wadekar | 07897a9 | 2017-02-13 09:00:04 -0800 | [diff] [blame] | 125 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 126 | /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 127 | #define MC_TZRAM_CARVEOUT_CFG U(0x2190) |
| 128 | #define MC_TZRAM_BASE_LO U(0x2194) |
| 129 | #define MC_TZRAM_BASE_HI U(0x2198) |
| 130 | #define MC_TZRAM_SIZE U(0x219C) |
Varun Wadekar | 4309d7b | 2017-10-03 15:25:44 -0700 | [diff] [blame] | 131 | #define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0) |
| 132 | #define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4) |
| 133 | #define TZRAM_ALLOW_MPCORER (U(1) << 7) |
| 134 | #define TZRAM_ALLOW_MPCOREW (U(1) << 25) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 135 | |
| 136 | /* Memory Controller Reset Control registers */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 137 | #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (U(1) << 28) |
| 138 | #define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (U(1) << 29) |
| 139 | #define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (U(1) << 30) |
| 140 | #define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (U(1) << 31) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 141 | |
| 142 | /******************************************************************************* |
| 143 | * Tegra UART Controller constants |
| 144 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 145 | #define TEGRA_UARTA_BASE U(0x03100000) |
| 146 | #define TEGRA_UARTB_BASE U(0x03110000) |
| 147 | #define TEGRA_UARTC_BASE U(0x0C280000) |
| 148 | #define TEGRA_UARTD_BASE U(0x03130000) |
| 149 | #define TEGRA_UARTE_BASE U(0x03140000) |
| 150 | #define TEGRA_UARTF_BASE U(0x03150000) |
| 151 | #define TEGRA_UARTG_BASE U(0x0C290000) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 152 | |
| 153 | /******************************************************************************* |
Varun Wadekar | 03aa014 | 2018-01-23 14:51:40 -0800 | [diff] [blame] | 154 | * XUSB PADCTL |
| 155 | ******************************************************************************/ |
| 156 | #define TEGRA_XUSB_PADCTL_BASE U(0x03520000) |
| 157 | #define TEGRA_XUSB_PADCTL_SIZE U(0x10000) |
| 158 | #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c) |
| 159 | #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370) |
| 160 | #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374) |
| 161 | #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378) |
| 162 | #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c) |
| 163 | #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c) |
| 164 | |
| 165 | /******************************************************************************* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 166 | * Tegra Fuse Controller related constants |
| 167 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 168 | #define TEGRA_FUSE_BASE U(0x03820000) |
| 169 | #define OPT_SUBREVISION U(0x248) |
| 170 | #define SUBREVISION_MASK U(0xF) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 171 | |
| 172 | /******************************************************************************* |
| 173 | * GICv2 & interrupt handling related constants |
| 174 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 175 | #define TEGRA_GICD_BASE U(0x03881000) |
| 176 | #define TEGRA_GICC_BASE U(0x03882000) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 177 | |
| 178 | /******************************************************************************* |
| 179 | * Security Engine related constants |
| 180 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 181 | #define TEGRA_SE0_BASE U(0x03AC0000) |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 182 | #define SE0_MUTEX_WATCHDOG_NS_LIMIT U(0x6C) |
| 183 | #define SE0_AES0_ENTROPY_SRC_AGE_CTRL U(0x2FC) |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 184 | #define TEGRA_PKA1_BASE U(0x03AD0000) |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 185 | #define SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL U(0x144) |
| 186 | #define PKA1_MUTEX_WATCHDOG_NS_LIMIT SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 187 | #define TEGRA_RNG1_BASE U(0x03AE0000) |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 188 | #define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 189 | |
| 190 | /******************************************************************************* |
steven kao | e579606 | 2018-01-02 19:09:04 -0800 | [diff] [blame] | 191 | * Tegra HSP doorbell #0 constants |
| 192 | ******************************************************************************/ |
Varun Wadekar | 03aa014 | 2018-01-23 14:51:40 -0800 | [diff] [blame] | 193 | #define TEGRA_HSP_DBELL_BASE U(0x03C90000) |
| 194 | #define HSP_DBELL_1_ENABLE U(0x104) |
| 195 | #define HSP_DBELL_3_TRIGGER U(0x300) |
| 196 | #define HSP_DBELL_3_ENABLE U(0x304) |
steven kao | e579606 | 2018-01-02 19:09:04 -0800 | [diff] [blame] | 197 | |
| 198 | /******************************************************************************* |
Varun Wadekar | 9d15f7e | 2019-08-21 14:01:31 -0700 | [diff] [blame] | 199 | * Tegra hardware synchronization primitives for the SPE engine |
| 200 | ******************************************************************************/ |
| 201 | #define TEGRA_AON_HSP_SM_6_7_BASE U(0x0c190000) |
| 202 | #define TEGRA_CONSOLE_SPE_BASE (TEGRA_AON_HSP_SM_6_7_BASE + U(0x8000)) |
| 203 | |
| 204 | /******************************************************************************* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 205 | * Tegra micro-seconds timer constants |
| 206 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 207 | #define TEGRA_TMRUS_BASE U(0x0C2E0000) |
| 208 | #define TEGRA_TMRUS_SIZE U(0x10000) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 209 | |
| 210 | /******************************************************************************* |
| 211 | * Tegra Power Mgmt Controller constants |
| 212 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 213 | #define TEGRA_PMC_BASE U(0x0C360000) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 214 | |
| 215 | /******************************************************************************* |
| 216 | * Tegra scratch registers constants |
| 217 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 218 | #define TEGRA_SCRATCH_BASE U(0x0C390000) |
Jeetesh Burman | dbcc95c | 2018-07-06 20:03:38 +0530 | [diff] [blame] | 219 | #define SECURE_SCRATCH_RSV68_LO U(0x284) |
| 220 | #define SECURE_SCRATCH_RSV68_HI U(0x288) |
| 221 | #define SECURE_SCRATCH_RSV69_LO U(0x28C) |
| 222 | #define SECURE_SCRATCH_RSV69_HI U(0x290) |
| 223 | #define SECURE_SCRATCH_RSV70_LO U(0x294) |
| 224 | #define SECURE_SCRATCH_RSV70_HI U(0x298) |
| 225 | #define SECURE_SCRATCH_RSV71_LO U(0x29C) |
| 226 | #define SECURE_SCRATCH_RSV71_HI U(0x2A0) |
Jeetesh Burman | 254b57d | 2018-07-06 19:58:30 +0530 | [diff] [blame] | 227 | #define SECURE_SCRATCH_RSV72_LO U(0x2A4) |
| 228 | #define SECURE_SCRATCH_RSV72_HI U(0x2A8) |
Steven Kao | 08ac273 | 2018-02-09 21:35:20 +0800 | [diff] [blame] | 229 | #define SECURE_SCRATCH_RSV75 U(0x2BC) |
steven kao | 150d033 | 2017-12-23 17:58:58 -0800 | [diff] [blame] | 230 | #define SECURE_SCRATCH_RSV81_LO U(0x2EC) |
| 231 | #define SECURE_SCRATCH_RSV81_HI U(0x2F0) |
Steven Kao | 4607f17 | 2017-10-23 18:35:14 +0800 | [diff] [blame] | 232 | #define SECURE_SCRATCH_RSV97 U(0x36C) |
| 233 | #define SECURE_SCRATCH_RSV99_LO U(0x37C) |
| 234 | #define SECURE_SCRATCH_RSV99_HI U(0x380) |
| 235 | #define SECURE_SCRATCH_RSV109_LO U(0x3CC) |
| 236 | #define SECURE_SCRATCH_RSV109_HI U(0x3D0) |
| 237 | |
Steven Kao | 08ac273 | 2018-02-09 21:35:20 +0800 | [diff] [blame] | 238 | #define SCRATCH_BL31_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75 |
| 239 | #define SCRATCH_BL31_PARAMS_HI_ADDR_MASK U(0xFFFF) |
| 240 | #define SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT U(0) |
| 241 | #define SCRATCH_BL31_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_LO |
| 242 | #define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75 |
| 243 | #define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK U(0xFFFF0000) |
| 244 | #define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT U(16) |
| 245 | #define SCRATCH_BL31_PLAT_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_HI |
Steven Kao | 4607f17 | 2017-10-23 18:35:14 +0800 | [diff] [blame] | 246 | #define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97 |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 247 | #define SCRATCH_MC_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO |
| 248 | #define SCRATCH_MC_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI |
Steven Kao | 4607f17 | 2017-10-23 18:35:14 +0800 | [diff] [blame] | 249 | #define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO |
| 250 | #define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 251 | |
| 252 | /******************************************************************************* |
| 253 | * Tegra Memory Mapped Control Register Access Bus constants |
| 254 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 255 | #define TEGRA_MMCRAB_BASE U(0x0E000000) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 256 | |
| 257 | /******************************************************************************* |
| 258 | * Tegra SMMU Controller constants |
| 259 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 260 | #define TEGRA_SMMU0_BASE U(0x12000000) |
| 261 | #define TEGRA_SMMU1_BASE U(0x11000000) |
| 262 | #define TEGRA_SMMU2_BASE U(0x10000000) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 263 | |
| 264 | /******************************************************************************* |
| 265 | * Tegra TZRAM constants |
| 266 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 267 | #define TEGRA_TZRAM_BASE U(0x40000000) |
| 268 | #define TEGRA_TZRAM_SIZE U(0x40000) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 269 | |
| 270 | /******************************************************************************* |
steven kao | e579606 | 2018-01-02 19:09:04 -0800 | [diff] [blame] | 271 | * Tegra CCPLEX-BPMP IPC constants |
| 272 | ******************************************************************************/ |
| 273 | #define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x4004C000) |
| 274 | #define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x4004D000) |
| 275 | #define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */ |
| 276 | |
| 277 | /******************************************************************************* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 278 | * Tegra Clock and Reset Controller constants |
| 279 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 280 | #define TEGRA_CAR_RESET_BASE U(0x20000000) |
Jeetesh Burman | 0f174f1 | 2018-01-22 16:52:11 +0530 | [diff] [blame] | 281 | #define TEGRA_GPU_RESET_REG_OFFSET U(0x18) |
| 282 | #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x1C) |
| 283 | #define GPU_RESET_BIT (U(1) << 0) |
| 284 | #define GPU_SET_BIT (U(1) << 0) |
Varun Wadekar | 602cf7e | 2018-04-03 13:10:48 -0700 | [diff] [blame] | 285 | #define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004) |
| 286 | #define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 287 | |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 288 | /******************************************************************************* |
Varun Wadekar | 1b0c124 | 2018-05-15 11:24:59 -0700 | [diff] [blame] | 289 | * Tegra DRAM memory base address |
| 290 | ******************************************************************************/ |
| 291 | #define TEGRA_DRAM_BASE ULL(0x80000000) |
| 292 | #define TEGRA_DRAM_END ULL(0xFFFFFFFFF) |
| 293 | |
| 294 | /******************************************************************************* |
Ajay Gupta | 8162109 | 2017-08-01 15:53:04 -0700 | [diff] [blame] | 295 | * XUSB STREAMIDs |
| 296 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 297 | #define TEGRA_SID_XUSB_HOST U(0x1b) |
| 298 | #define TEGRA_SID_XUSB_DEV U(0x1c) |
| 299 | #define TEGRA_SID_XUSB_VF0 U(0x5d) |
| 300 | #define TEGRA_SID_XUSB_VF1 U(0x5e) |
| 301 | #define TEGRA_SID_XUSB_VF2 U(0x5f) |
| 302 | #define TEGRA_SID_XUSB_VF3 U(0x60) |
Ajay Gupta | 8162109 | 2017-08-01 15:53:04 -0700 | [diff] [blame] | 303 | |
Kalyani Chidambaram Vaidyanathan | 3118cbf | 2019-10-02 13:57:23 -0700 | [diff] [blame] | 304 | /******************************************************************************* |
| 305 | * SCR addresses and expected settings |
| 306 | ******************************************************************************/ |
| 307 | #define SCRATCH_RSV68_SCR U(0x0C398110) |
| 308 | #define SCRATCH_RSV68_SCR_VAL U(0x38000101) |
| 309 | #define SCRATCH_RSV71_SCR U(0x0C39811C) |
| 310 | #define SCRATCH_RSV71_SCR_VAL U(0x38000101) |
| 311 | #define SCRATCH_RSV72_SCR U(0x0C398120) |
| 312 | #define SCRATCH_RSV72_SCR_VAL U(0x38000101) |
| 313 | #define SCRATCH_RSV75_SCR U(0x0C39812C) |
| 314 | #define SCRATCH_RSV75_SCR_VAL U(0x3A000005) |
| 315 | #define SCRATCH_RSV81_SCR U(0x0C398144) |
| 316 | #define SCRATCH_RSV81_SCR_VAL U(0x3A000105) |
| 317 | #define SCRATCH_RSV97_SCR U(0x0C398184) |
| 318 | #define SCRATCH_RSV97_SCR_VAL U(0x38000101) |
| 319 | #define SCRATCH_RSV99_SCR U(0x0C39818C) |
| 320 | #define SCRATCH_RSV99_SCR_VAL U(0x38000101) |
| 321 | #define SCRATCH_RSV109_SCR U(0x0C3981B4) |
| 322 | #define SCRATCH_RSV109_SCR_VAL U(0x38000101) |
| 323 | #define MISCREG_SCR_SCRTZWELCK U(0x00109000) |
| 324 | #define MISCREG_SCR_SCRTZWELCK_VAL U(0x30000100) |
| 325 | |
Varun Wadekar | 2909fa3 | 2020-01-09 08:52:10 -0800 | [diff] [blame] | 326 | #endif /* TEGRA_DEF_H */ |