Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 1 | /* |
Manish V Badarkhe | b65ae4e | 2022-12-12 10:14:25 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <drivers/arm/tzc400.h> |
| 11 | #include <lib/utils_def.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 12 | #include <plat/arm/board/common/v2m_def.h> |
| 13 | #include <plat/arm/common/arm_def.h> |
| 14 | #include <plat/arm/common/arm_spm_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 15 | #include <plat/common/common_def.h> |
| 16 | |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 17 | #include "../fvp_def.h" |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 18 | |
Govindraj Raja | a77c161 | 2023-02-08 15:04:55 +0000 | [diff] [blame] | 19 | #if TRUSTED_BOARD_BOOT |
| 20 | #include MBEDTLS_CONFIG_FILE |
| 21 | #endif |
| 22 | |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 23 | /* Required platform porting definitions */ |
Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 24 | #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ |
| 25 | U(FVP_MAX_CPUS_PER_CLUSTER) * \ |
| 26 | U(FVP_MAX_PE_PER_CPU)) |
Jeenu Viswambharan | 528d21b | 2016-11-15 13:53:57 +0000 | [diff] [blame] | 27 | |
Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 28 | #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ |
| 29 | PLATFORM_CORE_COUNT + U(1)) |
Jeenu Viswambharan | 528d21b | 2016-11-15 13:53:57 +0000 | [diff] [blame] | 30 | |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 31 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 32 | |
Wing Li | 05364b9 | 2023-01-26 18:33:43 -0800 | [diff] [blame] | 33 | #if PSCI_OS_INIT_MODE |
| 34 | #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 |
| 35 | #endif |
| 36 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 37 | /* |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 38 | * Other platform porting definitions are provided by included headers |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 39 | */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 40 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 41 | /* |
| 42 | * Required ARM standard platform porting definitions |
| 43 | */ |
Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 44 | #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 45 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 46 | #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 47 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 48 | #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) |
| 49 | #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 50 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 51 | #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) |
| 52 | #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 53 | |
Zelalem Aweke | c43c563 | 2021-07-12 23:41:05 -0500 | [diff] [blame] | 54 | #if ENABLE_RME |
| 55 | #define PLAT_ARM_RMM_BASE (RMM_BASE) |
| 56 | #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) |
| 57 | #endif |
| 58 | |
Arunachalam Ganapathy | 40618cf | 2020-07-27 13:51:30 +0100 | [diff] [blame] | 59 | /* |
| 60 | * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to |
| 61 | * max size of BL32 image. |
| 62 | */ |
| 63 | #if defined(SPD_spmd) |
| 64 | #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE |
| 65 | #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ |
| 66 | #endif |
| 67 | |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 68 | /* virtual address used by dynamic mem_protect for chunk_base */ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 69 | #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 70 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 71 | /* No SCP in FVP */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 72 | #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 73 | |
Federico Recanati | fe09a42 | 2021-12-23 11:01:11 +0100 | [diff] [blame] | 74 | #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ |
| 75 | #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ |
| 76 | |
| 77 | #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ |
| 78 | #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ |
| 79 | #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) |
| 80 | |
| 81 | #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ |
| 82 | #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ |
| 83 | #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) |
| 84 | |
| 85 | #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ |
| 86 | #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ |
| 87 | #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) |
| 88 | |
| 89 | #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ |
| 90 | #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ |
| 91 | #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) |
Juan Castillo | d227d8b | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 92 | |
Zelalem Aweke | cb6b562 | 2021-07-26 21:28:42 -0500 | [diff] [blame] | 93 | /* Range of kernel DTB load address */ |
| 94 | #define FVP_DTB_DRAM_MAP_START ULL(0x82000000) |
Zelalem Aweke | 1e8e3fd | 2021-07-26 21:39:05 -0500 | [diff] [blame] | 95 | #define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */ |
Madhukar Pappireddy | aa1121f | 2020-03-13 13:00:17 -0500 | [diff] [blame] | 96 | |
Marc Bonnici | 6ba5abe | 2021-11-29 16:59:02 +0000 | [diff] [blame] | 97 | #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ |
| 98 | FVP_DTB_DRAM_MAP_START, \ |
| 99 | FVP_DTB_DRAM_MAP_SIZE, \ |
| 100 | MT_MEMORY | MT_RO | MT_NS) |
| 101 | |
| 102 | #if SPMC_AT_EL3 |
| 103 | /* |
| 104 | * Number of Secure Partitions supported. |
| 105 | * SPMC at EL3, uses this count to configure the maximum number of supported |
| 106 | * secure partitions. |
| 107 | */ |
| 108 | #define SECURE_PARTITION_COUNT 1 |
| 109 | |
| 110 | /* |
| 111 | * Number of Normal World Partitions supported. |
| 112 | * SPMC at EL3, uses this count to configure the maximum number of supported |
| 113 | * NWd partitions. |
| 114 | */ |
| 115 | #define NS_PARTITION_COUNT 1 |
| 116 | |
| 117 | /* |
| 118 | * Number of Logical Partitions supported. |
| 119 | * SPMC at EL3, uses this count to configure the maximum number of supported |
| 120 | * logical partitions. |
| 121 | */ |
| 122 | #define MAX_EL3_LP_DESCS_COUNT 1 |
| 123 | |
| 124 | #endif /* SPMC_AT_EL3 */ |
| 125 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 126 | /* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 127 | * Load address of BL33 for this platform port |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 128 | */ |
Sandrine Bailleux | afa91db | 2019-01-31 15:01:32 +0100 | [diff] [blame] | 129 | #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 130 | |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 131 | /* |
| 132 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 133 | * plat_arm_mmap array defined for each BL stage. |
| 134 | */ |
| 135 | #if defined(IMAGE_BL31) |
Paul Beesley | db4e25a | 2019-10-14 15:27:12 +0000 | [diff] [blame] | 136 | # if SPM_MM |
Madhukar Pappireddy | ae9677b | 2020-01-27 13:37:51 -0600 | [diff] [blame] | 137 | # define PLAT_ARM_MMAP_ENTRIES 10 |
Javier Almansa Sobrino | 7176a77 | 2021-11-24 18:37:37 +0000 | [diff] [blame] | 138 | # define MAX_XLAT_TABLES 9 |
Antonio Nino Diaz | 840627f | 2018-11-27 08:36:02 +0000 | [diff] [blame] | 139 | # define PLAT_SP_IMAGE_MMAP_REGIONS 30 |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 140 | # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 |
Marc Bonnici | 6ba5abe | 2021-11-29 16:59:02 +0000 | [diff] [blame] | 141 | # elif SPMC_AT_EL3 |
| 142 | # define PLAT_ARM_MMAP_ENTRIES 13 |
| 143 | # define MAX_XLAT_TABLES 11 |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 144 | # else |
Madhukar Pappireddy | ae9677b | 2020-01-27 13:37:51 -0600 | [diff] [blame] | 145 | # define PLAT_ARM_MMAP_ENTRIES 9 |
Ambroise Vincent | 9660dc1 | 2019-07-12 13:47:03 +0100 | [diff] [blame] | 146 | # if USE_DEBUGFS |
Zelalem Aweke | c43c563 | 2021-07-12 23:41:05 -0500 | [diff] [blame] | 147 | # if ENABLE_RME |
Javier Almansa Sobrino | dea652e | 2022-04-13 17:57:35 +0100 | [diff] [blame] | 148 | # define MAX_XLAT_TABLES 9 |
Zelalem Aweke | c43c563 | 2021-07-12 23:41:05 -0500 | [diff] [blame] | 149 | # else |
| 150 | # define MAX_XLAT_TABLES 8 |
| 151 | # endif |
Ambroise Vincent | 9660dc1 | 2019-07-12 13:47:03 +0100 | [diff] [blame] | 152 | # else |
Zelalem Aweke | c43c563 | 2021-07-12 23:41:05 -0500 | [diff] [blame] | 153 | # if ENABLE_RME |
Javier Almansa Sobrino | dea652e | 2022-04-13 17:57:35 +0100 | [diff] [blame] | 154 | # define MAX_XLAT_TABLES 8 |
Manish V Badarkhe | dd9455f | 2022-02-23 09:47:59 +0000 | [diff] [blame] | 155 | # elif DRTM_SUPPORT |
| 156 | # define MAX_XLAT_TABLES 8 |
Zelalem Aweke | c43c563 | 2021-07-12 23:41:05 -0500 | [diff] [blame] | 157 | # else |
| 158 | # define MAX_XLAT_TABLES 7 |
| 159 | # endif |
Ambroise Vincent | 9660dc1 | 2019-07-12 13:47:03 +0100 | [diff] [blame] | 160 | # endif |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 161 | # endif |
| 162 | #elif defined(IMAGE_BL32) |
Marc Bonnici | 6ba5abe | 2021-11-29 16:59:02 +0000 | [diff] [blame] | 163 | # if SPMC_AT_EL3 |
| 164 | # define PLAT_ARM_MMAP_ENTRIES 270 |
| 165 | # define MAX_XLAT_TABLES 10 |
| 166 | # else |
| 167 | # define PLAT_ARM_MMAP_ENTRIES 9 |
| 168 | # define MAX_XLAT_TABLES 6 |
| 169 | # endif |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 170 | #elif !USE_ROMLIB |
| 171 | # define PLAT_ARM_MMAP_ENTRIES 11 |
| 172 | # define MAX_XLAT_TABLES 5 |
| 173 | #else |
| 174 | # define PLAT_ARM_MMAP_ENTRIES 12 |
Manish V Badarkhe | b65ae4e | 2022-12-12 10:14:25 +0000 | [diff] [blame] | 175 | # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ |
| 176 | defined(IMAGE_BL2) && MEASURED_BOOT |
| 177 | # define MAX_XLAT_TABLES 7 |
| 178 | # else |
| 179 | # define MAX_XLAT_TABLES 6 |
| 180 | # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 181 | #endif |
| 182 | |
| 183 | /* |
| 184 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 185 | * plus a little space for growth. |
| 186 | */ |
Govindraj Raja | a77c161 | 2023-02-08 15:04:55 +0000 | [diff] [blame] | 187 | #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA |
| 188 | #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) |
| 189 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 190 | #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) |
Govindraj Raja | a77c161 | 2023-02-08 15:04:55 +0000 | [diff] [blame] | 191 | #endif |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 192 | |
| 193 | /* |
| 194 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 195 | */ |
| 196 | |
| 197 | #if USE_ROMLIB |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 198 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) |
| 199 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) |
Manish V Badarkhe | dd6f252 | 2021-02-22 17:30:17 +0000 | [diff] [blame] | 200 | #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 201 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 202 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) |
| 203 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) |
Louis Mayencourt | 438aa72 | 2019-10-11 14:31:13 +0100 | [diff] [blame] | 204 | #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 205 | #endif |
| 206 | |
| 207 | /* |
| 208 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 209 | * little space for growth. |
| 210 | */ |
Govindraj Raja | 4e04b28 | 2023-02-12 20:36:02 +0000 | [diff] [blame] | 211 | #if CRYPTO_SUPPORT |
| 212 | #if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB |
Govindraj Raja | a77c161 | 2023-02-08 15:04:55 +0000 | [diff] [blame] | 213 | # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) |
| 214 | #else |
Louis Mayencourt | 438aa72 | 2019-10-11 14:31:13 +0100 | [diff] [blame] | 215 | # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) |
Govindraj Raja | a77c161 | 2023-02-08 15:04:55 +0000 | [diff] [blame] | 216 | #endif |
laurenw-arm | 698634a | 2022-06-08 16:50:42 -0500 | [diff] [blame] | 217 | #elif ARM_BL31_IN_DRAM |
| 218 | /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ |
| 219 | # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 220 | #else |
Manish V Badarkhe | 1856cc9 | 2020-07-10 09:44:21 +0100 | [diff] [blame] | 221 | # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 222 | #endif |
| 223 | |
Alexei Fedorov | ea0424f | 2020-02-17 13:38:35 +0000 | [diff] [blame] | 224 | #if RESET_TO_BL31 |
Zelalem Aweke | c43c563 | 2021-07-12 23:41:05 -0500 | [diff] [blame] | 225 | /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ |
Alexei Fedorov | ea0424f | 2020-02-17 13:38:35 +0000 | [diff] [blame] | 226 | #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ |
Zelalem Aweke | c43c563 | 2021-07-12 23:41:05 -0500 | [diff] [blame] | 227 | ARM_SHARED_RAM_SIZE - \ |
| 228 | ARM_L0_GPT_SIZE) |
Alexei Fedorov | ea0424f | 2020-02-17 13:38:35 +0000 | [diff] [blame] | 229 | #else |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 230 | /* |
| 231 | * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is |
| 232 | * calculated using the current BL31 PROGBITS debug size plus the sizes of |
| 233 | * BL2 and BL1-RW |
| 234 | */ |
Zelalem Aweke | c43c563 | 2021-07-12 23:41:05 -0500 | [diff] [blame] | 235 | #define PLAT_ARM_MAX_BL31_SIZE (UL(0x3D000) - ARM_L0_GPT_SIZE) |
Alexei Fedorov | ea0424f | 2020-02-17 13:38:35 +0000 | [diff] [blame] | 236 | #endif /* RESET_TO_BL31 */ |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 237 | |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 238 | #ifndef __aarch64__ |
Manish Pandey | 928da86 | 2021-06-10 15:22:48 +0100 | [diff] [blame] | 239 | #if RESET_TO_SP_MIN |
| 240 | /* Size of Trusted SRAM - the first 4KB of shared memory */ |
| 241 | #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ |
| 242 | ARM_SHARED_RAM_SIZE) |
| 243 | #else |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 244 | /* |
| 245 | * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is |
| 246 | * calculated using the current SP_MIN PROGBITS debug size plus the sizes of |
| 247 | * BL2 and BL1-RW |
| 248 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 249 | # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) |
Manish Pandey | 928da86 | 2021-06-10 15:22:48 +0100 | [diff] [blame] | 250 | #endif /* RESET_TO_SP_MIN */ |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 251 | #endif |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 252 | |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 253 | /* |
| 254 | * Size of cacheable stacks |
| 255 | */ |
| 256 | #if defined(IMAGE_BL1) |
Manish V Badarkhe | eba13bd | 2022-01-08 23:08:02 +0000 | [diff] [blame] | 257 | # if CRYPTO_SUPPORT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 258 | # define PLATFORM_STACK_SIZE UL(0x1000) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 259 | # else |
Louis Mayencourt | 2cef2d3 | 2020-01-17 16:10:45 +0000 | [diff] [blame] | 260 | # define PLATFORM_STACK_SIZE UL(0x500) |
Manish V Badarkhe | eba13bd | 2022-01-08 23:08:02 +0000 | [diff] [blame] | 261 | # endif /* CRYPTO_SUPPORT */ |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 262 | #elif defined(IMAGE_BL2) |
Manish V Badarkhe | eba13bd | 2022-01-08 23:08:02 +0000 | [diff] [blame] | 263 | # if CRYPTO_SUPPORT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 264 | # define PLATFORM_STACK_SIZE UL(0x1000) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 265 | # else |
Soby Mathew | ea4195d | 2021-06-18 12:25:35 +0100 | [diff] [blame] | 266 | # define PLATFORM_STACK_SIZE UL(0x600) |
Manish V Badarkhe | eba13bd | 2022-01-08 23:08:02 +0000 | [diff] [blame] | 267 | # endif /* CRYPTO_SUPPORT */ |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 268 | #elif defined(IMAGE_BL2U) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 269 | # define PLATFORM_STACK_SIZE UL(0x400) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 270 | #elif defined(IMAGE_BL31) |
Lucian Paul-Trifu | fd0c8aa | 2022-02-23 09:34:45 +0000 | [diff] [blame] | 271 | # if DRTM_SUPPORT |
| 272 | # define PLATFORM_STACK_SIZE UL(0x1000) |
| 273 | # else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 274 | # define PLATFORM_STACK_SIZE UL(0x800) |
Lucian Paul-Trifu | fd0c8aa | 2022-02-23 09:34:45 +0000 | [diff] [blame] | 275 | # endif /* DRTM_SUPPORT */ |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 276 | #elif defined(IMAGE_BL32) |
Shruti Gupta | c31beb6 | 2022-08-09 10:46:07 +0100 | [diff] [blame] | 277 | # if SPMC_AT_EL3 |
| 278 | # define PLATFORM_STACK_SIZE UL(0x1000) |
| 279 | # else |
| 280 | # define PLATFORM_STACK_SIZE UL(0x440) |
| 281 | # endif /* SPMC_AT_EL3 */ |
Zelalem Aweke | 96c0bab | 2021-07-11 18:39:39 -0500 | [diff] [blame] | 282 | #elif defined(IMAGE_RMM) |
| 283 | # define PLATFORM_STACK_SIZE UL(0x440) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 284 | #endif |
| 285 | |
| 286 | #define MAX_IO_DEVICES 3 |
| 287 | #define MAX_IO_HANDLES 4 |
| 288 | |
| 289 | /* Reserve the last block of flash for PSCI MEM PROTECT flag */ |
Manish V Badarkhe | 443ccbc | 2021-04-22 11:13:21 +0100 | [diff] [blame] | 290 | #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE |
| 291 | #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 292 | |
Manish V Badarkhe | dd6f252 | 2021-02-22 17:30:17 +0000 | [diff] [blame] | 293 | #if ARM_GPT_SUPPORT |
| 294 | /* |
| 295 | * Offset of the FIP in the GPT image. BL1 component uses this option |
| 296 | * as it does not load the partition table to get the FIP base |
| 297 | * address. At sector 34 by default (i.e. after reserved sectors 0-33) |
| 298 | * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 |
| 299 | */ |
| 300 | #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 |
| 301 | #endif /* ARM_GPT_SUPPORT */ |
| 302 | |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 303 | #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE |
| 304 | #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 305 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 306 | /* |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 307 | * PL011 related constants |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 308 | */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 309 | #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE |
| 310 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 311 | |
Usama Arif | 81eb5ce | 2019-02-11 16:35:42 +0000 | [diff] [blame] | 312 | #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE |
| 313 | #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ |
Soby Mathew | 2fd66be | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 314 | |
Usama Arif | 81eb5ce | 2019-02-11 16:35:42 +0000 | [diff] [blame] | 315 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE |
| 316 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 317 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 318 | #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE |
| 319 | #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 320 | |
Zelalem Aweke | c8bc23e | 2021-07-09 15:32:21 -0500 | [diff] [blame] | 321 | #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE |
| 322 | #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ |
| 323 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 324 | #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) |
Olivier Deprez | 73ad731 | 2022-02-04 12:30:11 +0100 | [diff] [blame] | 325 | #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 326 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 327 | /* CCI related constants */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 328 | #define PLAT_FVP_CCI400_BASE UL(0x2c090000) |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 329 | #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 |
| 330 | #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 |
| 331 | |
| 332 | /* CCI-500/CCI-550 on Base platform */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 333 | #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 334 | #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 |
| 335 | #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 |
Juan Castillo | e33ee5f | 2014-12-19 09:51:00 +0000 | [diff] [blame] | 336 | |
Soby Mathew | 7356b1e | 2016-03-24 10:12:42 +0000 | [diff] [blame] | 337 | /* CCN related constants. Only CCN 502 is currently supported */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 338 | #define PLAT_ARM_CCN_BASE UL(0x2e000000) |
Soby Mathew | 7356b1e | 2016-03-24 10:12:42 +0000 | [diff] [blame] | 339 | #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 |
| 340 | |
Vikram Kanigiri | a2cee03 | 2015-07-31 16:35:05 +0100 | [diff] [blame] | 341 | /* System timer related constants */ |
Antonio Nino Diaz | 6971f00 | 2018-11-06 13:14:21 +0000 | [diff] [blame] | 342 | #define PLAT_ARM_NSTIMER_FRAME_ID U(1) |
Vikram Kanigiri | a2cee03 | 2015-07-31 16:35:05 +0100 | [diff] [blame] | 343 | |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 344 | /* Mailbox base address */ |
| 345 | #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE |
| 346 | |
| 347 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 348 | /* TrustZone controller related constants |
| 349 | * |
| 350 | * Currently only filters 0 and 2 are connected on Base FVP. |
| 351 | * Filter 0 : CPU clusters (no access to DRAM by default) |
| 352 | * Filter 1 : not connected |
| 353 | * Filter 2 : LCDs (access to VRAM allowed by default) |
| 354 | * Filter 3 : not connected |
| 355 | * Programming unconnected filters will have no effect at the |
| 356 | * moment. These filter could, however, be connected in future. |
| 357 | * So care should be taken not to configure the unused filters. |
| 358 | * |
| 359 | * Allow only non-secure access to all DRAM to supported devices. |
| 360 | * Give access to the CPUs and Virtio. Some devices |
| 361 | * would normally use the default ID so allow that too. |
| 362 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 363 | #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) |
Soby Mathew | 9c708b5 | 2016-02-26 14:23:19 +0000 | [diff] [blame] | 364 | #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 365 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 366 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 367 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ |
| 368 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ |
| 369 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ |
| 370 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ |
| 371 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 372 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 373 | /* |
| 374 | * GIC related constants to cater for both GICv2 and GICv3 instances of an |
Alexei Fedorov | 61369a2 | 2020-07-13 14:59:02 +0100 | [diff] [blame] | 375 | * FVP. They could be overridden at runtime in case the FVP implements the |
| 376 | * legacy VE memory map. |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 377 | */ |
| 378 | #define PLAT_ARM_GICD_BASE BASE_GICD_BASE |
| 379 | #define PLAT_ARM_GICR_BASE BASE_GICR_BASE |
| 380 | #define PLAT_ARM_GICC_BASE BASE_GICC_BASE |
| 381 | |
| 382 | /* |
| 383 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 384 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 385 | * as Group 0 interrupts. |
| 386 | */ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 387 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 388 | ARM_G1S_IRQ_PROPS(grp), \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 389 | INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 390 | GIC_INTR_CFG_LEVEL), \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 391 | INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 392 | GIC_INTR_CFG_LEVEL) |
| 393 | |
| 394 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 395 | |
Balint Dobszay | d0dbd5e | 2019-12-18 15:28:00 +0100 | [diff] [blame] | 396 | #if SDEI_IN_FCONF |
| 397 | #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT |
| 398 | #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT |
| 399 | #else |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 400 | #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS |
| 401 | #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS |
Balint Dobszay | d0dbd5e | 2019-12-18 15:28:00 +0100 | [diff] [blame] | 402 | #endif |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 403 | |
Ard Biesheuvel | 8b034fc | 2018-12-29 19:43:21 +0100 | [diff] [blame] | 404 | #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ |
| 405 | PLAT_SP_IMAGE_NS_BUF_SIZE) |
Sughosh Ganu | 5f21294 | 2018-05-16 15:35:25 +0530 | [diff] [blame] | 406 | |
Sughosh Ganu | d284b57 | 2018-11-14 10:42:46 +0530 | [diff] [blame] | 407 | #define PLAT_SP_PRI PLAT_RAS_PRI |
| 408 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 409 | /* |
| 410 | * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes |
| 411 | */ |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 412 | #ifdef __aarch64__ |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 413 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) |
| 414 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) |
| 415 | #else |
| 416 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 417 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 418 | #endif |
| 419 | |
Manish V Badarkhe | 7ca9d65 | 2021-09-14 22:41:46 +0100 | [diff] [blame] | 420 | /* |
| 421 | * Maximum size of Event Log buffer used in Measured Boot Event Log driver |
| 422 | */ |
| 423 | #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) |
| 424 | |
johpow01 | baa3e6c | 2022-03-11 17:50:58 -0600 | [diff] [blame] | 425 | /* |
| 426 | * Maximum size of Event Log buffer used for DRTM |
| 427 | */ |
| 428 | #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) |
| 429 | |
| 430 | /* |
| 431 | * Number of MMAP entries used by DRTM implementation |
| 432 | */ |
| 433 | #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES |
| 434 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 435 | #endif /* PLATFORM_DEF_H */ |