Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 1 | /* |
annsai01 | 7c607f2 | 2023-02-20 13:34:57 +0000 | [diff] [blame] | 2 | * Copyright (c) 2020-2024, Arm Limited. All rights reserved. |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | |
Kshitij Sisodia | b32a8f4 | 2023-08-16 09:46:05 +0100 | [diff] [blame^] | 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 10 | #include <dt-bindings/interrupt-controller/irq.h> |
| 11 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 12 | / { |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 13 | compatible = "arm,tc"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 14 | interrupt-parent = <&gic>; |
| 15 | #address-cells = <2>; |
| 16 | #size-cells = <2>; |
| 17 | |
| 18 | aliases { |
annsai01 | 7c607f2 | 2023-02-20 13:34:57 +0000 | [diff] [blame] | 19 | serial0 = &ap_ns_uart; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 20 | }; |
| 21 | |
| 22 | chosen { |
Nikos Nikoleris | 35800bd | 2021-01-21 13:50:25 +0000 | [diff] [blame] | 23 | stdout-path = "serial0:115200n8"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 24 | }; |
| 25 | |
| 26 | cpus { |
| 27 | #address-cells = <1>; |
| 28 | #size-cells = <0>; |
| 29 | |
| 30 | cpu-map { |
| 31 | cluster0 { |
| 32 | core0 { |
| 33 | cpu = <&CPU0>; |
| 34 | }; |
| 35 | core1 { |
| 36 | cpu = <&CPU1>; |
| 37 | }; |
| 38 | core2 { |
| 39 | cpu = <&CPU2>; |
| 40 | }; |
| 41 | core3 { |
| 42 | cpu = <&CPU3>; |
| 43 | }; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 44 | core4 { |
| 45 | cpu = <&CPU4>; |
| 46 | }; |
| 47 | core5 { |
| 48 | cpu = <&CPU5>; |
| 49 | }; |
| 50 | core6 { |
| 51 | cpu = <&CPU6>; |
| 52 | }; |
| 53 | core7 { |
| 54 | cpu = <&CPU7>; |
| 55 | }; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 56 | }; |
| 57 | }; |
| 58 | |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 59 | /* |
| 60 | * The timings below are just to demonstrate working cpuidle. |
| 61 | * These values may be inaccurate. |
| 62 | */ |
| 63 | idle-states { |
| 64 | entry-method = "arm,psci"; |
| 65 | |
| 66 | CPU_SLEEP_0: cpu-sleep-0 { |
| 67 | compatible = "arm,idle-state"; |
| 68 | arm,psci-suspend-param = <0x0010000>; |
| 69 | local-timer-stop; |
| 70 | entry-latency-us = <300>; |
| 71 | exit-latency-us = <1200>; |
| 72 | min-residency-us = <2000>; |
| 73 | }; |
| 74 | CLUSTER_SLEEP_0: cluster-sleep-0 { |
| 75 | compatible = "arm,idle-state"; |
| 76 | arm,psci-suspend-param = <0x1010000>; |
| 77 | local-timer-stop; |
| 78 | entry-latency-us = <400>; |
| 79 | exit-latency-us = <1200>; |
| 80 | min-residency-us = <2500>; |
| 81 | }; |
| 82 | }; |
| 83 | |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 84 | amus { |
| 85 | amu: amu-0 { |
| 86 | #address-cells = <1>; |
| 87 | #size-cells = <0>; |
| 88 | |
| 89 | mpmm_gear0: counter@0 { |
| 90 | reg = <0>; |
| 91 | |
| 92 | enable-at-el3; |
| 93 | }; |
| 94 | |
| 95 | mpmm_gear1: counter@1 { |
| 96 | reg = <1>; |
| 97 | |
| 98 | enable-at-el3; |
| 99 | }; |
| 100 | |
| 101 | mpmm_gear2: counter@2 { |
| 102 | reg = <2>; |
| 103 | |
| 104 | enable-at-el3; |
| 105 | }; |
| 106 | }; |
| 107 | }; |
| 108 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 109 | CPU0:cpu@0 { |
| 110 | device_type = "cpu"; |
| 111 | compatible = "arm,armv8"; |
| 112 | reg = <0x0>; |
| 113 | enable-method = "psci"; |
| 114 | clocks = <&scmi_dvfs 0>; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 115 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 116 | capacity-dmips-mhz = <406>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 117 | amu = <&amu>; |
| 118 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 119 | }; |
| 120 | |
| 121 | CPU1:cpu@100 { |
| 122 | device_type = "cpu"; |
| 123 | compatible = "arm,armv8"; |
| 124 | reg = <0x100>; |
| 125 | enable-method = "psci"; |
| 126 | clocks = <&scmi_dvfs 0>; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 127 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 128 | capacity-dmips-mhz = <406>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 129 | amu = <&amu>; |
| 130 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 131 | }; |
| 132 | |
| 133 | CPU2:cpu@200 { |
| 134 | device_type = "cpu"; |
| 135 | compatible = "arm,armv8"; |
| 136 | reg = <0x200>; |
| 137 | enable-method = "psci"; |
| 138 | clocks = <&scmi_dvfs 0>; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 139 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 140 | capacity-dmips-mhz = <406>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 141 | amu = <&amu>; |
| 142 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 143 | }; |
| 144 | |
| 145 | CPU3:cpu@300 { |
| 146 | device_type = "cpu"; |
| 147 | compatible = "arm,armv8"; |
| 148 | reg = <0x300>; |
| 149 | enable-method = "psci"; |
| 150 | clocks = <&scmi_dvfs 0>; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 151 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 152 | capacity-dmips-mhz = <406>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 153 | amu = <&amu>; |
| 154 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 155 | }; |
| 156 | |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 157 | CPU4:cpu@400 { |
| 158 | device_type = "cpu"; |
| 159 | compatible = "arm,armv8"; |
| 160 | reg = <0x400>; |
| 161 | enable-method = "psci"; |
Usama Arif | 75edb75 | 2021-02-03 15:40:46 +0000 | [diff] [blame] | 162 | clocks = <&scmi_dvfs 1>; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 163 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 164 | capacity-dmips-mhz = <912>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 165 | amu = <&amu>; |
| 166 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 167 | }; |
| 168 | |
| 169 | CPU5:cpu@500 { |
| 170 | device_type = "cpu"; |
| 171 | compatible = "arm,armv8"; |
| 172 | reg = <0x500>; |
| 173 | enable-method = "psci"; |
Usama Arif | 75edb75 | 2021-02-03 15:40:46 +0000 | [diff] [blame] | 174 | clocks = <&scmi_dvfs 1>; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 175 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 176 | capacity-dmips-mhz = <912>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 177 | amu = <&amu>; |
| 178 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 179 | }; |
| 180 | |
| 181 | CPU6:cpu@600 { |
| 182 | device_type = "cpu"; |
| 183 | compatible = "arm,armv8"; |
| 184 | reg = <0x600>; |
| 185 | enable-method = "psci"; |
Usama Arif | 75edb75 | 2021-02-03 15:40:46 +0000 | [diff] [blame] | 186 | clocks = <&scmi_dvfs 1>; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 187 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 188 | capacity-dmips-mhz = <912>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 189 | amu = <&amu>; |
| 190 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 191 | }; |
| 192 | |
| 193 | CPU7:cpu@700 { |
| 194 | device_type = "cpu"; |
| 195 | compatible = "arm,armv8"; |
| 196 | reg = <0x700>; |
| 197 | enable-method = "psci"; |
Usama Arif | 410d50d | 2021-04-07 11:48:22 +0100 | [diff] [blame] | 198 | clocks = <&scmi_dvfs 2>; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 199 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 200 | capacity-dmips-mhz = <1024>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 201 | amu = <&amu>; |
| 202 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 203 | }; |
| 204 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 205 | }; |
| 206 | |
Arunachalam Ganapathy | 948bb44 | 2020-12-14 12:31:32 +0000 | [diff] [blame] | 207 | reserved-memory { |
| 208 | #address-cells = <2>; |
| 209 | #size-cells = <2>; |
| 210 | ranges; |
| 211 | |
Anders Dellien | a6c9b72 | 2021-12-08 21:57:21 +0000 | [diff] [blame] | 212 | linux,cma { |
| 213 | compatible = "shared-dma-pool"; |
| 214 | reusable; |
| 215 | size = <0x0 0x8000000>; |
| 216 | linux,cma-default; |
| 217 | }; |
| 218 | |
Arunachalam Ganapathy | ac9e120 | 2022-04-11 17:38:17 +0100 | [diff] [blame] | 219 | optee@0xf8e00000 { |
Davidson K | 4662a88 | 2022-12-14 17:38:14 +0530 | [diff] [blame] | 220 | compatible = "restricted-dma-pool"; |
Arunachalam Ganapathy | ac9e120 | 2022-04-11 17:38:17 +0100 | [diff] [blame] | 221 | reg = <0x00000000 0xf8e00000 0 0x00200000>; |
Arunachalam Ganapathy | 948bb44 | 2020-12-14 12:31:32 +0000 | [diff] [blame] | 222 | }; |
| 223 | }; |
| 224 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 225 | psci { |
Usama Arif | 7a64bfa | 2021-05-27 20:09:17 +0100 | [diff] [blame] | 226 | compatible = "arm,psci-1.0", "arm,psci-0.2"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 227 | method = "smc"; |
| 228 | }; |
| 229 | |
| 230 | sram: sram@6000000 { |
| 231 | compatible = "mmio-sram"; |
| 232 | reg = <0x0 0x06000000 0x0 0x8000>; |
| 233 | |
| 234 | #address-cells = <1>; |
| 235 | #size-cells = <1>; |
| 236 | ranges = <0 0x0 0x06000000 0x8000>; |
| 237 | |
| 238 | cpu_scp_scmi_mem: scp-shmem@0 { |
| 239 | compatible = "arm,scmi-shmem"; |
| 240 | reg = <0x0 0x80>; |
| 241 | }; |
| 242 | }; |
| 243 | |
| 244 | mbox_db_rx: mhu@45010000 { |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 245 | compatible = "arm,mhuv2-rx","arm,primecell"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 246 | reg = <0x0 0x45010000 0x0 0x1000>; |
| 247 | clocks = <&soc_refclk100mhz>; |
| 248 | clock-names = "apb_pclk"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 249 | #mbox-cells = <2>; |
Usama Arif | 884f40d | 2020-08-18 12:56:44 +0100 | [diff] [blame] | 250 | interrupts = <0 317 4>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 251 | interrupt-names = "mhu_rx"; |
| 252 | mhu-protocol = "doorbell"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 253 | arm,mhuv2-protocols = <0 1>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 254 | }; |
| 255 | |
| 256 | mbox_db_tx: mhu@45000000 { |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 257 | compatible = "arm,mhuv2-tx","arm,primecell"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 258 | reg = <0x0 0x45000000 0x0 0x1000>; |
| 259 | clocks = <&soc_refclk100mhz>; |
| 260 | clock-names = "apb_pclk"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 261 | #mbox-cells = <2>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 262 | interrupt-names = "mhu_tx"; |
| 263 | mhu-protocol = "doorbell"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 264 | arm,mhuv2-protocols = <0 1>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 265 | }; |
| 266 | |
Rupinderjit Singh | 8c90196 | 2022-02-22 21:50:33 +0000 | [diff] [blame] | 267 | cmn-pmu { |
| 268 | compatible = "arm,ci-700"; |
| 269 | reg = <0x0 0x50000000 0x0 0x10000000>; |
| 270 | interrupts = <0x0 460 0x4>; |
| 271 | }; |
| 272 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 273 | scmi { |
| 274 | compatible = "arm,scmi"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 275 | mbox-names = "tx", "rx"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 276 | mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 277 | shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>; |
| 278 | #address-cells = <1>; |
| 279 | #size-cells = <0>; |
| 280 | |
Ben Horgan | 80781a5 | 2023-07-26 20:45:27 +0100 | [diff] [blame] | 281 | scmi_devpd: protocol@11 { |
| 282 | reg = <0x11>; |
| 283 | #power-domain-cells = <1>; |
| 284 | }; |
| 285 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 286 | scmi_dvfs: protocol@13 { |
| 287 | reg = <0x13>; |
| 288 | #clock-cells = <1>; |
| 289 | }; |
| 290 | |
| 291 | scmi_clk: protocol@14 { |
| 292 | reg = <0x14>; |
| 293 | #clock-cells = <1>; |
| 294 | }; |
| 295 | }; |
| 296 | |
| 297 | gic: interrupt-controller@2c010000 { |
| 298 | compatible = "arm,gic-600", "arm,gic-v3"; |
| 299 | #address-cells = <2>; |
| 300 | #interrupt-cells = <3>; |
| 301 | #size-cells = <2>; |
| 302 | ranges; |
| 303 | interrupt-controller; |
| 304 | reg = <0x0 0x30000000 0 0x10000>, /* GICD */ |
Usama Arif | fdfd250 | 2021-03-30 16:39:19 +0100 | [diff] [blame] | 305 | <0x0 0x30080000 0 0x200000>; /* GICR */ |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 306 | interrupts = <0x1 0x9 0x4>; |
| 307 | }; |
| 308 | |
| 309 | timer { |
| 310 | compatible = "arm,armv8-timer"; |
| 311 | interrupts = <0x1 13 0x8>, |
| 312 | <0x1 14 0x8>, |
| 313 | <0x1 11 0x8>, |
| 314 | <0x1 10 0x8>; |
| 315 | }; |
| 316 | |
| 317 | soc_refclk100mhz: refclk100mhz { |
| 318 | compatible = "fixed-clock"; |
| 319 | #clock-cells = <0>; |
| 320 | clock-frequency = <100000000>; |
| 321 | clock-output-names = "apb_pclk"; |
| 322 | }; |
| 323 | |
| 324 | soc_refclk60mhz: refclk60mhz { |
| 325 | compatible = "fixed-clock"; |
| 326 | #clock-cells = <0>; |
| 327 | clock-frequency = <60000000>; |
| 328 | clock-output-names = "iofpga_clk"; |
| 329 | }; |
| 330 | |
| 331 | soc_uartclk: uartclk { |
| 332 | compatible = "fixed-clock"; |
| 333 | #clock-cells = <0>; |
| 334 | clock-frequency = <50000000>; |
| 335 | clock-output-names = "uartclk"; |
| 336 | }; |
| 337 | |
annsai01 | 7c607f2 | 2023-02-20 13:34:57 +0000 | [diff] [blame] | 338 | ap_ns_uart: uart@2A400000 { |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 339 | compatible = "arm,pl011", "arm,primecell"; |
annsai01 | 7c607f2 | 2023-02-20 13:34:57 +0000 | [diff] [blame] | 340 | reg = <0x0 0x2A400000 0x0 0x1000>; |
| 341 | interrupts = <0x0 63 0x4>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 342 | clocks = <&soc_uartclk>, <&soc_refclk100mhz>; |
| 343 | clock-names = "uartclk", "apb_pclk"; |
| 344 | status = "okay"; |
| 345 | }; |
| 346 | |
Jayanth Dodderi Chidanand | 2858cf5 | 2022-09-28 11:41:48 +0100 | [diff] [blame] | 347 | rtc0: rtc@1C170000 { |
| 348 | compatible = "arm,pl031", "arm,primecell"; |
| 349 | reg = <0x0 0x1C170000 0x0 0x1000>; |
| 350 | interrupts = <0x0 100 0x4>; |
| 351 | clocks = <&soc_refclk100mhz>; |
| 352 | clock-names = "apb_pclk"; |
| 353 | wakeup-source; |
| 354 | }; |
Rupinderjit Singh | d2d0298 | 2022-09-12 17:25:32 +0100 | [diff] [blame] | 355 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 356 | vencoder { |
| 357 | compatible = "drm,virtual-encoder"; |
| 358 | |
| 359 | port { |
| 360 | vencoder_in: endpoint { |
Avinash Mehta | df71a60 | 2020-07-22 16:40:07 +0100 | [diff] [blame] | 361 | remote-endpoint = <&dp_pl0_out0>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 362 | }; |
| 363 | }; |
| 364 | |
| 365 | display-timings { |
| 366 | panel-timing { |
| 367 | clock-frequency = <25175000>; |
| 368 | hactive = <640>; |
| 369 | vactive = <480>; |
| 370 | hfront-porch = <16>; |
| 371 | hback-porch = <48>; |
| 372 | hsync-len = <96>; |
| 373 | vfront-porch = <10>; |
| 374 | vback-porch = <33>; |
| 375 | vsync-len = <2>; |
| 376 | }; |
| 377 | }; |
| 378 | |
| 379 | }; |
| 380 | |
| 381 | hdlcd: hdlcd@7ff60000 { |
| 382 | compatible = "arm,hdlcd"; |
| 383 | reg = <0x0 0x7ff60000 0x0 0x1000>; |
| 384 | interrupts = <0x0 117 0x4>; |
| 385 | clocks = <&fake_hdlcd_clk>; |
| 386 | clock-names = "pxlclk"; |
Avinash Mehta | df71a60 | 2020-07-22 16:40:07 +0100 | [diff] [blame] | 387 | status = "disabled"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 388 | |
| 389 | port { |
| 390 | hdlcd_out: endpoint { |
| 391 | remote-endpoint = <&vencoder_in>; |
| 392 | }; |
| 393 | }; |
| 394 | }; |
| 395 | |
| 396 | fake_hdlcd_clk: fake-hdlcd-clk { |
| 397 | compatible = "fixed-clock"; |
| 398 | #clock-cells = <0>; |
| 399 | clock-frequency = <25175000>; |
| 400 | clock-output-names = "pxlclk"; |
| 401 | }; |
| 402 | |
| 403 | ethernet@18000000 { |
| 404 | compatible = "smsc,lan91c111"; |
| 405 | reg = <0x0 0x18000000 0x0 0x10000>; |
| 406 | interrupts = <0 109 4>; |
| 407 | }; |
| 408 | |
| 409 | kmi@1c060000 { |
| 410 | compatible = "arm,pl050", "arm,primecell"; |
| 411 | reg = <0x0 0x001c060000 0x0 0x1000>; |
| 412 | interrupts = <0 197 4>; |
| 413 | clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; |
| 414 | clock-names = "KMIREFCLK", "apb_pclk"; |
| 415 | }; |
| 416 | |
| 417 | kmi@1c070000 { |
| 418 | compatible = "arm,pl050", "arm,primecell"; |
| 419 | reg = <0x0 0x001c070000 0x0 0x1000>; |
| 420 | interrupts = <0 103 4>; |
| 421 | clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; |
| 422 | clock-names = "KMIREFCLK", "apb_pclk"; |
| 423 | }; |
| 424 | |
| 425 | bp_clock24mhz: clock24mhz { |
| 426 | compatible = "fixed-clock"; |
| 427 | #clock-cells = <0>; |
| 428 | clock-frequency = <24000000>; |
| 429 | clock-output-names = "bp:clock24mhz"; |
| 430 | }; |
| 431 | |
| 432 | virtio_block@1c130000 { |
| 433 | compatible = "virtio,mmio"; |
| 434 | reg = <0x0 0x1c130000 0x0 0x200>; |
| 435 | interrupts = <0 204 4>; |
| 436 | }; |
| 437 | |
Usama Arif | 1cd56dc | 2020-06-10 16:27:53 +0100 | [diff] [blame] | 438 | sysreg: sysreg@1c010000 { |
| 439 | compatible = "arm,vexpress-sysreg"; |
| 440 | reg = <0x0 0x001c010000 0x0 0x1000>; |
| 441 | gpio-controller; |
| 442 | #gpio-cells = <2>; |
| 443 | }; |
| 444 | |
| 445 | fixed_3v3: v2m-3v3 { |
| 446 | compatible = "regulator-fixed"; |
| 447 | regulator-name = "3V3"; |
| 448 | regulator-min-microvolt = <3300000>; |
| 449 | regulator-max-microvolt = <3300000>; |
| 450 | regulator-always-on; |
| 451 | }; |
| 452 | |
| 453 | mmci@1c050000 { |
| 454 | compatible = "arm,pl180", "arm,primecell"; |
| 455 | reg = <0x0 0x001c050000 0x0 0x1000>; |
| 456 | interrupts = <0 107 0x4>, |
| 457 | <0 108 0x4>; |
| 458 | cd-gpios = <&sysreg 0 0>; |
| 459 | wp-gpios = <&sysreg 1 0>; |
| 460 | bus-width = <8>; |
| 461 | max-frequency = <12000000>; |
| 462 | vmmc-supply = <&fixed_3v3>; |
| 463 | clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; |
| 464 | clock-names = "mclk", "apb_pclk"; |
| 465 | }; |
| 466 | |
Rupinderjit Singh | b2a75b8 | 2023-02-03 09:29:57 +0000 | [diff] [blame] | 467 | gpu_clk: gpu_clk { |
| 468 | compatible = "fixed-clock"; |
| 469 | #clock-cells = <0>; |
| 470 | clock-frequency = <1000000000>; |
| 471 | }; |
| 472 | |
| 473 | gpu_core_clk: gpu_core_clk { |
| 474 | compatible = "fixed-clock"; |
| 475 | #clock-cells = <0>; |
| 476 | clock-frequency = <1000000000>; |
| 477 | }; |
| 478 | |
Anders Dellien | 7a84980 | 2022-01-01 21:51:21 +0000 | [diff] [blame] | 479 | gpu: gpu@2d000000 { |
| 480 | compatible = "arm,mali-midgard"; |
| 481 | reg = <0x0 0x2d000000 0x0 0x200000>; |
| 482 | interrupts = <0 66 4>, <0 67 4>, <0 65 4>; |
| 483 | interrupt-names = "JOB", "MMU", "GPU"; |
Ben Horgan | 80781a5 | 2023-07-26 20:45:27 +0100 | [diff] [blame] | 484 | clocks = <&gpu_core_clk>; |
| 485 | clock-names = "shadercores"; |
| 486 | power-domains = <&scmi_devpd 9>; |
| 487 | scmi-perf-domain = <3>; |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 488 | iommus = <&smmu_700 0x200>; |
Anders Dellien | 7a84980 | 2022-01-01 21:51:21 +0000 | [diff] [blame] | 489 | }; |
| 490 | |
Rupinderjit Singh | b2a75b8 | 2023-02-03 09:29:57 +0000 | [diff] [blame] | 491 | power_model@simple { |
| 492 | /* |
| 493 | * Numbers used are irrelevant to Titan, |
| 494 | * it helps suppressing the kernel warnings. |
| 495 | */ |
| 496 | compatible = "arm,mali-simple-power-model"; |
| 497 | static-coefficient = <2427750>; |
| 498 | dynamic-coefficient = <4687>; |
| 499 | ts = <20000 2000 (-20) 2>; |
| 500 | thermal-zone = ""; |
| 501 | }; |
| 502 | |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 503 | smmu_700: smmu_700@3f000000 { |
Anders Dellien | a191413 | 2022-01-01 21:56:25 +0000 | [diff] [blame] | 504 | #iommu-cells = <1>; |
| 505 | compatible = "arm,smmu-v3"; |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 506 | reg = <0x0 0x3f000000 0x0 0x5000000>; |
Kshitij Sisodia | b32a8f4 | 2023-08-16 09:46:05 +0100 | [diff] [blame^] | 507 | interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, |
| 508 | <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, |
| 509 | <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>; |
| 510 | interrupt-names = "eventq", "cmdq-sync", "gerror"; |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 511 | dma-coherent; |
Anders Dellien | a191413 | 2022-01-01 21:56:25 +0000 | [diff] [blame] | 512 | }; |
| 513 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 514 | dp0: display@2cc00000 { |
| 515 | #address-cells = <1>; |
| 516 | #size-cells = <0>; |
| 517 | compatible = "arm,mali-d71"; |
| 518 | reg = <0 0x2cc00000 0 0x20000>; |
| 519 | interrupts = <0 69 4>; |
| 520 | interrupt-names = "DPU"; |
| 521 | clocks = <&scmi_clk 0>; |
| 522 | clock-names = "aclk"; |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 523 | iommus = <&smmu_700 0x100>; |
Ben Horgan | 80781a5 | 2023-07-26 20:45:27 +0100 | [diff] [blame] | 524 | power-domains = <&scmi_devpd 10>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 525 | pl0: pipeline@0 { |
| 526 | reg = <0>; |
| 527 | clocks = <&scmi_clk 1>; |
| 528 | clock-names = "pxclk"; |
| 529 | pl_id = <0>; |
| 530 | ports { |
| 531 | #address-cells = <1>; |
| 532 | #size-cells = <0>; |
| 533 | port@0 { |
| 534 | reg = <0>; |
| 535 | dp_pl0_out0: endpoint { |
| 536 | remote-endpoint = <&vencoder_in>; |
| 537 | }; |
| 538 | }; |
| 539 | }; |
| 540 | }; |
| 541 | |
| 542 | pl1: pipeline@1 { |
| 543 | reg = <1>; |
| 544 | clocks = <&scmi_clk 2>; |
| 545 | clock-names = "pxclk"; |
| 546 | pl_id = <1>; |
| 547 | ports { |
| 548 | #address-cells = <1>; |
| 549 | #size-cells = <0>; |
| 550 | port@0 { |
| 551 | reg = <0>; |
| 552 | }; |
| 553 | }; |
| 554 | }; |
| 555 | }; |
Arunachalam Ganapathy | c44e43d | 2020-11-17 15:05:01 +0000 | [diff] [blame] | 556 | |
Davidson K | 1ad2c41 | 2023-01-13 14:02:13 +0530 | [diff] [blame] | 557 | /* |
| 558 | * L3 cache in the DSU is the Memory System Component (MSC) |
| 559 | * The MPAM registers are accessed through utility bus in the DSU |
| 560 | */ |
| 561 | msc0 { |
| 562 | compatible = "arm,mpam-msc"; |
| 563 | reg = <0x1 0x00010000 0x0 0x2000>; |
| 564 | }; |
| 565 | |
Davidson K | 6536105 | 2021-10-13 18:49:41 +0530 | [diff] [blame] | 566 | ete0 { |
| 567 | compatible = "arm,embedded-trace-extension"; |
| 568 | cpu = <&CPU0>; |
| 569 | }; |
| 570 | |
| 571 | ete1 { |
| 572 | compatible = "arm,embedded-trace-extension"; |
| 573 | cpu = <&CPU1>; |
| 574 | }; |
| 575 | |
| 576 | ete2 { |
| 577 | compatible = "arm,embedded-trace-extension"; |
| 578 | cpu = <&CPU2>; |
| 579 | }; |
| 580 | |
| 581 | ete3 { |
| 582 | compatible = "arm,embedded-trace-extension"; |
| 583 | cpu = <&CPU3>; |
| 584 | }; |
| 585 | |
| 586 | ete4 { |
| 587 | compatible = "arm,embedded-trace-extension"; |
| 588 | cpu = <&CPU4>; |
| 589 | }; |
| 590 | |
| 591 | ete5 { |
| 592 | compatible = "arm,embedded-trace-extension"; |
| 593 | cpu = <&CPU5>; |
| 594 | }; |
| 595 | |
| 596 | ete6 { |
| 597 | compatible = "arm,embedded-trace-extension"; |
| 598 | cpu = <&CPU6>; |
| 599 | }; |
| 600 | |
| 601 | ete7 { |
| 602 | compatible = "arm,embedded-trace-extension"; |
| 603 | cpu = <&CPU7>; |
| 604 | }; |
| 605 | |
| 606 | trbe0 { |
| 607 | compatible = "arm,trace-buffer-extension"; |
| 608 | interrupts = <1 2 4>; |
| 609 | }; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 610 | }; |