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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diazc326c342019-01-11 11:20:10 +00002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef ARCH_H
8#define ARCH_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010011
12/*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070015#define MIDR_IMPL_MASK U(0xff)
16#define MIDR_IMPL_SHIFT U(0x18)
17#define MIDR_VAR_SHIFT U(20)
18#define MIDR_VAR_BITS U(4)
19#define MIDR_VAR_MASK U(0xf)
20#define MIDR_REV_SHIFT U(0)
21#define MIDR_REV_BITS U(4)
22#define MIDR_REV_MASK U(0xf)
23#define MIDR_PN_MASK U(0xfff)
24#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010025
26/*******************************************************************************
27 * MPIDR macros
28 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010029#define MPIDR_MT_MASK (ULL(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010030#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekarc6a11f62017-05-25 18:04:48 -070031#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
32#define MPIDR_AFFINITY_BITS U(8)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010033#define MPIDR_AFFLVL_MASK ULL(0xff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070034#define MPIDR_AFF0_SHIFT U(0)
35#define MPIDR_AFF1_SHIFT U(8)
36#define MPIDR_AFF2_SHIFT U(16)
37#define MPIDR_AFF3_SHIFT U(32)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000038#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010039#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070040#define MPIDR_AFFLVL_SHIFT U(3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000041#define MPIDR_AFFLVL0 ULL(0x0)
42#define MPIDR_AFFLVL1 ULL(0x1)
43#define MPIDR_AFFLVL2 ULL(0x2)
44#define MPIDR_AFFLVL3 ULL(0x3)
45#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000046#define MPIDR_AFFLVL0_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010047 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000048#define MPIDR_AFFLVL1_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010049 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000050#define MPIDR_AFFLVL2_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010051 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000052#define MPIDR_AFFLVL3_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010053 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000054/*
55 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
56 * add one while using this macro to define array sizes.
57 * TODO: Support only the first 3 affinity levels for now.
58 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070059#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010060
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000061#define MPID_MASK (MPIDR_MT_MASK | \
62 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
63 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
65 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
66
67#define MPIDR_AFF_ID(mpid, n) \
68 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
69
70/*
71 * An invalid MPID. This value can be used by functions that return an MPID to
72 * indicate an error.
73 */
74#define INVALID_MPID U(0xFFFFFFFF)
Achin Gupta4f6ad662013-10-25 09:08:21 +010075
76/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010077 * Definitions for CPU system register interface to GICv3
78 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000079#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
80#define ICC_SGI1R S3_0_C12_C11_5
81#define ICC_SRE_EL1 S3_0_C12_C12_5
82#define ICC_SRE_EL2 S3_4_C12_C9_5
83#define ICC_SRE_EL3 S3_6_C12_C12_5
84#define ICC_CTLR_EL1 S3_0_C12_C12_4
85#define ICC_CTLR_EL3 S3_6_C12_C12_4
86#define ICC_PMR_EL1 S3_0_C4_C6_0
87#define ICC_RPR_EL1 S3_0_C12_C11_3
88#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
89#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
90#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
91#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
92#define ICC_IAR0_EL1 S3_0_c12_c8_0
93#define ICC_IAR1_EL1 S3_0_c12_c12_0
94#define ICC_EOIR0_EL1 S3_0_c12_c8_1
95#define ICC_EOIR1_EL1 S3_0_c12_c12_1
96#define ICC_SGI0R_EL1 S3_0_c12_c11_7
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010097
98/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +000099 * Generic timer memory mapped registers & offsets
100 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700101#define CNTCR_OFF U(0x000)
102#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +0000103
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700104#define CNTCR_EN (U(1) << 0)
105#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100106#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000107
108/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100109 * System register bit definitions
110 ******************************************************************************/
111/* CLIDR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700112#define LOUIS_SHIFT U(21)
113#define LOC_SHIFT U(24)
114#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100115
116/* CSSELR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700117#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100118
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100119/* Data cache set/way op type defines */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700120#define DCISW U(0x0)
121#define DCCISW U(0x1)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000122#if ERRATA_A53_827319
123#define DCCSW DCCISW
124#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700125#define DCCSW U(0x2)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000126#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127
128/* ID_AA64PFR0_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700129#define ID_AA64PFR0_EL0_SHIFT U(0)
130#define ID_AA64PFR0_EL1_SHIFT U(4)
131#define ID_AA64PFR0_EL2_SHIFT U(8)
132#define ID_AA64PFR0_EL3_SHIFT U(12)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100133#define ID_AA64PFR0_AMU_SHIFT U(44)
134#define ID_AA64PFR0_AMU_LENGTH U(4)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100135#define ID_AA64PFR0_AMU_MASK ULL(0xf)
136#define ID_AA64PFR0_ELX_MASK ULL(0xf)
David Cunadoce88eee2017-10-20 11:30:57 +0100137#define ID_AA64PFR0_SVE_SHIFT U(32)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100138#define ID_AA64PFR0_SVE_MASK ULL(0xf)
David Cunadoce88eee2017-10-20 11:30:57 +0100139#define ID_AA64PFR0_SVE_LENGTH U(4)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100140#define ID_AA64PFR0_MPAM_SHIFT U(40)
141#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
Sathees Balya0911df12018-12-06 13:33:24 +0000142#define ID_AA64PFR0_DIT_SHIFT U(48)
143#define ID_AA64PFR0_DIT_MASK ULL(0xf)
144#define ID_AA64PFR0_DIT_LENGTH U(4)
145#define ID_AA64PFR0_DIT_SUPPORTED U(1)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000146#define ID_AA64PFR0_CSV2_SHIFT U(56)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100147#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000148#define ID_AA64PFR0_CSV2_LENGTH U(4)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100149
dp-armee3457b2017-05-23 09:32:49 +0100150/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
151#define ID_AA64DFR0_PMS_SHIFT U(32)
152#define ID_AA64DFR0_PMS_LENGTH U(4)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100153#define ID_AA64DFR0_PMS_MASK ULL(0xf)
dp-armee3457b2017-05-23 09:32:49 +0100154
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100155#define EL_IMPL_NONE ULL(0)
156#define EL_IMPL_A64ONLY ULL(1)
157#define EL_IMPL_A64_A32 ULL(2)
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000158
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700159#define ID_AA64PFR0_GIC_SHIFT U(24)
160#define ID_AA64PFR0_GIC_WIDTH U(4)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000161#define ID_AA64PFR0_GIC_MASK ULL(0xf)
Achin Gupta92712a52015-09-03 14:18:02 +0100162
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000163/* ID_AA64ISAR1_EL1 definitions */
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000164#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000165#define ID_AA64ISAR1_GPI_SHIFT U(28)
166#define ID_AA64ISAR1_GPI_WIDTH U(4)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000167#define ID_AA64ISAR1_GPI_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000168#define ID_AA64ISAR1_GPA_SHIFT U(24)
169#define ID_AA64ISAR1_GPA_WIDTH U(4)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000170#define ID_AA64ISAR1_GPA_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000171#define ID_AA64ISAR1_API_SHIFT U(8)
172#define ID_AA64ISAR1_API_WIDTH U(4)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000173#define ID_AA64ISAR1_API_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000174#define ID_AA64ISAR1_APA_SHIFT U(4)
175#define ID_AA64ISAR1_APA_WIDTH U(4)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000176#define ID_AA64ISAR1_APA_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000177
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000178/* ID_AA64MMFR0_EL1 definitions */
179#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
180#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
181
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700182#define PARANGE_0000 U(32)
183#define PARANGE_0001 U(36)
184#define PARANGE_0010 U(40)
185#define PARANGE_0011 U(42)
186#define PARANGE_0100 U(44)
187#define PARANGE_0101 U(48)
Antonio Nino Diazb9ef6642017-11-17 09:52:53 +0000188#define PARANGE_0110 U(52)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000189
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100190#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100191#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
192#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
193#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100194
195#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100196#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
197#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
198#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100199
200#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100201#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
202#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
203#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100204
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000205/* ID_AA64MMFR2_EL1 definitions */
206#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
Sathees Balya74155972019-01-25 11:36:01 +0000207
208#define ID_AA64MMFR2_EL1_ST_SHIFT U(28)
209#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
210
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000211#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
212#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
213
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000214/* ID_AA64PFR1_EL1 definitions */
215#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
216#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
217
218#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
219
Achin Gupta4f6ad662013-10-25 09:08:21 +0100220/* ID_PFR1_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700221#define ID_PFR1_VIRTEXT_SHIFT U(12)
222#define ID_PFR1_VIRTEXT_MASK U(0xf)
Antonio Nino Diaz34235a32018-07-11 16:45:49 +0100223#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
Achin Gupta4f6ad662013-10-25 09:08:21 +0100224 & ID_PFR1_VIRTEXT_MASK)
225
226/* SCTLR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100227#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700228 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
229 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100230
David Cunadofee86532017-04-13 22:38:29 +0100231#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700232 (U(1) << 22) | (U(1) << 20) | (U(1) << 11))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200233#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700234 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
235 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200236
David Cunadofee86532017-04-13 22:38:29 +0100237#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
238 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
239 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
240
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000241#define SCTLR_M_BIT (ULL(1) << 0)
242#define SCTLR_A_BIT (ULL(1) << 1)
243#define SCTLR_C_BIT (ULL(1) << 2)
244#define SCTLR_SA_BIT (ULL(1) << 3)
245#define SCTLR_SA0_BIT (ULL(1) << 4)
246#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
247#define SCTLR_ITD_BIT (ULL(1) << 7)
248#define SCTLR_SED_BIT (ULL(1) << 8)
249#define SCTLR_UMA_BIT (ULL(1) << 9)
250#define SCTLR_I_BIT (ULL(1) << 12)
251#define SCTLR_V_BIT (ULL(1) << 13)
252#define SCTLR_DZE_BIT (ULL(1) << 14)
253#define SCTLR_UCT_BIT (ULL(1) << 15)
254#define SCTLR_NTWI_BIT (ULL(1) << 16)
255#define SCTLR_NTWE_BIT (ULL(1) << 18)
256#define SCTLR_WXN_BIT (ULL(1) << 19)
257#define SCTLR_UWXN_BIT (ULL(1) << 20)
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000258#define SCTLR_IESB_BIT (ULL(1) << 21)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000259#define SCTLR_E0E_BIT (ULL(1) << 24)
260#define SCTLR_EE_BIT (ULL(1) << 25)
261#define SCTLR_UCI_BIT (ULL(1) << 26)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000262#define SCTLR_EnIA_BIT (ULL(1) << 31)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000263#define SCTLR_DSSBS_BIT (ULL(1) << 44)
David Cunadofee86532017-04-13 22:38:29 +0100264#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100265
Achin Gupta4f6ad662013-10-25 09:08:21 +0100266/* CPACR_El1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700267#define CPACR_EL1_FPEN(x) ((x) << 20)
268#define CPACR_EL1_FP_TRAP_EL0 U(0x1)
269#define CPACR_EL1_FP_TRAP_ALL U(0x2)
270#define CPACR_EL1_FP_TRAP_NONE U(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100271
272/* SCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700273#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000274#define SCR_FIEN_BIT (U(1) << 21)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100275#define SCR_API_BIT (U(1) << 17)
276#define SCR_APK_BIT (U(1) << 16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700277#define SCR_TWE_BIT (U(1) << 13)
278#define SCR_TWI_BIT (U(1) << 12)
279#define SCR_ST_BIT (U(1) << 11)
280#define SCR_RW_BIT (U(1) << 10)
281#define SCR_SIF_BIT (U(1) << 9)
282#define SCR_HCE_BIT (U(1) << 8)
283#define SCR_SMD_BIT (U(1) << 7)
284#define SCR_EA_BIT (U(1) << 3)
285#define SCR_FIQ_BIT (U(1) << 2)
286#define SCR_IRQ_BIT (U(1) << 1)
287#define SCR_NS_BIT (U(1) << 0)
288#define SCR_VALID_BIT_MASK U(0x2f8f)
David Cunadofee86532017-04-13 22:38:29 +0100289#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100290
David Cunadofee86532017-04-13 22:38:29 +0100291/* MDCR_EL3 definitions */
dp-arm595d0d52017-02-08 11:51:50 +0000292#define MDCR_SPD32(x) ((x) << 14)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000293#define MDCR_SPD32_LEGACY ULL(0x0)
294#define MDCR_SPD32_DISABLE ULL(0x2)
295#define MDCR_SPD32_ENABLE ULL(0x3)
296#define MDCR_SDD_BIT (ULL(1) << 16)
dp-armee3457b2017-05-23 09:32:49 +0100297#define MDCR_NSPB(x) ((x) << 12)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000298#define MDCR_NSPB_EL1 ULL(0x3)
299#define MDCR_TDOSA_BIT (ULL(1) << 10)
300#define MDCR_TDA_BIT (ULL(1) << 9)
301#define MDCR_TPM_BIT (ULL(1) << 6)
302#define MDCR_SCCD_BIT (ULL(1) << 23)
303#define MDCR_EL3_RESET_VAL ULL(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000304
David Cunadofee86532017-04-13 22:38:29 +0100305/* MDCR_EL2 definitions */
dp-armee3457b2017-05-23 09:32:49 +0100306#define MDCR_EL2_TPMS (U(1) << 14)
307#define MDCR_EL2_E2PB(x) ((x) << 12)
308#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100309#define MDCR_EL2_TDRA_BIT (U(1) << 11)
310#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
311#define MDCR_EL2_TDA_BIT (U(1) << 9)
312#define MDCR_EL2_TDE_BIT (U(1) << 8)
313#define MDCR_EL2_HPME_BIT (U(1) << 7)
314#define MDCR_EL2_TPM_BIT (U(1) << 6)
315#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
316#define MDCR_EL2_RESET_VAL U(0x0)
317
318/* HSTR_EL2 definitions */
319#define HSTR_EL2_RESET_VAL U(0x0)
320#define HSTR_EL2_T_MASK U(0xff)
321
322/* CNTHP_CTL_EL2 definitions */
323#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
324#define CNTHP_CTL_RESET_VAL U(0x0)
325
326/* VTTBR_EL2 definitions */
327#define VTTBR_RESET_VAL ULL(0x0)
328#define VTTBR_VMID_MASK ULL(0xff)
329#define VTTBR_VMID_SHIFT U(48)
330#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
331#define VTTBR_BADDR_SHIFT U(0)
dp-arm595d0d52017-02-08 11:51:50 +0000332
Achin Gupta4f6ad662013-10-25 09:08:21 +0100333/* HCR definitions */
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100334#define HCR_API_BIT (ULL(1) << 41)
335#define HCR_APK_BIT (ULL(1) << 40)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000336#define HCR_TGE_BIT (ULL(1) << 27)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700337#define HCR_RW_SHIFT U(31)
338#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100339#define HCR_AMO_BIT (ULL(1) << 5)
340#define HCR_IMO_BIT (ULL(1) << 4)
341#define HCR_FMO_BIT (ULL(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100342
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100343/* ISR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700344#define ISR_A_SHIFT U(8)
345#define ISR_I_SHIFT U(7)
346#define ISR_F_SHIFT U(6)
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100347
Achin Gupta4f6ad662013-10-25 09:08:21 +0100348/* CNTHCTL_EL2 definitions */
David Cunadofee86532017-04-13 22:38:29 +0100349#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700350#define EVNTEN_BIT (U(1) << 2)
351#define EL1PCEN_BIT (U(1) << 1)
352#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100353
354/* CNTKCTL_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700355#define EL0PTEN_BIT (U(1) << 9)
356#define EL0VTEN_BIT (U(1) << 8)
357#define EL0PCTEN_BIT (U(1) << 0)
358#define EL0VCTEN_BIT (U(1) << 1)
359#define EVNTEN_BIT (U(1) << 2)
360#define EVNTDIR_BIT (U(1) << 3)
361#define EVNTI_SHIFT U(4)
362#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100363
364/* CPTR_EL3 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700365#define TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100366#define TAM_BIT (U(1) << 30)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700367#define TTA_BIT (U(1) << 20)
368#define TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100369#define CPTR_EZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100370#define CPTR_EL3_RESET_VAL U(0x0)
371
372/* CPTR_EL2 definitions */
373#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
374#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100375#define CPTR_EL2_TAM_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100376#define CPTR_EL2_TTA_BIT (U(1) << 20)
377#define CPTR_EL2_TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100378#define CPTR_EL2_TZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100379#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100380
381/* CPSR/SPSR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700382#define DAIF_FIQ_BIT (U(1) << 0)
383#define DAIF_IRQ_BIT (U(1) << 1)
384#define DAIF_ABT_BIT (U(1) << 2)
385#define DAIF_DBG_BIT (U(1) << 3)
386#define SPSR_DAIF_SHIFT U(6)
387#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100388
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700389#define SPSR_AIF_SHIFT U(6)
390#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100391
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700392#define SPSR_E_SHIFT U(9)
393#define SPSR_E_MASK U(0x1)
394#define SPSR_E_LITTLE U(0x0)
395#define SPSR_E_BIG U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100396
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700397#define SPSR_T_SHIFT U(5)
398#define SPSR_T_MASK U(0x1)
399#define SPSR_T_ARM U(0x0)
400#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100401
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000402#define SPSR_M_SHIFT U(4)
403#define SPSR_M_MASK U(0x1)
404#define SPSR_M_AARCH64 U(0x0)
405#define SPSR_M_AARCH32 U(0x1)
406
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100407#define DISABLE_ALL_EXCEPTIONS \
408 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
409
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000410#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
411
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000412/*
413 * RMR_EL3 definitions
414 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700415#define RMR_EL3_RR_BIT (U(1) << 1)
416#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000417
418/*
419 * HI-VECTOR address for AArch32 state
420 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000421#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100422
423/*
424 * TCR defintions
425 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000426#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100427#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700428#define TCR_EL1_IPS_SHIFT U(32)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100429#define TCR_EL2_PS_SHIFT U(16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700430#define TCR_EL3_PS_SHIFT U(16)
Lin Ma741a3822014-06-27 16:56:30 -0700431
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100432#define TCR_TxSZ_MIN ULL(16)
433#define TCR_TxSZ_MAX ULL(39)
Sathees Balya74155972019-01-25 11:36:01 +0000434#define TCR_TxSZ_MAX_TTST ULL(48)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100435
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000436#define TCR_T0SZ_SHIFT U(0)
437#define TCR_T1SZ_SHIFT U(16)
438
Lin Ma741a3822014-06-27 16:56:30 -0700439/* (internal) physical address size bits in EL3/EL1 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100440#define TCR_PS_BITS_4GB ULL(0x0)
441#define TCR_PS_BITS_64GB ULL(0x1)
442#define TCR_PS_BITS_1TB ULL(0x2)
443#define TCR_PS_BITS_4TB ULL(0x3)
444#define TCR_PS_BITS_16TB ULL(0x4)
445#define TCR_PS_BITS_256TB ULL(0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100446
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700447#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
448#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
449#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
450#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
451#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
452#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100453
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100454#define TCR_RGN_INNER_NC (ULL(0x0) << 8)
455#define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
456#define TCR_RGN_INNER_WT (ULL(0x2) << 8)
457#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100458
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100459#define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
460#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
461#define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
462#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100463
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100464#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
465#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
466#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100467
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000468#define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
469#define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
470#define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
471#define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
472
473#define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
474#define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
475#define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
476#define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
477
478#define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
479#define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
480#define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
481
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100482#define TCR_TG0_SHIFT U(14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100483#define TCR_TG0_MASK ULL(3)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100484#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
485#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
486#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
487
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000488#define TCR_TG1_SHIFT U(30)
489#define TCR_TG1_MASK ULL(3)
490#define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
491#define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
492#define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
493
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100494#define TCR_EPD0_BIT (ULL(1) << 7)
495#define TCR_EPD1_BIT (ULL(1) << 23)
Antonio Nino Diazc8274a82017-09-15 10:30:34 +0100496
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700497#define MODE_SP_SHIFT U(0x0)
498#define MODE_SP_MASK U(0x1)
499#define MODE_SP_EL0 U(0x0)
500#define MODE_SP_ELX U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100501
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700502#define MODE_RW_SHIFT U(0x4)
503#define MODE_RW_MASK U(0x1)
504#define MODE_RW_64 U(0x0)
505#define MODE_RW_32 U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100506
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700507#define MODE_EL_SHIFT U(0x2)
508#define MODE_EL_MASK U(0x3)
509#define MODE_EL3 U(0x3)
510#define MODE_EL2 U(0x2)
511#define MODE_EL1 U(0x1)
512#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100513
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700514#define MODE32_SHIFT U(0)
515#define MODE32_MASK U(0xf)
516#define MODE32_usr U(0x0)
517#define MODE32_fiq U(0x1)
518#define MODE32_irq U(0x2)
519#define MODE32_svc U(0x3)
520#define MODE32_mon U(0x6)
521#define MODE32_abt U(0x7)
522#define MODE32_hyp U(0xa)
523#define MODE32_und U(0xb)
524#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100525
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100526#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
527#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
528#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
529#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100530
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100531#define SPSR_64(el, sp, daif) \
Antonio Nino Diaze8811472018-04-17 15:10:18 +0100532 ((MODE_RW_64 << MODE_RW_SHIFT) | \
533 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
534 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
535 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT))
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100536
537#define SPSR_MODE32(mode, isa, endian, aif) \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700538 ((MODE_RW_32 << MODE_RW_SHIFT) | \
539 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
540 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
541 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
542 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100543
Dan Handley0cdebbd2015-03-30 17:15:16 +0100544/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100545 * TTBR Definitions
546 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100547#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100548
549/*
Dan Handley0cdebbd2015-03-30 17:15:16 +0100550 * CTR_EL0 definitions
551 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700552#define CTR_CWG_SHIFT U(24)
553#define CTR_CWG_MASK U(0xf)
554#define CTR_ERG_SHIFT U(20)
555#define CTR_ERG_MASK U(0xf)
556#define CTR_DMINLINE_SHIFT U(16)
557#define CTR_DMINLINE_MASK U(0xf)
558#define CTR_L1IP_SHIFT U(14)
559#define CTR_L1IP_MASK U(0x3)
560#define CTR_IMINLINE_SHIFT U(0)
561#define CTR_IMINLINE_MASK U(0xf)
Dan Handley0cdebbd2015-03-30 17:15:16 +0100562
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700563#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100564
Achin Gupta405406d2014-05-09 12:00:17 +0100565/* Physical timer control register bit fields shifts and masks */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700566#define CNTP_CTL_ENABLE_SHIFT U(0)
567#define CNTP_CTL_IMASK_SHIFT U(1)
568#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Gupta405406d2014-05-09 12:00:17 +0100569
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700570#define CNTP_CTL_ENABLE_MASK U(1)
571#define CNTP_CTL_IMASK_MASK U(1)
572#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Gupta405406d2014-05-09 12:00:17 +0100573
Achin Gupta4f6ad662013-10-25 09:08:21 +0100574/* Exception Syndrome register bits and bobs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700575#define ESR_EC_SHIFT U(26)
576#define ESR_EC_MASK U(0x3f)
577#define ESR_EC_LENGTH U(6)
578#define EC_UNKNOWN U(0x0)
579#define EC_WFE_WFI U(0x1)
580#define EC_AARCH32_CP15_MRC_MCR U(0x3)
581#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
582#define EC_AARCH32_CP14_MRC_MCR U(0x5)
583#define EC_AARCH32_CP14_LDC_STC U(0x6)
584#define EC_FP_SIMD U(0x7)
585#define EC_AARCH32_CP10_MRC U(0x8)
586#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
587#define EC_ILLEGAL U(0xe)
588#define EC_AARCH32_SVC U(0x11)
589#define EC_AARCH32_HVC U(0x12)
590#define EC_AARCH32_SMC U(0x13)
591#define EC_AARCH64_SVC U(0x15)
592#define EC_AARCH64_HVC U(0x16)
593#define EC_AARCH64_SMC U(0x17)
594#define EC_AARCH64_SYS U(0x18)
595#define EC_IABORT_LOWER_EL U(0x20)
596#define EC_IABORT_CUR_EL U(0x21)
597#define EC_PC_ALIGN U(0x22)
598#define EC_DABORT_LOWER_EL U(0x24)
599#define EC_DABORT_CUR_EL U(0x25)
600#define EC_SP_ALIGN U(0x26)
601#define EC_AARCH32_FP U(0x28)
602#define EC_AARCH64_FP U(0x2c)
603#define EC_SERROR U(0x2f)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100604
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000605/*
606 * External Abort bit in Instruction and Data Aborts synchronous exception
607 * syndromes.
608 */
609#define ESR_ISS_EABORT_EA_BIT U(9)
610
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700611#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100612
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800613/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700614#define RMR_RESET_REQUEST_SHIFT U(0x1)
615#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800616
Dan Handleyed6ff952014-05-14 17:44:19 +0100617/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000618 * Definitions of register offsets, fields and macros for CPU system
619 * instructions.
620 ******************************************************************************/
621
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700622#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000623#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
624#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
625
626/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +0100627 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
628 * system level implementation of the Generic Timer.
629 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100630#define CNTCTLBASE_CNTFRQ U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700631#define CNTNSAR U(0x4)
632#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handleyed6ff952014-05-14 17:44:19 +0100633
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700634#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
635#define CNTACR_RPCT_SHIFT U(0x0)
636#define CNTACR_RVCT_SHIFT U(0x1)
637#define CNTACR_RFRQ_SHIFT U(0x2)
638#define CNTACR_RVOFF_SHIFT U(0x3)
639#define CNTACR_RWVT_SHIFT U(0x4)
640#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handleyed6ff952014-05-14 17:44:19 +0100641
Soby Mathew2d9f7952018-06-11 16:21:30 +0100642/*******************************************************************************
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000643 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew2d9f7952018-06-11 16:21:30 +0100644 * system level implementation of the Generic Timer.
645 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000646/* Physical Count register. */
647#define CNTPCT_LO U(0x0)
648/* Counter Frequency register. */
649#define CNTBASEN_CNTFRQ U(0x10)
650/* Physical Timer CompareValue register. */
651#define CNTP_CVAL_LO U(0x20)
652/* Physical Timer Control register. */
653#define CNTP_CTL U(0x2c)
Soby Mathew2d9f7952018-06-11 16:21:30 +0100654
David Cunado5f55e282016-10-31 17:37:34 +0000655/* PMCR_EL0 definitions */
David Cunado4168f2f2017-10-02 17:41:39 +0100656#define PMCR_EL0_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700657#define PMCR_EL0_N_SHIFT U(11)
658#define PMCR_EL0_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000659#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
David Cunado4168f2f2017-10-02 17:41:39 +0100660#define PMCR_EL0_LC_BIT (U(1) << 6)
661#define PMCR_EL0_DP_BIT (U(1) << 5)
662#define PMCR_EL0_X_BIT (U(1) << 4)
663#define PMCR_EL0_D_BIT (U(1) << 3)
David Cunado5f55e282016-10-31 17:37:34 +0000664
Isla Mitchell02c63072017-07-21 14:44:36 +0100665/*******************************************************************************
David Cunadoce88eee2017-10-20 11:30:57 +0100666 * Definitions for system register interface to SVE
667 ******************************************************************************/
668#define ZCR_EL3 S3_6_C1_C2_0
669#define ZCR_EL2 S3_4_C1_C2_0
670
671/* ZCR_EL3 definitions */
672#define ZCR_EL3_LEN_MASK U(0xf)
673
674/* ZCR_EL2 definitions */
675#define ZCR_EL2_LEN_MASK U(0xf)
676
677/*******************************************************************************
Isla Mitchell02c63072017-07-21 14:44:36 +0100678 * Definitions of MAIR encodings for device and normal memory
679 ******************************************************************************/
680/*
681 * MAIR encodings for device memory attributes.
682 */
683#define MAIR_DEV_nGnRnE ULL(0x0)
684#define MAIR_DEV_nGnRE ULL(0x4)
685#define MAIR_DEV_nGRE ULL(0x8)
686#define MAIR_DEV_GRE ULL(0xc)
687
688/*
689 * MAIR encodings for normal memory attributes.
690 *
691 * Cache Policy
692 * WT: Write Through
693 * WB: Write Back
694 * NC: Non-Cacheable
695 *
696 * Transient Hint
697 * NTR: Non-Transient
698 * TR: Transient
699 *
700 * Allocation Policy
701 * RA: Read Allocate
702 * WA: Write Allocate
703 * RWA: Read and Write Allocate
704 * NA: No Allocation
705 */
706#define MAIR_NORM_WT_TR_WA ULL(0x1)
707#define MAIR_NORM_WT_TR_RA ULL(0x2)
708#define MAIR_NORM_WT_TR_RWA ULL(0x3)
709#define MAIR_NORM_NC ULL(0x4)
710#define MAIR_NORM_WB_TR_WA ULL(0x5)
711#define MAIR_NORM_WB_TR_RA ULL(0x6)
712#define MAIR_NORM_WB_TR_RWA ULL(0x7)
713#define MAIR_NORM_WT_NTR_NA ULL(0x8)
714#define MAIR_NORM_WT_NTR_WA ULL(0x9)
715#define MAIR_NORM_WT_NTR_RA ULL(0xa)
716#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
717#define MAIR_NORM_WB_NTR_NA ULL(0xc)
718#define MAIR_NORM_WB_NTR_WA ULL(0xd)
719#define MAIR_NORM_WB_NTR_RA ULL(0xe)
720#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
721
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100722#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +0100723
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100724#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
725 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +0100726
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100727/* PAR_EL1 fields */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100728#define PAR_F_SHIFT U(0)
729#define PAR_F_MASK ULL(0x1)
730#define PAR_ADDR_SHIFT U(12)
731#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100732
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100733/*******************************************************************************
734 * Definitions for system register interface to SPE
735 ******************************************************************************/
736#define PMBLIMITR_EL1 S3_0_C9_C10_0
737
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100738/*******************************************************************************
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100739 * Definitions for system register interface to MPAM
740 ******************************************************************************/
741#define MPAMIDR_EL1 S3_0_C10_C4_4
742#define MPAM2_EL2 S3_4_C10_C5_0
743#define MPAMHCR_EL2 S3_4_C10_C4_0
744#define MPAM3_EL3 S3_6_C10_C5_0
745
746/*******************************************************************************
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100747 * Definitions for system register interface to AMU for ARMv8.4 onwards
748 ******************************************************************************/
749#define AMCR_EL0 S3_3_C13_C2_0
750#define AMCFGR_EL0 S3_3_C13_C2_1
751#define AMCGCR_EL0 S3_3_C13_C2_2
752#define AMUSERENR_EL0 S3_3_C13_C2_3
753#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
754#define AMCNTENSET0_EL0 S3_3_C13_C2_5
755#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
756#define AMCNTENSET1_EL0 S3_3_C13_C3_1
757
758/* Activity Monitor Group 0 Event Counter Registers */
759#define AMEVCNTR00_EL0 S3_3_C13_C4_0
760#define AMEVCNTR01_EL0 S3_3_C13_C4_1
761#define AMEVCNTR02_EL0 S3_3_C13_C4_2
762#define AMEVCNTR03_EL0 S3_3_C13_C4_3
763
764/* Activity Monitor Group 0 Event Type Registers */
765#define AMEVTYPER00_EL0 S3_3_C13_C6_0
766#define AMEVTYPER01_EL0 S3_3_C13_C6_1
767#define AMEVTYPER02_EL0 S3_3_C13_C6_2
768#define AMEVTYPER03_EL0 S3_3_C13_C6_3
769
Dimitris Papastamos525c37a2017-11-13 09:49:45 +0000770/* Activity Monitor Group 1 Event Counter Registers */
771#define AMEVCNTR10_EL0 S3_3_C13_C12_0
772#define AMEVCNTR11_EL0 S3_3_C13_C12_1
773#define AMEVCNTR12_EL0 S3_3_C13_C12_2
774#define AMEVCNTR13_EL0 S3_3_C13_C12_3
775#define AMEVCNTR14_EL0 S3_3_C13_C12_4
776#define AMEVCNTR15_EL0 S3_3_C13_C12_5
777#define AMEVCNTR16_EL0 S3_3_C13_C12_6
778#define AMEVCNTR17_EL0 S3_3_C13_C12_7
779#define AMEVCNTR18_EL0 S3_3_C13_C13_0
780#define AMEVCNTR19_EL0 S3_3_C13_C13_1
781#define AMEVCNTR1A_EL0 S3_3_C13_C13_2
782#define AMEVCNTR1B_EL0 S3_3_C13_C13_3
783#define AMEVCNTR1C_EL0 S3_3_C13_C13_4
784#define AMEVCNTR1D_EL0 S3_3_C13_C13_5
785#define AMEVCNTR1E_EL0 S3_3_C13_C13_6
786#define AMEVCNTR1F_EL0 S3_3_C13_C13_7
787
788/* Activity Monitor Group 1 Event Type Registers */
789#define AMEVTYPER10_EL0 S3_3_C13_C14_0
790#define AMEVTYPER11_EL0 S3_3_C13_C14_1
791#define AMEVTYPER12_EL0 S3_3_C13_C14_2
792#define AMEVTYPER13_EL0 S3_3_C13_C14_3
793#define AMEVTYPER14_EL0 S3_3_C13_C14_4
794#define AMEVTYPER15_EL0 S3_3_C13_C14_5
795#define AMEVTYPER16_EL0 S3_3_C13_C14_6
796#define AMEVTYPER17_EL0 S3_3_C13_C14_7
797#define AMEVTYPER18_EL0 S3_3_C13_C15_0
798#define AMEVTYPER19_EL0 S3_3_C13_C15_1
799#define AMEVTYPER1A_EL0 S3_3_C13_C15_2
800#define AMEVTYPER1B_EL0 S3_3_C13_C15_3
801#define AMEVTYPER1C_EL0 S3_3_C13_C15_4
802#define AMEVTYPER1D_EL0 S3_3_C13_C15_5
803#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
804#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
805
806/* AMCGCR_EL0 definitions */
807#define AMCGCR_EL0_CG1NC_SHIFT U(8)
808#define AMCGCR_EL0_CG1NC_LENGTH U(8)
809#define AMCGCR_EL0_CG1NC_MASK U(0xff)
810
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100811/* MPAM register definitions */
812#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
Louis Mayencourtbdfa1032019-02-11 11:25:50 +0000813#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
814
815#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
816#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100817
818#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
819
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100820/*******************************************************************************
821 * RAS system registers
Sathees Balya0911df12018-12-06 13:33:24 +0000822 ******************************************************************************/
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100823#define DISR_EL1 S3_0_C12_C1_1
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100824#define DISR_A_BIT U(31)
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100825
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000826#define ERRIDR_EL1 S3_0_C5_C3_0
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100827#define ERRIDR_MASK U(0xffff)
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000828
829#define ERRSELR_EL1 S3_0_C5_C3_1
830
831/* System register access to Standard Error Record registers */
832#define ERXFR_EL1 S3_0_C5_C4_0
833#define ERXCTLR_EL1 S3_0_C5_C4_1
834#define ERXSTATUS_EL1 S3_0_C5_C4_2
835#define ERXADDR_EL1 S3_0_C5_C4_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000836#define ERXPFGF_EL1 S3_0_C5_C4_4
837#define ERXPFGCTL_EL1 S3_0_C5_C4_5
838#define ERXPFGCDN_EL1 S3_0_C5_C4_6
Jan Dabros82ef8bf2018-08-30 13:52:23 +0200839#define ERXMISC0_EL1 S3_0_C5_C5_0
840#define ERXMISC1_EL1 S3_0_C5_C5_1
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000841
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000842#define ERXCTLR_ED_BIT (U(1) << 0)
843#define ERXCTLR_UE_BIT (U(1) << 4)
844
845#define ERXPFGCTL_UC_BIT (U(1) << 1)
846#define ERXPFGCTL_UEU_BIT (U(1) << 2)
847#define ERXPFGCTL_CDEN_BIT (U(1) << 31)
848
849/*******************************************************************************
850 * Armv8.3 Pointer Authentication Registers
Sathees Balya0911df12018-12-06 13:33:24 +0000851 ******************************************************************************/
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000852#define APIAKeyLo_EL1 S3_0_C2_C1_0
853#define APIAKeyHi_EL1 S3_0_C2_C1_1
854#define APIBKeyLo_EL1 S3_0_C2_C1_2
855#define APIBKeyHi_EL1 S3_0_C2_C1_3
856#define APDAKeyLo_EL1 S3_0_C2_C2_0
857#define APDAKeyHi_EL1 S3_0_C2_C2_1
858#define APDBKeyLo_EL1 S3_0_C2_C2_2
859#define APDBKeyHi_EL1 S3_0_C2_C2_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000860#define APGAKeyLo_EL1 S3_0_C2_C3_0
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000861#define APGAKeyHi_EL1 S3_0_C2_C3_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000862
Sathees Balya0911df12018-12-06 13:33:24 +0000863/*******************************************************************************
864 * Armv8.4 Data Independent Timing Registers
865 ******************************************************************************/
866#define DIT S3_3_C4_C2_5
867#define DIT_BIT BIT(24)
868
John Tsichritzis1f9ff492019-03-04 16:41:26 +0000869/*******************************************************************************
870 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
871 ******************************************************************************/
872#define SSBS S3_3_C4_C2_6
873
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100874#endif /* ARCH_H */