Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Madhukar Pappireddy | f4e6ea6 | 2020-01-27 15:32:15 -0600 | [diff] [blame] | 2 | * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <platform_def.h> |
| 8 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 9 | #include <arch.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 10 | #include <asm_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <bl31/ea_handle.h> |
| 12 | #include <bl31/interrupt_mgmt.h> |
| 13 | #include <common/runtime_svc.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 14 | #include <context.h> |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 15 | #include <el3_common_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 16 | #include <lib/el3_runtime/cpu_data.h> |
| 17 | #include <lib/smccc.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 18 | |
| 19 | .globl runtime_exceptions |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 20 | |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 21 | .globl sync_exception_sp_el0 |
| 22 | .globl irq_sp_el0 |
| 23 | .globl fiq_sp_el0 |
| 24 | .globl serror_sp_el0 |
| 25 | |
| 26 | .globl sync_exception_sp_elx |
| 27 | .globl irq_sp_elx |
| 28 | .globl fiq_sp_elx |
| 29 | .globl serror_sp_elx |
| 30 | |
| 31 | .globl sync_exception_aarch64 |
| 32 | .globl irq_aarch64 |
| 33 | .globl fiq_aarch64 |
| 34 | .globl serror_aarch64 |
| 35 | |
| 36 | .globl sync_exception_aarch32 |
| 37 | .globl irq_aarch32 |
| 38 | .globl fiq_aarch32 |
| 39 | .globl serror_aarch32 |
| 40 | |
Jeenu Viswambharan | 96c7df0 | 2017-11-30 12:54:15 +0000 | [diff] [blame] | 41 | /* |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 42 | * Macro that prepares entry to EL3 upon taking an exception. |
| 43 | * |
| 44 | * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB |
| 45 | * instruction. When an error is thus synchronized, the handling is |
| 46 | * delegated to platform EA handler. |
| 47 | * |
| 48 | * Without RAS_EXTENSION, this macro just saves x30, and unmasks |
| 49 | * Asynchronous External Aborts. |
| 50 | */ |
| 51 | .macro check_and_unmask_ea |
| 52 | #if RAS_EXTENSION |
| 53 | /* Synchronize pending External Aborts */ |
| 54 | esb |
| 55 | |
| 56 | /* Unmask the SError interrupt */ |
| 57 | msr daifclr, #DAIF_ABT_BIT |
| 58 | |
| 59 | /* |
| 60 | * Explicitly save x30 so as to free up a register and to enable |
| 61 | * branching |
| 62 | */ |
| 63 | str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
| 64 | |
| 65 | /* Check for SErrors synchronized by the ESB instruction */ |
| 66 | mrs x30, DISR_EL1 |
| 67 | tbz x30, #DISR_A_BIT, 1f |
| 68 | |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 69 | /* |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 70 | * Save general purpose and ARMv8.3-PAuth registers (if enabled). |
| 71 | * If Secure Cycle Counter is not disabled in MDCR_EL3 when |
| 72 | * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 73 | */ |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 74 | bl save_gp_pmcr_pauth_regs |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 75 | |
Jeenu Viswambharan | e86a247 | 2018-07-05 15:24:45 +0100 | [diff] [blame] | 76 | bl handle_lower_el_ea_esb |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 77 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 78 | /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */ |
| 79 | bl restore_gp_pmcr_pauth_regs |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 80 | 1: |
| 81 | #else |
| 82 | /* Unmask the SError interrupt */ |
| 83 | msr daifclr, #DAIF_ABT_BIT |
| 84 | |
| 85 | str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
| 86 | #endif |
| 87 | .endm |
| 88 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 89 | /* --------------------------------------------------------------------- |
| 90 | * This macro handles Synchronous exceptions. |
| 91 | * Only SMC exceptions are supported. |
| 92 | * --------------------------------------------------------------------- |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 93 | */ |
| 94 | .macro handle_sync_exception |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 95 | #if ENABLE_RUNTIME_INSTRUMENTATION |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 96 | /* |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 97 | * Read the timestamp value and store it in per-cpu data. The value |
| 98 | * will be extracted from per-cpu data by the C level SMC handler and |
| 99 | * saved to the PMF timestamp region. |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 100 | */ |
| 101 | mrs x30, cntpct_el0 |
| 102 | str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] |
| 103 | mrs x29, tpidr_el3 |
| 104 | str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] |
| 105 | ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] |
| 106 | #endif |
| 107 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 108 | mrs x30, esr_el3 |
| 109 | ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH |
| 110 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 111 | /* Handle SMC exceptions separately from other synchronous exceptions */ |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 112 | cmp x30, #EC_AARCH32_SMC |
| 113 | b.eq smc_handler32 |
| 114 | |
| 115 | cmp x30, #EC_AARCH64_SMC |
| 116 | b.eq smc_handler64 |
| 117 | |
Jeenu Viswambharan | e86a247 | 2018-07-05 15:24:45 +0100 | [diff] [blame] | 118 | /* Synchronous exceptions other than the above are assumed to be EA */ |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 119 | ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
Jeenu Viswambharan | e86a247 | 2018-07-05 15:24:45 +0100 | [diff] [blame] | 120 | b enter_lower_el_sync_ea |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 121 | .endm |
| 122 | |
| 123 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 124 | /* --------------------------------------------------------------------- |
| 125 | * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS |
| 126 | * interrupts. |
| 127 | * --------------------------------------------------------------------- |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 128 | */ |
| 129 | .macro handle_interrupt_exception label |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 130 | |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 131 | /* |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 132 | * Save general purpose and ARMv8.3-PAuth registers (if enabled). |
| 133 | * If Secure Cycle Counter is not disabled in MDCR_EL3 when |
| 134 | * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 135 | */ |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 136 | bl save_gp_pmcr_pauth_regs |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 137 | |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 138 | #if ENABLE_PAUTH |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 139 | /* Load and program APIAKey firmware key */ |
| 140 | bl pauth_load_bl31_apiakey |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 141 | #endif |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 142 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 143 | /* Save the EL3 system registers needed to return from this exception */ |
Achin Gupta | 979992e | 2015-05-13 17:57:18 +0100 | [diff] [blame] | 144 | mrs x0, spsr_el3 |
| 145 | mrs x1, elr_el3 |
| 146 | stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] |
| 147 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 148 | /* Switch to the runtime stack i.e. SP_EL0 */ |
| 149 | ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] |
| 150 | mov x20, sp |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 151 | msr spsel, #MODE_SP_EL0 |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 152 | mov sp, x2 |
| 153 | |
| 154 | /* |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 155 | * Find out whether this is a valid interrupt type. |
| 156 | * If the interrupt controller reports a spurious interrupt then return |
| 157 | * to where we came from. |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 158 | */ |
Dan Handley | 701fea7 | 2014-05-27 16:17:21 +0100 | [diff] [blame] | 159 | bl plat_ic_get_pending_interrupt_type |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 160 | cmp x0, #INTR_TYPE_INVAL |
| 161 | b.eq interrupt_exit_\label |
| 162 | |
| 163 | /* |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 164 | * Get the registered handler for this interrupt type. |
| 165 | * A NULL return value could be 'cause of the following conditions: |
Achin Gupta | 979992e | 2015-05-13 17:57:18 +0100 | [diff] [blame] | 166 | * |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 167 | * a. An interrupt of a type was routed correctly but a handler for its |
| 168 | * type was not registered. |
Achin Gupta | 979992e | 2015-05-13 17:57:18 +0100 | [diff] [blame] | 169 | * |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 170 | * b. An interrupt of a type was not routed correctly so a handler for |
| 171 | * its type was not registered. |
Achin Gupta | 979992e | 2015-05-13 17:57:18 +0100 | [diff] [blame] | 172 | * |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 173 | * c. An interrupt of a type was routed correctly to EL3, but was |
| 174 | * deasserted before its pending state could be read. Another |
| 175 | * interrupt of a different type pended at the same time and its |
| 176 | * type was reported as pending instead. However, a handler for this |
| 177 | * type was not registered. |
Achin Gupta | 979992e | 2015-05-13 17:57:18 +0100 | [diff] [blame] | 178 | * |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 179 | * a. and b. can only happen due to a programming error. The |
| 180 | * occurrence of c. could be beyond the control of Trusted Firmware. |
| 181 | * It makes sense to return from this exception instead of reporting an |
| 182 | * error. |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 183 | */ |
| 184 | bl get_interrupt_type_handler |
Achin Gupta | 979992e | 2015-05-13 17:57:18 +0100 | [diff] [blame] | 185 | cbz x0, interrupt_exit_\label |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 186 | mov x21, x0 |
| 187 | |
| 188 | mov x0, #INTR_ID_UNAVAILABLE |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 189 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 190 | /* Set the current security state in the 'flags' parameter */ |
| 191 | mrs x2, scr_el3 |
| 192 | ubfx x1, x2, #0, #1 |
| 193 | |
| 194 | /* Restore the reference to the 'handle' i.e. SP_EL3 */ |
| 195 | mov x2, x20 |
| 196 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 197 | /* x3 will point to a cookie (not used now) */ |
Soby Mathew | 799f0ab | 2014-05-27 16:54:31 +0100 | [diff] [blame] | 198 | mov x3, xzr |
| 199 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 200 | /* Call the interrupt type handler */ |
| 201 | blr x21 |
| 202 | |
| 203 | interrupt_exit_\label: |
| 204 | /* Return from exception, possibly in a different security state */ |
| 205 | b el3_exit |
| 206 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 207 | .endm |
| 208 | |
| 209 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 210 | vector_base runtime_exceptions |
| 211 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 212 | /* --------------------------------------------------------------------- |
| 213 | * Current EL with SP_EL0 : 0x0 - 0x200 |
| 214 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 215 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 216 | vector_entry sync_exception_sp_el0 |
Justin Chadwell | 83e0488 | 2019-08-20 11:01:52 +0100 | [diff] [blame] | 217 | #ifdef MONITOR_TRAPS |
| 218 | stp x29, x30, [sp, #-16]! |
| 219 | |
| 220 | mrs x30, esr_el3 |
| 221 | ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH |
| 222 | |
| 223 | /* Check for BRK */ |
| 224 | cmp x30, #EC_BRK |
| 225 | b.eq brk_handler |
| 226 | |
| 227 | ldp x29, x30, [sp], #16 |
| 228 | #endif /* MONITOR_TRAPS */ |
| 229 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 230 | /* We don't expect any synchronous exceptions from EL3 */ |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 231 | b report_unhandled_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 232 | end_vector_entry sync_exception_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 233 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 234 | vector_entry irq_sp_el0 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 235 | /* |
| 236 | * EL3 code is non-reentrant. Any asynchronous exception is a serious |
| 237 | * error. Loop infinitely. |
| 238 | */ |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 239 | b report_unhandled_interrupt |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 240 | end_vector_entry irq_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 241 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 242 | |
| 243 | vector_entry fiq_sp_el0 |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 244 | b report_unhandled_interrupt |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 245 | end_vector_entry fiq_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 246 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 247 | |
| 248 | vector_entry serror_sp_el0 |
Jeenu Viswambharan | 911fcc9 | 2018-07-06 16:50:06 +0100 | [diff] [blame] | 249 | no_ret plat_handle_el3_ea |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 250 | end_vector_entry serror_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 251 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 252 | /* --------------------------------------------------------------------- |
| 253 | * Current EL with SP_ELx: 0x200 - 0x400 |
| 254 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 255 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 256 | vector_entry sync_exception_sp_elx |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 257 | /* |
| 258 | * This exception will trigger if anything went wrong during a previous |
| 259 | * exception entry or exit or while handling an earlier unexpected |
| 260 | * synchronous exception. There is a high probability that SP_EL3 is |
| 261 | * corrupted. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 262 | */ |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 263 | b report_unhandled_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 264 | end_vector_entry sync_exception_sp_elx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 265 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 266 | vector_entry irq_sp_elx |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 267 | b report_unhandled_interrupt |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 268 | end_vector_entry irq_sp_elx |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 269 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 270 | vector_entry fiq_sp_elx |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 271 | b report_unhandled_interrupt |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 272 | end_vector_entry fiq_sp_elx |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 273 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 274 | vector_entry serror_sp_elx |
Jeenu Viswambharan | 911fcc9 | 2018-07-06 16:50:06 +0100 | [diff] [blame] | 275 | no_ret plat_handle_el3_ea |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 276 | end_vector_entry serror_sp_elx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 277 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 278 | /* --------------------------------------------------------------------- |
Sandrine Bailleux | 046cd3f | 2014-08-06 11:27:23 +0100 | [diff] [blame] | 279 | * Lower EL using AArch64 : 0x400 - 0x600 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 280 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 281 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 282 | vector_entry sync_exception_aarch64 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 283 | /* |
| 284 | * This exception vector will be the entry point for SMCs and traps |
| 285 | * that are unhandled at lower ELs most commonly. SP_EL3 should point |
| 286 | * to a valid cpu context where the general purpose and system register |
| 287 | * state can be saved. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 288 | */ |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 289 | apply_at_speculative_wa |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 290 | check_and_unmask_ea |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 291 | handle_sync_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 292 | end_vector_entry sync_exception_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 293 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 294 | vector_entry irq_aarch64 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 295 | apply_at_speculative_wa |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 296 | check_and_unmask_ea |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 297 | handle_interrupt_exception irq_aarch64 |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 298 | end_vector_entry irq_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 299 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 300 | vector_entry fiq_aarch64 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 301 | apply_at_speculative_wa |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 302 | check_and_unmask_ea |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 303 | handle_interrupt_exception fiq_aarch64 |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 304 | end_vector_entry fiq_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 305 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 306 | vector_entry serror_aarch64 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 307 | apply_at_speculative_wa |
Jeenu Viswambharan | 96c7df0 | 2017-11-30 12:54:15 +0000 | [diff] [blame] | 308 | msr daifclr, #DAIF_ABT_BIT |
Jeenu Viswambharan | e86a247 | 2018-07-05 15:24:45 +0100 | [diff] [blame] | 309 | b enter_lower_el_async_ea |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 310 | end_vector_entry serror_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 311 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 312 | /* --------------------------------------------------------------------- |
Sandrine Bailleux | 046cd3f | 2014-08-06 11:27:23 +0100 | [diff] [blame] | 313 | * Lower EL using AArch32 : 0x600 - 0x800 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 314 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 315 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 316 | vector_entry sync_exception_aarch32 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 317 | /* |
| 318 | * This exception vector will be the entry point for SMCs and traps |
| 319 | * that are unhandled at lower ELs most commonly. SP_EL3 should point |
| 320 | * to a valid cpu context where the general purpose and system register |
| 321 | * state can be saved. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 322 | */ |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 323 | apply_at_speculative_wa |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 324 | check_and_unmask_ea |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 325 | handle_sync_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 326 | end_vector_entry sync_exception_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 327 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 328 | vector_entry irq_aarch32 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 329 | apply_at_speculative_wa |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 330 | check_and_unmask_ea |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 331 | handle_interrupt_exception irq_aarch32 |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 332 | end_vector_entry irq_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 333 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 334 | vector_entry fiq_aarch32 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 335 | apply_at_speculative_wa |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 336 | check_and_unmask_ea |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 337 | handle_interrupt_exception fiq_aarch32 |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 338 | end_vector_entry fiq_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 339 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 340 | vector_entry serror_aarch32 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 341 | apply_at_speculative_wa |
Jeenu Viswambharan | 96c7df0 | 2017-11-30 12:54:15 +0000 | [diff] [blame] | 342 | msr daifclr, #DAIF_ABT_BIT |
Jeenu Viswambharan | e86a247 | 2018-07-05 15:24:45 +0100 | [diff] [blame] | 343 | b enter_lower_el_async_ea |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 344 | end_vector_entry serror_aarch32 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 345 | |
Justin Chadwell | 83e0488 | 2019-08-20 11:01:52 +0100 | [diff] [blame] | 346 | #ifdef MONITOR_TRAPS |
| 347 | .section .rodata.brk_string, "aS" |
| 348 | brk_location: |
| 349 | .asciz "Error at instruction 0x" |
| 350 | brk_message: |
| 351 | .asciz "Unexpected BRK instruction with value 0x" |
| 352 | #endif /* MONITOR_TRAPS */ |
| 353 | |
Antonio Nino Diaz | 35c8cfc | 2018-04-23 15:43:29 +0100 | [diff] [blame] | 354 | /* --------------------------------------------------------------------- |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 355 | * The following code handles secure monitor calls. |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 356 | * Depending upon the execution state from where the SMC has been |
| 357 | * invoked, it frees some general purpose registers to perform the |
| 358 | * remaining tasks. They involve finding the runtime service handler |
| 359 | * that is the target of the SMC & switching to runtime stacks (SP_EL0) |
| 360 | * before calling the handler. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 361 | * |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 362 | * Note that x30 has been explicitly saved and can be used here |
| 363 | * --------------------------------------------------------------------- |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 364 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 365 | func smc_handler |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 366 | smc_handler32: |
| 367 | /* Check whether aarch32 issued an SMC64 */ |
| 368 | tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited |
| 369 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 370 | smc_handler64: |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 371 | /* NOTE: The code below must preserve x0-x4 */ |
| 372 | |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 373 | /* |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 374 | * Save general purpose and ARMv8.3-PAuth registers (if enabled). |
| 375 | * If Secure Cycle Counter is not disabled in MDCR_EL3 when |
| 376 | * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 377 | */ |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 378 | bl save_gp_pmcr_pauth_regs |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 379 | |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 380 | #if ENABLE_PAUTH |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 381 | /* Load and program APIAKey firmware key */ |
| 382 | bl pauth_load_bl31_apiakey |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 383 | #endif |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 384 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 385 | /* |
| 386 | * Populate the parameters for the SMC handler. |
| 387 | * We already have x0-x4 in place. x5 will point to a cookie (not used |
| 388 | * now). x6 will point to the context structure (SP_EL3) and x7 will |
Dimitris Papastamos | 0415951 | 2018-01-22 11:53:04 +0000 | [diff] [blame] | 389 | * contain flags we need to pass to the handler. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 390 | */ |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 391 | mov x5, xzr |
| 392 | mov x6, sp |
| 393 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 394 | /* |
Antonio Nino Diaz | 35c8cfc | 2018-04-23 15:43:29 +0100 | [diff] [blame] | 395 | * Restore the saved C runtime stack value which will become the new |
| 396 | * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' |
| 397 | * structure prior to the last ERET from EL3. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 398 | */ |
Antonio Nino Diaz | 35c8cfc | 2018-04-23 15:43:29 +0100 | [diff] [blame] | 399 | ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] |
| 400 | |
| 401 | /* Switch to SP_EL0 */ |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 402 | msr spsel, #MODE_SP_EL0 |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 403 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 404 | /* |
| 405 | * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world |
| 406 | * switch during SMC handling. |
| 407 | * TODO: Revisit if all system registers can be saved later. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 408 | */ |
| 409 | mrs x16, spsr_el3 |
| 410 | mrs x17, elr_el3 |
| 411 | mrs x18, scr_el3 |
| 412 | stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] |
Achin Gupta | e1aa516 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 413 | str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 414 | |
| 415 | /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ |
| 416 | bfi x7, x18, #0, #1 |
| 417 | |
| 418 | mov sp, x12 |
| 419 | |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 420 | /* Get the unique owning entity number */ |
| 421 | ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH |
| 422 | ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH |
| 423 | orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH |
| 424 | |
| 425 | /* Load descriptor index from array of indices */ |
Madhukar Pappireddy | f4e6ea6 | 2020-01-27 15:32:15 -0600 | [diff] [blame] | 426 | adrp x14, rt_svc_descs_indices |
| 427 | add x14, x14, :lo12:rt_svc_descs_indices |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 428 | ldrb w15, [x14, x16] |
| 429 | |
| 430 | /* Any index greater than 127 is invalid. Check bit 7. */ |
| 431 | tbnz w15, 7, smc_unknown |
| 432 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 433 | /* |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 434 | * Get the descriptor using the index |
| 435 | * x11 = (base + off), w15 = index |
| 436 | * |
| 437 | * handler = (base + off) + (index << log2(size)) |
| 438 | */ |
| 439 | adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) |
| 440 | lsl w10, w15, #RT_SVC_SIZE_LOG2 |
| 441 | ldr x15, [x11, w10, uxtw] |
| 442 | |
| 443 | /* |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 444 | * Call the Secure Monitor Call handler and then drop directly into |
| 445 | * el3_exit() which will program any remaining architectural state |
| 446 | * prior to issuing the ERET to the desired lower EL. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 447 | */ |
| 448 | #if DEBUG |
| 449 | cbz x15, rt_svc_fw_critical_error |
| 450 | #endif |
| 451 | blr x15 |
| 452 | |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 453 | b el3_exit |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 454 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 455 | smc_unknown: |
| 456 | /* |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 457 | * Unknown SMC call. Populate return value with SMC_UNK and call |
| 458 | * el3_exit() which will restore the remaining architectural state |
| 459 | * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET |
| 460 | * to the desired lower EL. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 461 | */ |
Antonio Nino Diaz | e4794b7 | 2018-02-14 14:22:29 +0000 | [diff] [blame] | 462 | mov x0, #SMC_UNK |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 463 | str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] |
| 464 | b el3_exit |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 465 | |
| 466 | smc_prohibited: |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 467 | restore_ptw_el1_sys_regs |
| 468 | ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 469 | ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
Antonio Nino Diaz | e4794b7 | 2018-02-14 14:22:29 +0000 | [diff] [blame] | 470 | mov x0, #SMC_UNK |
Anthony Steinhauser | 0f7e601 | 2020-01-07 15:44:06 -0800 | [diff] [blame] | 471 | exception_return |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 472 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 473 | #if DEBUG |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 474 | rt_svc_fw_critical_error: |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 475 | /* Switch to SP_ELx */ |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 476 | msr spsel, #MODE_SP_ELX |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 477 | no_ret report_unhandled_exception |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 478 | #endif |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 479 | endfunc smc_handler |
Justin Chadwell | 83e0488 | 2019-08-20 11:01:52 +0100 | [diff] [blame] | 480 | |
| 481 | /* --------------------------------------------------------------------- |
| 482 | * The following code handles exceptions caused by BRK instructions. |
| 483 | * Following a BRK instruction, the only real valid cause of action is |
| 484 | * to print some information and panic, as the code that caused it is |
| 485 | * likely in an inconsistent internal state. |
| 486 | * |
| 487 | * This is initially intended to be used in conjunction with |
| 488 | * __builtin_trap. |
| 489 | * --------------------------------------------------------------------- |
| 490 | */ |
| 491 | #ifdef MONITOR_TRAPS |
| 492 | func brk_handler |
| 493 | /* Extract the ISS */ |
| 494 | mrs x10, esr_el3 |
| 495 | ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH |
| 496 | |
| 497 | /* Ensure the console is initialized */ |
| 498 | bl plat_crash_console_init |
| 499 | |
| 500 | adr x4, brk_location |
| 501 | bl asm_print_str |
| 502 | mrs x4, elr_el3 |
| 503 | bl asm_print_hex |
| 504 | bl asm_print_newline |
| 505 | |
| 506 | adr x4, brk_message |
| 507 | bl asm_print_str |
| 508 | mov x4, x10 |
| 509 | mov x5, #28 |
| 510 | bl asm_print_hex_bits |
| 511 | bl asm_print_newline |
| 512 | |
| 513 | no_ret plat_panic_handler |
| 514 | endfunc brk_handler |
| 515 | #endif /* MONITOR_TRAPS */ |