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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Madhukar Pappireddyf4e6ea62020-01-27 15:32:15 -06002 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
Achin Gupta4f6ad662013-10-25 09:08:21 +01009#include <arch.h>
Dan Handley714a0d22014-04-09 13:13:04 +010010#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <bl31/ea_handle.h>
12#include <bl31/interrupt_mgmt.h>
13#include <common/runtime_svc.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010014#include <context.h>
Manish V Badarkhee07e8082020-07-23 12:43:25 +010015#include <el3_common_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <lib/el3_runtime/cpu_data.h>
17#include <lib/smccc.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010018
19 .globl runtime_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010020
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000021 .globl sync_exception_sp_el0
22 .globl irq_sp_el0
23 .globl fiq_sp_el0
24 .globl serror_sp_el0
25
26 .globl sync_exception_sp_elx
27 .globl irq_sp_elx
28 .globl fiq_sp_elx
29 .globl serror_sp_elx
30
31 .globl sync_exception_aarch64
32 .globl irq_aarch64
33 .globl fiq_aarch64
34 .globl serror_aarch64
35
36 .globl sync_exception_aarch32
37 .globl irq_aarch32
38 .globl fiq_aarch32
39 .globl serror_aarch32
40
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +000041 /*
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010042 * Macro that prepares entry to EL3 upon taking an exception.
43 *
44 * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB
45 * instruction. When an error is thus synchronized, the handling is
46 * delegated to platform EA handler.
47 *
48 * Without RAS_EXTENSION, this macro just saves x30, and unmasks
49 * Asynchronous External Aborts.
50 */
51 .macro check_and_unmask_ea
52#if RAS_EXTENSION
53 /* Synchronize pending External Aborts */
54 esb
55
56 /* Unmask the SError interrupt */
57 msr daifclr, #DAIF_ABT_BIT
58
59 /*
60 * Explicitly save x30 so as to free up a register and to enable
61 * branching
62 */
63 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
64
65 /* Check for SErrors synchronized by the ESB instruction */
66 mrs x30, DISR_EL1
67 tbz x30, #DISR_A_BIT, 1f
68
Alexei Fedorov503bbf32019-08-13 15:17:53 +010069 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +010070 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
71 * If Secure Cycle Counter is not disabled in MDCR_EL3 when
72 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
Alexei Fedorov503bbf32019-08-13 15:17:53 +010073 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +010074 bl save_gp_pmcr_pauth_regs
Alexei Fedorov503bbf32019-08-13 15:17:53 +010075
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010076 bl handle_lower_el_ea_esb
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010077
Alexei Fedorovf41355c2019-09-13 14:11:59 +010078 /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */
79 bl restore_gp_pmcr_pauth_regs
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100801:
81#else
82 /* Unmask the SError interrupt */
83 msr daifclr, #DAIF_ABT_BIT
84
85 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
86#endif
87 .endm
88
Douglas Raillard0980eed2016-11-09 17:48:27 +000089 /* ---------------------------------------------------------------------
90 * This macro handles Synchronous exceptions.
91 * Only SMC exceptions are supported.
92 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +010093 */
94 .macro handle_sync_exception
dp-arm3cac7862016-09-19 11:18:44 +010095#if ENABLE_RUNTIME_INSTRUMENTATION
dp-arm3cac7862016-09-19 11:18:44 +010096 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +000097 * Read the timestamp value and store it in per-cpu data. The value
98 * will be extracted from per-cpu data by the C level SMC handler and
99 * saved to the PMF timestamp region.
dp-arm3cac7862016-09-19 11:18:44 +0100100 */
101 mrs x30, cntpct_el0
102 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
103 mrs x29, tpidr_el3
104 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
105 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
106#endif
107
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100108 mrs x30, esr_el3
109 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
110
Douglas Raillard0980eed2016-11-09 17:48:27 +0000111 /* Handle SMC exceptions separately from other synchronous exceptions */
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100112 cmp x30, #EC_AARCH32_SMC
113 b.eq smc_handler32
114
115 cmp x30, #EC_AARCH64_SMC
116 b.eq smc_handler64
117
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100118 /* Synchronous exceptions other than the above are assumed to be EA */
Julius Werner67ebde72017-07-27 14:59:34 -0700119 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100120 b enter_lower_el_sync_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100121 .endm
122
123
Douglas Raillard0980eed2016-11-09 17:48:27 +0000124 /* ---------------------------------------------------------------------
125 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
126 * interrupts.
127 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100128 */
129 .macro handle_interrupt_exception label
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000130
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100131 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100132 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
133 * If Secure Cycle Counter is not disabled in MDCR_EL3 when
134 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100135 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100136 bl save_gp_pmcr_pauth_regs
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100137
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000138#if ENABLE_PAUTH
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100139 /* Load and program APIAKey firmware key */
140 bl pauth_load_bl31_apiakey
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000141#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000142
Douglas Raillard0980eed2016-11-09 17:48:27 +0000143 /* Save the EL3 system registers needed to return from this exception */
Achin Gupta979992e2015-05-13 17:57:18 +0100144 mrs x0, spsr_el3
145 mrs x1, elr_el3
146 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
147
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100148 /* Switch to the runtime stack i.e. SP_EL0 */
149 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
150 mov x20, sp
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100151 msr spsel, #MODE_SP_EL0
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100152 mov sp, x2
153
154 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000155 * Find out whether this is a valid interrupt type.
156 * If the interrupt controller reports a spurious interrupt then return
157 * to where we came from.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100158 */
Dan Handley701fea72014-05-27 16:17:21 +0100159 bl plat_ic_get_pending_interrupt_type
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100160 cmp x0, #INTR_TYPE_INVAL
161 b.eq interrupt_exit_\label
162
163 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000164 * Get the registered handler for this interrupt type.
165 * A NULL return value could be 'cause of the following conditions:
Achin Gupta979992e2015-05-13 17:57:18 +0100166 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000167 * a. An interrupt of a type was routed correctly but a handler for its
168 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100169 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000170 * b. An interrupt of a type was not routed correctly so a handler for
171 * its type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100172 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000173 * c. An interrupt of a type was routed correctly to EL3, but was
174 * deasserted before its pending state could be read. Another
175 * interrupt of a different type pended at the same time and its
176 * type was reported as pending instead. However, a handler for this
177 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100178 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000179 * a. and b. can only happen due to a programming error. The
180 * occurrence of c. could be beyond the control of Trusted Firmware.
181 * It makes sense to return from this exception instead of reporting an
182 * error.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100183 */
184 bl get_interrupt_type_handler
Achin Gupta979992e2015-05-13 17:57:18 +0100185 cbz x0, interrupt_exit_\label
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100186 mov x21, x0
187
188 mov x0, #INTR_ID_UNAVAILABLE
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100189
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100190 /* Set the current security state in the 'flags' parameter */
191 mrs x2, scr_el3
192 ubfx x1, x2, #0, #1
193
194 /* Restore the reference to the 'handle' i.e. SP_EL3 */
195 mov x2, x20
196
Douglas Raillard0980eed2016-11-09 17:48:27 +0000197 /* x3 will point to a cookie (not used now) */
Soby Mathew799f0ab2014-05-27 16:54:31 +0100198 mov x3, xzr
199
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100200 /* Call the interrupt type handler */
201 blr x21
202
203interrupt_exit_\label:
204 /* Return from exception, possibly in a different security state */
205 b el3_exit
206
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100207 .endm
208
209
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100210vector_base runtime_exceptions
211
Douglas Raillard0980eed2016-11-09 17:48:27 +0000212 /* ---------------------------------------------------------------------
213 * Current EL with SP_EL0 : 0x0 - 0x200
214 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100215 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100216vector_entry sync_exception_sp_el0
Justin Chadwell83e04882019-08-20 11:01:52 +0100217#ifdef MONITOR_TRAPS
218 stp x29, x30, [sp, #-16]!
219
220 mrs x30, esr_el3
221 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
222
223 /* Check for BRK */
224 cmp x30, #EC_BRK
225 b.eq brk_handler
226
227 ldp x29, x30, [sp], #16
228#endif /* MONITOR_TRAPS */
229
Douglas Raillard0980eed2016-11-09 17:48:27 +0000230 /* We don't expect any synchronous exceptions from EL3 */
Julius Werner67ebde72017-07-27 14:59:34 -0700231 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100232end_vector_entry sync_exception_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100233
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100234vector_entry irq_sp_el0
Douglas Raillard0980eed2016-11-09 17:48:27 +0000235 /*
236 * EL3 code is non-reentrant. Any asynchronous exception is a serious
237 * error. Loop infinitely.
238 */
Julius Werner67ebde72017-07-27 14:59:34 -0700239 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100240end_vector_entry irq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100241
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100242
243vector_entry fiq_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -0700244 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100245end_vector_entry fiq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100246
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100247
248vector_entry serror_sp_el0
Jeenu Viswambharan911fcc92018-07-06 16:50:06 +0100249 no_ret plat_handle_el3_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100250end_vector_entry serror_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100251
Douglas Raillard0980eed2016-11-09 17:48:27 +0000252 /* ---------------------------------------------------------------------
253 * Current EL with SP_ELx: 0x200 - 0x400
254 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100255 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100256vector_entry sync_exception_sp_elx
Douglas Raillard0980eed2016-11-09 17:48:27 +0000257 /*
258 * This exception will trigger if anything went wrong during a previous
259 * exception entry or exit or while handling an earlier unexpected
260 * synchronous exception. There is a high probability that SP_EL3 is
261 * corrupted.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000262 */
Julius Werner67ebde72017-07-27 14:59:34 -0700263 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100264end_vector_entry sync_exception_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100265
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100266vector_entry irq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700267 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100268end_vector_entry irq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000269
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100270vector_entry fiq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700271 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100272end_vector_entry fiq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000273
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100274vector_entry serror_sp_elx
Jeenu Viswambharan911fcc92018-07-06 16:50:06 +0100275 no_ret plat_handle_el3_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100276end_vector_entry serror_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100277
Douglas Raillard0980eed2016-11-09 17:48:27 +0000278 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100279 * Lower EL using AArch64 : 0x400 - 0x600
Douglas Raillard0980eed2016-11-09 17:48:27 +0000280 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100281 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100282vector_entry sync_exception_aarch64
Douglas Raillard0980eed2016-11-09 17:48:27 +0000283 /*
284 * This exception vector will be the entry point for SMCs and traps
285 * that are unhandled at lower ELs most commonly. SP_EL3 should point
286 * to a valid cpu context where the general purpose and system register
287 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000288 */
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100289 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100290 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000291 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100292end_vector_entry sync_exception_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100293
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100294vector_entry irq_aarch64
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100295 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100296 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100297 handle_interrupt_exception irq_aarch64
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100298end_vector_entry irq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100299
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100300vector_entry fiq_aarch64
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100301 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100302 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100303 handle_interrupt_exception fiq_aarch64
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100304end_vector_entry fiq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100305
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100306vector_entry serror_aarch64
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100307 apply_at_speculative_wa
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000308 msr daifclr, #DAIF_ABT_BIT
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100309 b enter_lower_el_async_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100310end_vector_entry serror_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100311
Douglas Raillard0980eed2016-11-09 17:48:27 +0000312 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100313 * Lower EL using AArch32 : 0x600 - 0x800
Douglas Raillard0980eed2016-11-09 17:48:27 +0000314 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100315 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100316vector_entry sync_exception_aarch32
Douglas Raillard0980eed2016-11-09 17:48:27 +0000317 /*
318 * This exception vector will be the entry point for SMCs and traps
319 * that are unhandled at lower ELs most commonly. SP_EL3 should point
320 * to a valid cpu context where the general purpose and system register
321 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000322 */
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100323 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100324 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000325 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100326end_vector_entry sync_exception_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100327
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100328vector_entry irq_aarch32
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100329 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100330 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100331 handle_interrupt_exception irq_aarch32
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100332end_vector_entry irq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100333
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100334vector_entry fiq_aarch32
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100335 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100336 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100337 handle_interrupt_exception fiq_aarch32
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100338end_vector_entry fiq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100339
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100340vector_entry serror_aarch32
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100341 apply_at_speculative_wa
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000342 msr daifclr, #DAIF_ABT_BIT
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100343 b enter_lower_el_async_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100344end_vector_entry serror_aarch32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000345
Justin Chadwell83e04882019-08-20 11:01:52 +0100346#ifdef MONITOR_TRAPS
347 .section .rodata.brk_string, "aS"
348brk_location:
349 .asciz "Error at instruction 0x"
350brk_message:
351 .asciz "Unexpected BRK instruction with value 0x"
352#endif /* MONITOR_TRAPS */
353
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100354 /* ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000355 * The following code handles secure monitor calls.
Douglas Raillard0980eed2016-11-09 17:48:27 +0000356 * Depending upon the execution state from where the SMC has been
357 * invoked, it frees some general purpose registers to perform the
358 * remaining tasks. They involve finding the runtime service handler
359 * that is the target of the SMC & switching to runtime stacks (SP_EL0)
360 * before calling the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000361 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000362 * Note that x30 has been explicitly saved and can be used here
363 * ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000364 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000365func smc_handler
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000366smc_handler32:
367 /* Check whether aarch32 issued an SMC64 */
368 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
369
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000370smc_handler64:
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000371 /* NOTE: The code below must preserve x0-x4 */
372
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100373 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100374 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
375 * If Secure Cycle Counter is not disabled in MDCR_EL3 when
376 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100377 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100378 bl save_gp_pmcr_pauth_regs
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100379
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000380#if ENABLE_PAUTH
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100381 /* Load and program APIAKey firmware key */
382 bl pauth_load_bl31_apiakey
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000383#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000384
Douglas Raillard0980eed2016-11-09 17:48:27 +0000385 /*
386 * Populate the parameters for the SMC handler.
387 * We already have x0-x4 in place. x5 will point to a cookie (not used
388 * now). x6 will point to the context structure (SP_EL3) and x7 will
Dimitris Papastamos04159512018-01-22 11:53:04 +0000389 * contain flags we need to pass to the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000390 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000391 mov x5, xzr
392 mov x6, sp
393
Douglas Raillard0980eed2016-11-09 17:48:27 +0000394 /*
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100395 * Restore the saved C runtime stack value which will become the new
396 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
397 * structure prior to the last ERET from EL3.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000398 */
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100399 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
400
401 /* Switch to SP_EL0 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100402 msr spsel, #MODE_SP_EL0
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000403
Douglas Raillard0980eed2016-11-09 17:48:27 +0000404 /*
405 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world
406 * switch during SMC handling.
407 * TODO: Revisit if all system registers can be saved later.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000408 */
409 mrs x16, spsr_el3
410 mrs x17, elr_el3
411 mrs x18, scr_el3
412 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
Achin Guptae1aa5162014-06-26 09:58:52 +0100413 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000414
415 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
416 bfi x7, x18, #0, #1
417
418 mov sp, x12
419
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500420 /* Get the unique owning entity number */
421 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
422 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
423 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
424
425 /* Load descriptor index from array of indices */
Madhukar Pappireddyf4e6ea62020-01-27 15:32:15 -0600426 adrp x14, rt_svc_descs_indices
427 add x14, x14, :lo12:rt_svc_descs_indices
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500428 ldrb w15, [x14, x16]
429
430 /* Any index greater than 127 is invalid. Check bit 7. */
431 tbnz w15, 7, smc_unknown
432
Douglas Raillard0980eed2016-11-09 17:48:27 +0000433 /*
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500434 * Get the descriptor using the index
435 * x11 = (base + off), w15 = index
436 *
437 * handler = (base + off) + (index << log2(size))
438 */
439 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
440 lsl w10, w15, #RT_SVC_SIZE_LOG2
441 ldr x15, [x11, w10, uxtw]
442
443 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000444 * Call the Secure Monitor Call handler and then drop directly into
445 * el3_exit() which will program any remaining architectural state
446 * prior to issuing the ERET to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000447 */
448#if DEBUG
449 cbz x15, rt_svc_fw_critical_error
450#endif
451 blr x15
452
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100453 b el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +0100454
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000455smc_unknown:
456 /*
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500457 * Unknown SMC call. Populate return value with SMC_UNK and call
458 * el3_exit() which will restore the remaining architectural state
459 * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET
460 * to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000461 */
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000462 mov x0, #SMC_UNK
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500463 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
464 b el3_exit
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000465
466smc_prohibited:
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100467 restore_ptw_el1_sys_regs
468 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
Soby Mathew6c5192a2014-04-30 15:36:37 +0100469 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000470 mov x0, #SMC_UNK
Anthony Steinhauser0f7e6012020-01-07 15:44:06 -0800471 exception_return
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000472
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100473#if DEBUG
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000474rt_svc_fw_critical_error:
Douglas Raillard0980eed2016-11-09 17:48:27 +0000475 /* Switch to SP_ELx */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100476 msr spsel, #MODE_SP_ELX
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000477 no_ret report_unhandled_exception
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100478#endif
Kévin Petita877c252015-03-24 14:03:57 +0000479endfunc smc_handler
Justin Chadwell83e04882019-08-20 11:01:52 +0100480
481 /* ---------------------------------------------------------------------
482 * The following code handles exceptions caused by BRK instructions.
483 * Following a BRK instruction, the only real valid cause of action is
484 * to print some information and panic, as the code that caused it is
485 * likely in an inconsistent internal state.
486 *
487 * This is initially intended to be used in conjunction with
488 * __builtin_trap.
489 * ---------------------------------------------------------------------
490 */
491#ifdef MONITOR_TRAPS
492func brk_handler
493 /* Extract the ISS */
494 mrs x10, esr_el3
495 ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH
496
497 /* Ensure the console is initialized */
498 bl plat_crash_console_init
499
500 adr x4, brk_location
501 bl asm_print_str
502 mrs x4, elr_el3
503 bl asm_print_hex
504 bl asm_print_newline
505
506 adr x4, brk_message
507 bl asm_print_str
508 mov x4, x10
509 mov x5, #28
510 bl asm_print_hex_bits
511 bl asm_print_newline
512
513 no_ret plat_panic_handler
514endfunc brk_handler
515#endif /* MONITOR_TRAPS */