Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __TEGRA_DEF_H__ |
| 32 | #define __TEGRA_DEF_H__ |
| 33 | |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 34 | /******************************************************************************* |
Varun Wadekar | acf1cad | 2016-12-12 14:24:17 -0800 | [diff] [blame] | 35 | * MCE apertures used by the ARI interface |
| 36 | * |
| 37 | * Aperture 0 - Cpu0 (ARM Cortex A-57) |
| 38 | * Aperture 1 - Cpu1 (ARM Cortex A-57) |
| 39 | * Aperture 2 - Cpu2 (ARM Cortex A-57) |
| 40 | * Aperture 3 - Cpu3 (ARM Cortex A-57) |
| 41 | * Aperture 4 - Cpu4 (Denver15) |
| 42 | * Aperture 5 - Cpu5 (Denver15) |
| 43 | ******************************************************************************/ |
| 44 | #define MCE_ARI_APERTURE_0_OFFSET 0x0 |
| 45 | #define MCE_ARI_APERTURE_1_OFFSET 0x10000 |
| 46 | #define MCE_ARI_APERTURE_2_OFFSET 0x20000 |
| 47 | #define MCE_ARI_APERTURE_3_OFFSET 0x30000 |
| 48 | #define MCE_ARI_APERTURE_4_OFFSET 0x40000 |
| 49 | #define MCE_ARI_APERTURE_5_OFFSET 0x50000 |
| 50 | #define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET |
| 51 | |
| 52 | /* number of apertures */ |
| 53 | #define MCE_ARI_APERTURES_MAX 6 |
| 54 | |
| 55 | /* each ARI aperture is 64KB */ |
| 56 | #define MCE_ARI_APERTURE_SIZE 0x10000 |
| 57 | |
| 58 | /******************************************************************************* |
| 59 | * CPU core id macros for the MCE_ONLINE_CORE ARI |
| 60 | ******************************************************************************/ |
| 61 | #define MCE_CORE_ID_MAX 8 |
| 62 | #define MCE_CORE_ID_MASK 0x7 |
| 63 | |
| 64 | /******************************************************************************* |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 65 | * These values are used by the PSCI implementation during the `CPU_SUSPEND` |
| 66 | * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' |
| 67 | * parameter. |
| 68 | ******************************************************************************/ |
| 69 | #define PSTATE_ID_CORE_IDLE 6 |
| 70 | #define PSTATE_ID_CORE_POWERDN 7 |
| 71 | #define PSTATE_ID_SOC_POWERDN 2 |
| 72 | |
| 73 | /******************************************************************************* |
| 74 | * Platform power states (used by PSCI framework) |
| 75 | * |
| 76 | * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID |
| 77 | * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 78 | ******************************************************************************/ |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 79 | #define PLAT_MAX_RET_STATE 1 |
| 80 | #define PLAT_MAX_OFF_STATE 8 |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 81 | |
| 82 | /******************************************************************************* |
| 83 | * Implementation defined ACTLR_EL3 bit definitions |
| 84 | ******************************************************************************/ |
| 85 | #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) |
| 86 | #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) |
| 87 | #define ACTLR_EL3_L2CTLR_BIT (1 << 4) |
| 88 | #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) |
| 89 | #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) |
| 90 | #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ |
| 91 | ACTLR_EL3_L2ECTLR_BIT | \ |
| 92 | ACTLR_EL3_L2CTLR_BIT | \ |
| 93 | ACTLR_EL3_CPUECTLR_BIT | \ |
| 94 | ACTLR_EL3_CPUACTLR_BIT) |
| 95 | |
| 96 | /******************************************************************************* |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 97 | * Secure IRQ definitions |
| 98 | ******************************************************************************/ |
| 99 | #define TEGRA186_TOP_WDT_IRQ 49 |
| 100 | #define TEGRA186_AON_WDT_IRQ 50 |
| 101 | |
| 102 | #define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */ |
| 103 | |
| 104 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 105 | * Tegra Miscellanous register constants |
| 106 | ******************************************************************************/ |
| 107 | #define TEGRA_MISC_BASE 0x00100000 |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 108 | #define HARDWARE_REVISION_OFFSET 0x4 |
Varun Wadekar | e2bc7f2 | 2016-04-02 15:41:20 -0700 | [diff] [blame] | 109 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 110 | #define MISCREG_PFCFG 0x200C |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 111 | |
| 112 | /******************************************************************************* |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 113 | * Tegra TSA Controller constants |
| 114 | ******************************************************************************/ |
| 115 | #define TEGRA_TSA_BASE 0x02400000 |
| 116 | |
| 117 | /******************************************************************************* |
Varun Wadekar | f5fc53f | 2016-12-15 11:54:51 -0800 | [diff] [blame] | 118 | * TSA configuration registers |
| 119 | ******************************************************************************/ |
| 120 | #define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010 |
| 121 | #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 |
| 122 | #define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038 |
| 123 | #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 |
| 124 | #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010 |
| 125 | #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 |
| 126 | #define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008 |
| 127 | #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 |
| 128 | #define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008 |
| 129 | #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100 |
| 130 | #define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018 |
| 131 | #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 |
| 132 | #define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018 |
| 133 | #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 |
| 134 | #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028 |
| 135 | #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 |
| 136 | #define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018 |
| 137 | #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 |
| 138 | #define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008 |
| 139 | #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 |
| 140 | #define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018 |
| 141 | #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 |
| 142 | #define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028 |
| 143 | #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 |
| 144 | #define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038 |
| 145 | #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 |
| 146 | #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008 |
| 147 | #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 |
| 148 | #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018 |
| 149 | #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 |
| 150 | |
| 151 | #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) |
| 152 | #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) |
| 153 | |
| 154 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 155 | * Tegra Memory Controller constants |
| 156 | ******************************************************************************/ |
| 157 | #define TEGRA_MC_STREAMID_BASE 0x02C00000 |
| 158 | #define TEGRA_MC_BASE 0x02C10000 |
| 159 | |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 160 | /* TZDRAM carveout configuration registers */ |
| 161 | #define MC_SECURITY_CFG0_0 0x70 |
| 162 | #define MC_SECURITY_CFG1_0 0x74 |
| 163 | #define MC_SECURITY_CFG3_0 0x9BC |
| 164 | |
| 165 | /* Video Memory carveout configuration registers */ |
| 166 | #define MC_VIDEO_PROTECT_BASE_HI 0x978 |
| 167 | #define MC_VIDEO_PROTECT_BASE_LO 0x648 |
| 168 | #define MC_VIDEO_PROTECT_SIZE_MB 0x64c |
| 169 | |
| 170 | /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ |
| 171 | #define MC_TZRAM_BASE_LO 0x2194 |
| 172 | #define TZRAM_BASE_LO_SHIFT 12 |
| 173 | #define TZRAM_BASE_LO_MASK 0xFFFFF |
| 174 | #define MC_TZRAM_BASE_HI 0x2198 |
| 175 | #define TZRAM_BASE_HI_SHIFT 0 |
| 176 | #define TZRAM_BASE_HI_MASK 3 |
| 177 | #define MC_TZRAM_SIZE 0x219C |
| 178 | #define TZRAM_SIZE_RANGE_4KB_SHIFT 27 |
| 179 | |
| 180 | #define MC_TZRAM_CARVEOUT_CFG 0x2190 |
| 181 | #define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1) |
| 182 | #define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0) |
| 183 | #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0 |
| 184 | #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4 |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 185 | #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8 |
| 186 | #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC |
| 187 | #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0 |
| 188 | #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4 |
| 189 | |
| 190 | #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8 |
| 191 | #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC |
| 192 | #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0 |
| 193 | #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4 |
| 194 | #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8 |
| 195 | #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC |
| 196 | |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 197 | /******************************************************************************* |
| 198 | * Tegra UART Controller constants |
| 199 | ******************************************************************************/ |
| 200 | #define TEGRA_UARTA_BASE 0x03100000 |
| 201 | #define TEGRA_UARTB_BASE 0x03110000 |
| 202 | #define TEGRA_UARTC_BASE 0x0C280000 |
| 203 | #define TEGRA_UARTD_BASE 0x03130000 |
| 204 | #define TEGRA_UARTE_BASE 0x03140000 |
| 205 | #define TEGRA_UARTF_BASE 0x03150000 |
| 206 | #define TEGRA_UARTG_BASE 0x0C290000 |
| 207 | |
| 208 | /******************************************************************************* |
Varun Wadekar | 4debe05 | 2016-05-18 13:39:16 -0700 | [diff] [blame] | 209 | * Tegra Fuse Controller related constants |
| 210 | ******************************************************************************/ |
| 211 | #define TEGRA_FUSE_BASE 0x03820000 |
| 212 | #define OPT_SUBREVISION 0x248 |
| 213 | #define SUBREVISION_MASK 0xFF |
| 214 | |
| 215 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 216 | * GICv2 & interrupt handling related constants |
| 217 | ******************************************************************************/ |
| 218 | #define TEGRA_GICD_BASE 0x03881000 |
| 219 | #define TEGRA_GICC_BASE 0x03882000 |
| 220 | |
| 221 | /******************************************************************************* |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 222 | * Security Engine related constants |
| 223 | ******************************************************************************/ |
| 224 | #define TEGRA_SE0_BASE 0x03AC0000 |
| 225 | #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C |
| 226 | #define TEGRA_PKA1_BASE 0x03AD0000 |
| 227 | #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 |
| 228 | #define TEGRA_RNG1_BASE 0x03AE0000 |
| 229 | #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 |
| 230 | |
| 231 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 232 | * Tegra Clock and Reset Controller constants |
| 233 | ******************************************************************************/ |
| 234 | #define TEGRA_CAR_RESET_BASE 0x05000000 |
| 235 | |
| 236 | /******************************************************************************* |
| 237 | * Tegra micro-seconds timer constants |
| 238 | ******************************************************************************/ |
| 239 | #define TEGRA_TMRUS_BASE 0x0C2E0000 |
| 240 | |
| 241 | /******************************************************************************* |
| 242 | * Tegra Power Mgmt Controller constants |
| 243 | ******************************************************************************/ |
| 244 | #define TEGRA_PMC_BASE 0x0C360000 |
| 245 | |
| 246 | /******************************************************************************* |
| 247 | * Tegra scratch registers constants |
| 248 | ******************************************************************************/ |
| 249 | #define TEGRA_SCRATCH_BASE 0x0C390000 |
Varun Wadekar | bd2b414 | 2016-12-12 16:46:44 -0800 | [diff] [blame] | 250 | #define SECURE_SCRATCH_RSV1_LO 0x658 |
| 251 | #define SECURE_SCRATCH_RSV1_HI 0x65C |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 252 | #define SECURE_SCRATCH_RSV6 0x680 |
| 253 | #define SECURE_SCRATCH_RSV11_LO 0x6A8 |
| 254 | #define SECURE_SCRATCH_RSV11_HI 0x6AC |
Varun Wadekar | 94701ff | 2016-05-23 11:47:34 -0700 | [diff] [blame] | 255 | #define SECURE_SCRATCH_RSV53_LO 0x7F8 |
| 256 | #define SECURE_SCRATCH_RSV53_HI 0x7FC |
Harvey Hsieh | c95802d | 2016-07-29 20:10:59 +0800 | [diff] [blame] | 257 | #define SECURE_SCRATCH_RSV54_HI 0x804 |
| 258 | #define SECURE_SCRATCH_RSV55_LO 0x808 |
| 259 | #define SECURE_SCRATCH_RSV55_HI 0x80C |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 260 | |
| 261 | /******************************************************************************* |
Varun Wadekar | d64db96 | 2016-09-23 14:28:16 -0700 | [diff] [blame] | 262 | * Tegra Memory Mapped Control Register Access constants |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 263 | ******************************************************************************/ |
| 264 | #define TEGRA_MMCRAB_BASE 0x0E000000 |
| 265 | |
| 266 | /******************************************************************************* |
Varun Wadekar | d64db96 | 2016-09-23 14:28:16 -0700 | [diff] [blame] | 267 | * Tegra Memory Mapped Activity Monitor Register Access constants |
| 268 | ******************************************************************************/ |
| 269 | #define TEGRA_ARM_ACTMON_CTR_BASE 0x0E060000 |
| 270 | #define TEGRA_DENVER_ACTMON_CTR_BASE 0x0E070000 |
| 271 | |
| 272 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 273 | * Tegra SMMU Controller constants |
| 274 | ******************************************************************************/ |
| 275 | #define TEGRA_SMMU_BASE 0x12000000 |
| 276 | |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 277 | /******************************************************************************* |
| 278 | * Tegra TZRAM constants |
| 279 | ******************************************************************************/ |
| 280 | #define TEGRA_TZRAM_BASE 0x30000000 |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 281 | #define TEGRA_TZRAM_SIZE 0x40000 |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 282 | |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 283 | #endif /* __TEGRA_DEF_H__ */ |