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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Alexei Fedorovd27febf2021-09-01 15:41:14 +01002 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2bd4ef22014-04-09 13:14:54 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <arch_helpers.h>
10#include <common/debug.h>
11#include <drivers/arm/gicv3.h>
Antonio Nino Diazf13d09a2019-01-23 21:50:09 +000012#include <drivers/arm/fvp/fvp_pwrc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <lib/extensions/spe.h>
14#include <lib/mmio.h>
15#include <lib/psci/psci.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000016#include <plat/arm/common/arm_config.h>
17#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +000018#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019
Dan Handleyed6ff952014-05-14 17:44:19 +010020#include "fvp_private.h"
Ambroise Vincentb237bca2019-02-13 15:58:00 +000021#include "../drivers/arm/gic/v3/gicv3_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010022
Dan Handley2b6b5742015-03-19 19:17:53 +000023
Soby Mathew7799cf72015-04-16 14:49:09 +010024#if ARM_RECOM_STATE_ID_ENC
25/*
26 * The table storing the valid idle power states. Ensure that the
27 * array entries are populated in ascending order of state-id to
28 * enable us to use binary search during power state validation.
29 * The table must be terminated by a NULL entry.
30 */
31const unsigned int arm_pm_idle_states[] = {
32 /* State-id - 0x01 */
33 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET,
34 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
35 /* State-id - 0x02 */
36 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
37 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
38 /* State-id - 0x22 */
39 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
40 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
Soby Mathew9ca28062017-10-11 16:08:58 +010041 /* State-id - 0x222 */
42 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
43 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
Soby Mathew7799cf72015-04-16 14:49:09 +010044 0,
45};
46#endif
47
Achin Gupta4f6ad662013-10-25 09:08:21 +010048/*******************************************************************************
Achin Gupta85876392014-07-31 17:45:51 +010049 * Function which implements the common FVP specific operations to power down a
Achin Gupta85876392014-07-31 17:45:51 +010050 * cluster in response to a CPU_OFF or CPU_SUSPEND request.
51 ******************************************************************************/
Sandrine Bailleuxa64a8542015-03-05 10:54:34 +000052static void fvp_cluster_pwrdwn_common(void)
Achin Gupta85876392014-07-31 17:45:51 +010053{
54 uint64_t mpidr = read_mpidr_el1();
55
dp-armee3457b2017-05-23 09:32:49 +010056#if ENABLE_SPE_FOR_LOWER_ELS
57 /*
58 * On power down we need to disable statistical profiling extensions
59 * before exiting coherency.
60 */
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010061 spe_disable();
dp-armee3457b2017-05-23 09:32:49 +010062#endif
63
Achin Gupta85876392014-07-31 17:45:51 +010064 /* Disable coherency if this cluster is to be turned off */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000065 fvp_interconnect_disable();
Achin Gupta85876392014-07-31 17:45:51 +010066
Madhukar Pappireddy90d65322019-10-30 14:24:39 -050067#if HW_ASSISTED_COHERENCY
68 uint32_t reg;
69
70 /*
71 * If we have determined this core to be the last man standing and we
72 * intend to power down the cluster proactively, we provide a hint to
73 * the power controller that cluster power is not required when all
74 * cores are powered down.
75 * Note that this is only an advisory to power controller and is supported
76 * by SoCs with DynamIQ Shared Units only.
77 */
78 reg = read_clusterpwrdn();
79
80 /* Clear and set bit 0 : Cluster power not required */
81 reg &= ~DSU_CLUSTER_PWR_MASK;
82 reg |= DSU_CLUSTER_PWR_OFF;
83 write_clusterpwrdn(reg);
84#endif
85
Achin Gupta85876392014-07-31 17:45:51 +010086 /* Program the power controller to turn the cluster off */
87 fvp_pwrc_write_pcoffr(mpidr);
88}
89
Soby Mathew9ca28062017-10-11 16:08:58 +010090/*
91 * Empty implementation of these hooks avoid setting the GICR_WAKER.Sleep bit
92 * on ARM GICv3 implementations on FVP. This is required, because FVP does not
93 * support SYSTEM_SUSPEND and it is `faked` in firmware. Hence, for wake up
94 * from `fake` system suspend the GIC must not be powered off.
95 */
Roberto Vargas1a6eed32018-02-12 12:36:17 +000096void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num)
Soby Mathew9ca28062017-10-11 16:08:58 +010097{}
98
Roberto Vargas1a6eed32018-02-12 12:36:17 +000099void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num)
Soby Mathew9ca28062017-10-11 16:08:58 +0100100{}
101
Soby Mathew12012dd2015-10-26 14:01:53 +0000102static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state)
103{
104 unsigned long mpidr;
105
106 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
107 ARM_LOCAL_STATE_OFF);
108
109 /* Get the mpidr for this cpu */
110 mpidr = read_mpidr_el1();
111
112 /* Perform the common cluster specific operations */
113 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
114 ARM_LOCAL_STATE_OFF) {
115 /*
116 * This CPU might have woken up whilst the cluster was
117 * attempting to power down. In this case the FVP power
118 * controller will have a pending cluster power off request
119 * which needs to be cleared by writing to the PPONR register.
120 * This prevents the power controller from interpreting a
121 * subsequent entry of this cpu into a simple wfi as a power
122 * down request.
123 */
124 fvp_pwrc_write_pponr(mpidr);
125
126 /* Enable coherency if this cluster was off */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000127 fvp_interconnect_enable();
Soby Mathew12012dd2015-10-26 14:01:53 +0000128 }
Soby Mathew9ca28062017-10-11 16:08:58 +0100129 /* Perform the common system specific operations */
130 if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
131 ARM_LOCAL_STATE_OFF)
132 arm_system_pwr_domain_resume();
Soby Mathew12012dd2015-10-26 14:01:53 +0000133
134 /*
135 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
136 * with a cpu power down unless the bit is set again
137 */
138 fvp_pwrc_clr_wen(mpidr);
139}
140
Achin Gupta85876392014-07-31 17:45:51 +0100141/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100142 * FVP handler called when a CPU is about to enter standby.
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000143 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000144static void fvp_cpu_standby(plat_local_state_t cpu_state)
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000145{
Alexei Fedorovd27febf2021-09-01 15:41:14 +0100146 u_register_t scr = read_scr_el3();
Soby Mathewfec4eb72015-07-01 16:16:20 +0100147
148 assert(cpu_state == ARM_LOCAL_STATE_RET);
149
Andrew Thoelke42e75a72014-04-28 12:28:39 +0100150 /*
Alexei Fedorovd27febf2021-09-01 15:41:14 +0100151 * Enable the Non-secure interrupt to wake the CPU.
152 * In GICv3 affinity routing mode, the Non-secure Group 1 interrupts
153 * use Physical FIQ at EL3 whereas in GICv2, Physical IRQ is used.
154 * Enabling both the bits works for both GICv2 mode and GICv3 affinity
155 * routing mode.
156 */
157 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
158 isb();
159
160 /*
161 * Enter standby state.
162 * dsb is good practice before using wfi to enter low power states.
Andrew Thoelke42e75a72014-04-28 12:28:39 +0100163 */
164 dsb();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000165 wfi();
Alexei Fedorovd27febf2021-09-01 15:41:14 +0100166
167 /*
168 * Restore SCR_EL3 to the original value, synchronisation of SCR_EL3
169 * is done by eret in el3_exit() to save some execution cycles.
170 */
171 write_scr_el3(scr);
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000172}
173
174/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100175 * FVP handler called when a power domain is about to be turned on. The
176 * mpidr determines the CPU to be turned on.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100177 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000178static int fvp_pwr_domain_on(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100179{
180 int rc = PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100181 unsigned int psysr;
182
Achin Gupta4f6ad662013-10-25 09:08:21 +0100183 /*
Sandrine Bailleux7175bde2015-12-08 14:18:24 +0000184 * Ensure that we do not cancel an inflight power off request for the
185 * target cpu. That would leave it in a zombie wfi. Wait for it to power
186 * off and then program the power controller to turn that CPU on.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100187 */
188 do {
189 psysr = fvp_pwrc_read_psysr(mpidr);
Sathees Balya50905c72018-10-05 13:30:59 +0100190 } while ((psysr & PSYSR_AFF_L0) != 0U);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100191
Achin Gupta4f6ad662013-10-25 09:08:21 +0100192 fvp_pwrc_write_pponr(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100193 return rc;
194}
195
196/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100197 * FVP handler called when a power domain is about to be turned off. The
198 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100199 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000200static void fvp_pwr_domain_off(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100201{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100202 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
203 ARM_LOCAL_STATE_OFF);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100204
Achin Gupta85876392014-07-31 17:45:51 +0100205 /*
Soby Mathewfec4eb72015-07-01 16:16:20 +0100206 * If execution reaches this stage then this power domain will be
207 * suspended. Perform at least the cpu specific actions followed
208 * by the cluster specific operations if applicable.
Achin Gupta85876392014-07-31 17:45:51 +0100209 */
Jeenu Viswambharan6ad35482016-12-09 11:14:34 +0000210
211 /* Prevent interrupts from spuriously waking up this cpu */
212 plat_arm_gic_cpuif_disable();
213
214 /* Turn redistributor off */
215 plat_arm_gic_redistif_off();
216
217 /* Program the power controller to power off this cpu. */
218 fvp_pwrc_write_ppoffr(read_mpidr_el1());
Achin Gupta4f6ad662013-10-25 09:08:21 +0100219
Soby Mathewfec4eb72015-07-01 16:16:20 +0100220 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
221 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100222 fvp_cluster_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100223
Achin Gupta4f6ad662013-10-25 09:08:21 +0100224}
225
226/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100227 * FVP handler called when a power domain is about to be suspended. The
228 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100229 ******************************************************************************/
Wing Li05364b92023-01-26 18:33:43 -0800230#if PSCI_OS_INIT_MODE
231static int fvp_pwr_domain_suspend(const psci_power_state_t *target_state)
232#else
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000233static void fvp_pwr_domain_suspend(const psci_power_state_t *target_state)
Wing Li05364b92023-01-26 18:33:43 -0800234#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100235{
Soby Mathewffb4ab12014-09-26 15:08:52 +0100236 unsigned long mpidr;
237
Soby Mathewfec4eb72015-07-01 16:16:20 +0100238 /*
239 * FVP has retention only at cpu level. Just return
240 * as nothing is to be done for retention.
241 */
242 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
243 ARM_LOCAL_STATE_RET)
Wing Li05364b92023-01-26 18:33:43 -0800244#if PSCI_OS_INIT_MODE
245 return PSCI_E_SUCCESS;
246#else
Soby Mathew74e52a72014-10-02 16:56:51 +0100247 return;
Wing Li05364b92023-01-26 18:33:43 -0800248#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100249
Soby Mathewfec4eb72015-07-01 16:16:20 +0100250 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
251 ARM_LOCAL_STATE_OFF);
252
Soby Mathewffb4ab12014-09-26 15:08:52 +0100253 /* Get the mpidr for this cpu */
254 mpidr = read_mpidr_el1();
255
Achin Gupta85876392014-07-31 17:45:51 +0100256 /* Program the power controller to enable wakeup interrupts. */
257 fvp_pwrc_set_wen(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100258
Jeenu Viswambharan6ad35482016-12-09 11:14:34 +0000259 /* Prevent interrupts from spuriously waking up this cpu */
260 plat_arm_gic_cpuif_disable();
261
262 /*
263 * The Redistributor is not powered off as it can potentially prevent
264 * wake up events reaching the CPUIF and/or might lead to losing
265 * register context.
266 */
267
Achin Gupta85876392014-07-31 17:45:51 +0100268 /* Perform the common cluster specific operations */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100269 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
270 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100271 fvp_cluster_pwrdwn_common();
Soby Mathew9ca28062017-10-11 16:08:58 +0100272
273 /* Perform the common system specific operations */
274 if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
275 ARM_LOCAL_STATE_OFF)
276 arm_system_pwr_domain_save();
277
278 /* Program the power controller to power off this cpu. */
279 fvp_pwrc_write_ppoffr(read_mpidr_el1());
Wing Li05364b92023-01-26 18:33:43 -0800280
281#if PSCI_OS_INIT_MODE
282 return PSCI_E_SUCCESS;
283#else
284 return;
285#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100286}
287
288/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100289 * FVP handler called when a power domain has just been powered on after
290 * being turned off earlier. The target_state encodes the low power state that
291 * each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100292 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000293static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100294{
Soby Mathew12012dd2015-10-26 14:01:53 +0000295 fvp_power_domain_on_finish_common(target_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100296
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500297}
298
299/*******************************************************************************
300 * FVP handler called when a power domain has just been powered on and the cpu
301 * and its cluster are fully participating in coherent transaction on the
302 * interconnect. Data cache must be enabled for CPU at this point.
303 ******************************************************************************/
304static void fvp_pwr_domain_on_finish_late(const psci_power_state_t *target_state)
305{
306 /* Program GIC per-cpu distributor or re-distributor interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000307 plat_arm_gic_pcpu_init();
308
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500309 /* Enable GIC CPU interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000310 plat_arm_gic_cpuif_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100311}
312
313/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100314 * FVP handler called when a power domain has just been powered on after
315 * having been suspended earlier. The target_state encodes the low power state
316 * that each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100317 * TODO: At the moment we reuse the on finisher and reinitialize the secure
318 * context. Need to implement a separate suspend finisher.
319 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000320static void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100321{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100322 /*
323 * Nothing to be done on waking up from retention from CPU level.
324 */
325 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
326 ARM_LOCAL_STATE_RET)
327 return;
328
Soby Mathew12012dd2015-10-26 14:01:53 +0000329 fvp_power_domain_on_finish_common(target_state);
330
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500331 /* Enable GIC CPU interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000332 plat_arm_gic_cpuif_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100333}
334
Juan Castillo4dc4a472014-08-12 11:17:06 +0100335/*******************************************************************************
336 * FVP handlers to shutdown/reboot the system
337 ******************************************************************************/
338static void __dead2 fvp_system_off(void)
339{
340 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000341 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
342 V2M_CFGCTRL_START |
343 V2M_CFGCTRL_RW |
344 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100345 wfi();
346 ERROR("FVP System Off: operation not handled.\n");
347 panic();
348}
349
350static void __dead2 fvp_system_reset(void)
351{
352 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000353 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
354 V2M_CFGCTRL_START |
355 V2M_CFGCTRL_RW |
356 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100357 wfi();
358 ERROR("FVP System Reset: operation not handled.\n");
359 panic();
360}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100361
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100362static int fvp_node_hw_state(u_register_t target_cpu,
363 unsigned int power_level)
364{
365 unsigned int psysr;
366 int ret;
367
368 /*
369 * The format of 'power_level' is implementation-defined, but 0 must
370 * mean a CPU. We also allow 1 to denote the cluster
371 */
Sathees Balya50905c72018-10-05 13:30:59 +0100372 if ((power_level != ARM_PWR_LVL0) && (power_level != ARM_PWR_LVL1))
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100373 return PSCI_E_INVALID_PARAMS;
374
375 /*
376 * Read the status of the given MPDIR from FVP power controller. The
377 * power controller only gives us on/off status, so map that to expected
378 * return values of the PSCI call
379 */
380 psysr = fvp_pwrc_read_psysr(target_cpu);
381 if (psysr == PSYSR_INVALID)
382 return PSCI_E_INVALID_PARAMS;
383
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000384 if (power_level == ARM_PWR_LVL0) {
Sathees Balya50905c72018-10-05 13:30:59 +0100385 ret = ((psysr & PSYSR_AFF_L0) != 0U) ? HW_ON : HW_OFF;
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000386 } else {
387 /* power_level == ARM_PWR_LVL1 */
Sathees Balya50905c72018-10-05 13:30:59 +0100388 ret = ((psysr & PSYSR_AFF_L1) != 0U) ? HW_ON : HW_OFF;
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100389 }
390
391 return ret;
392}
393
Soby Mathew9ca28062017-10-11 16:08:58 +0100394/*
395 * The FVP doesn't truly support power management at SYSTEM power domain. The
396 * SYSTEM_SUSPEND will be down-graded to the cluster level within the platform
397 * layer. The `fake` SYSTEM_SUSPEND allows us to validate some of the driver
398 * save and restore sequences on FVP.
399 */
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000400#if !ARM_BL31_IN_DRAM
401static void fvp_get_sys_suspend_power_state(psci_power_state_t *req_state)
Soby Mathew9ca28062017-10-11 16:08:58 +0100402{
403 unsigned int i;
404
405 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
406 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF;
407}
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000408#endif
Soby Mathew9ca28062017-10-11 16:08:58 +0100409
Achin Gupta4f6ad662013-10-25 09:08:21 +0100410/*******************************************************************************
Soby Mathew9ca28062017-10-11 16:08:58 +0100411 * Handler to filter PSCI requests.
412 ******************************************************************************/
413/*
414 * The system power domain suspend is only supported only via
415 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain
416 * will be downgraded to the lower level.
417 */
418static int fvp_validate_power_state(unsigned int power_state,
419 psci_power_state_t *req_state)
420{
421 int rc;
422 rc = arm_validate_power_state(power_state, req_state);
423
424 /*
425 * Ensure that the system power domain level is never suspended
426 * via PSCI CPU SUSPEND API. Currently system suspend is only
427 * supported via PSCI SYSTEM SUSPEND API.
428 */
429 req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN;
430 return rc;
431}
432
433/*
434 * Custom `translate_power_state_by_mpidr` handler for FVP. Unlike in the
435 * `fvp_validate_power_state`, we do not downgrade the system power
436 * domain level request in `power_state` as it will be used to query the
437 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level.
438 */
439static int fvp_translate_power_state_by_mpidr(u_register_t mpidr,
440 unsigned int power_state,
441 psci_power_state_t *output_state)
442{
443 return arm_validate_power_state(power_state, output_state);
444}
445
446/*******************************************************************************
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100447 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
448 * platform layer will take care of registering the handlers with PSCI.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100449 ******************************************************************************/
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100450plat_psci_ops_t plat_arm_psci_pm_ops = {
Soby Mathewfec4eb72015-07-01 16:16:20 +0100451 .cpu_standby = fvp_cpu_standby,
452 .pwr_domain_on = fvp_pwr_domain_on,
453 .pwr_domain_off = fvp_pwr_domain_off,
454 .pwr_domain_suspend = fvp_pwr_domain_suspend,
455 .pwr_domain_on_finish = fvp_pwr_domain_on_finish,
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500456 .pwr_domain_on_finish_late = fvp_pwr_domain_on_finish_late,
Soby Mathewfec4eb72015-07-01 16:16:20 +0100457 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish,
Juan Castillo4dc4a472014-08-12 11:17:06 +0100458 .system_off = fvp_system_off,
Soby Mathew74e52a72014-10-02 16:56:51 +0100459 .system_reset = fvp_system_reset,
Soby Mathew9ca28062017-10-11 16:08:58 +0100460 .validate_power_state = fvp_validate_power_state,
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100461 .validate_ns_entrypoint = arm_validate_psci_entrypoint,
Soby Mathew9ca28062017-10-11 16:08:58 +0100462 .translate_power_state_by_mpidr = fvp_translate_power_state_by_mpidr,
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100463 .get_node_hw_state = fvp_node_hw_state,
Antonio Nino Diaz0b6af832017-11-22 12:00:44 +0000464#if !ARM_BL31_IN_DRAM
465 /*
466 * The TrustZone Controller is set up during the warmboot sequence after
467 * resuming the CPU from a SYSTEM_SUSPEND. If BL31 is located in SRAM
468 * this is not a problem but, if it is in TZC-secured DRAM, it tries to
469 * reconfigure the same memory it is running on, causing an exception.
470 */
Soby Mathew9ca28062017-10-11 16:08:58 +0100471 .get_sys_suspend_power_state = fvp_get_sys_suspend_power_state,
Antonio Nino Diaz0b6af832017-11-22 12:00:44 +0000472#endif
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100473 .mem_protect_chk = arm_psci_mem_protect_chk,
474 .read_mem_protect = arm_psci_read_mem_protect,
475 .write_mem_protect = arm_nor_psci_write_mem_protect,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100476};
Chandni Cherukurie4bf6a02018-11-14 13:43:59 +0530477
478const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
479{
480 return ops;
481}