Hadi Asyrafi | ab1132f | 2019-10-22 10:31:45 +0800 | [diff] [blame] | 1 | /* |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. |
Hadi Asyrafi | ab1132f | 2019-10-22 10:31:45 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SOCFPGA_SIP_SVC_H |
| 8 | #define SOCFPGA_SIP_SVC_H |
| 9 | |
| 10 | |
| 11 | /* SiP status response */ |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 12 | #define INTEL_SIP_SMC_STATUS_OK 0 |
| 13 | #define INTEL_SIP_SMC_STATUS_BUSY 0x1 |
| 14 | #define INTEL_SIP_SMC_STATUS_REJECTED 0x2 |
| 15 | #define INTEL_SIP_SMC_STATUS_NO_RESPONSE 0x3 |
| 16 | #define INTEL_SIP_SMC_STATUS_ERROR 0x4 |
| 17 | #define INTEL_SIP_SMC_RSU_ERROR 0x7 |
Abdul Halim, Muhammad Hadi Asyrafi | 25f623e | 2020-02-27 10:23:48 +0800 | [diff] [blame] | 18 | |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 19 | /* SiP mailbox error code */ |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 20 | #define GENERIC_RESPONSE_ERROR 0x3FF |
Hadi Asyrafi | ab1132f | 2019-10-22 10:31:45 +0800 | [diff] [blame] | 21 | |
Sieu Mun Tang | 044ed48 | 2022-05-11 10:45:19 +0800 | [diff] [blame^] | 22 | /* SiP V2 command code range */ |
| 23 | #define INTEL_SIP_SMC_CMD_MASK 0xFFFF |
| 24 | #define INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN 0x400 |
| 25 | #define INTEL_SIP_SMC_CMD_V2_RANGE_END 0x4FF |
| 26 | |
| 27 | /* SMC SiP service function identifier for version 1 */ |
Abdul Halim, Muhammad Hadi Asyrafi | ec164b6 | 2020-05-14 14:53:29 +0800 | [diff] [blame] | 28 | |
| 29 | /* FPGA Reconfig */ |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 30 | #define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001 |
| 31 | #define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002 |
| 32 | #define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003 |
| 33 | #define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004 |
| 34 | #define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005 |
Abdul Halim, Muhammad Hadi Asyrafi | ec164b6 | 2020-05-14 14:53:29 +0800 | [diff] [blame] | 35 | |
Sieu Mun Tang | 5406498 | 2022-04-28 22:40:58 +0800 | [diff] [blame] | 36 | /* FPGA Bitstream Flag */ |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 37 | #define FLAG_PARTIAL_CONFIG BIT(0) |
| 38 | #define FLAG_AUTHENTICATION BIT(1) |
| 39 | #define CONFIG_TEST_FLAG(_flag, _type) (((flag) & FLAG_##_type) \ |
| 40 | == FLAG_##_type) |
Sieu Mun Tang | 5406498 | 2022-04-28 22:40:58 +0800 | [diff] [blame] | 41 | |
Abdul Halim, Muhammad Hadi Asyrafi | ec164b6 | 2020-05-14 14:53:29 +0800 | [diff] [blame] | 42 | /* Secure Register Access */ |
Hadi Asyrafi | ab1132f | 2019-10-22 10:31:45 +0800 | [diff] [blame] | 43 | #define INTEL_SIP_SMC_REG_READ 0xC2000007 |
| 44 | #define INTEL_SIP_SMC_REG_WRITE 0xC2000008 |
| 45 | #define INTEL_SIP_SMC_REG_UPDATE 0xC2000009 |
Abdul Halim, Muhammad Hadi Asyrafi | ec164b6 | 2020-05-14 14:53:29 +0800 | [diff] [blame] | 46 | |
| 47 | /* Remote System Update */ |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 48 | #define INTEL_SIP_SMC_RSU_STATUS 0xC200000B |
| 49 | #define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C |
| 50 | #define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E |
| 51 | #define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F |
| 52 | #define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010 |
| 53 | #define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011 |
| 54 | #define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012 |
| 55 | #define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013 |
| 56 | #define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014 |
| 57 | #define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015 |
Abdul Halim, Muhammad Hadi Asyrafi | ec164b6 | 2020-05-14 14:53:29 +0800 | [diff] [blame] | 58 | |
Kris Chaplin | e768dfa | 2021-06-25 11:31:52 +0100 | [diff] [blame] | 59 | /* Hardware monitor */ |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 60 | #define INTEL_SIP_SMC_HWMON_READTEMP 0xC2000020 |
| 61 | #define INTEL_SIP_SMC_HWMON_READVOLT 0xC2000021 |
| 62 | #define TEMP_CHANNEL_MAX (1 << 15) |
| 63 | #define VOLT_CHANNEL_MAX (1 << 15) |
Sieu Mun Tang | dbcc2cf | 2022-03-07 12:13:04 +0800 | [diff] [blame] | 64 | |
| 65 | /* ECC */ |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 66 | #define INTEL_SIP_SMC_ECC_DBE 0xC200000D |
Sieu Mun Tang | dbcc2cf | 2022-03-07 12:13:04 +0800 | [diff] [blame] | 67 | |
Sieu Mun Tang | a34b881 | 2022-03-17 03:11:55 +0800 | [diff] [blame] | 68 | /* Generic Command */ |
Sieu Mun Tang | 758a2ad | 2022-05-11 10:23:13 +0800 | [diff] [blame] | 69 | #define INTEL_SIP_SMC_SERVICE_COMPLETED 0xC200001E |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 70 | #define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F |
| 71 | #define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032 |
| 72 | #define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040 |
Sieu Mun Tang | a34b881 | 2022-03-17 03:11:55 +0800 | [diff] [blame] | 73 | |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 74 | #define SERVICE_COMPLETED_MODE_ASYNC 0x00004F4E |
Sieu Mun Tang | fd8a8ad | 2022-05-07 00:50:37 +0800 | [diff] [blame] | 75 | |
Sieu Mun Tang | 2b8e005 | 2022-04-27 18:57:29 +0800 | [diff] [blame] | 76 | /* Mailbox Command */ |
Sieu Mun Tang | 758a2ad | 2022-05-11 10:23:13 +0800 | [diff] [blame] | 77 | #define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200003C |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 78 | #define INTEL_SIP_SMC_GET_USERCODE 0xC200003D |
Abdul Halim, Muhammad Hadi Asyrafi | ec164b6 | 2020-05-14 14:53:29 +0800 | [diff] [blame] | 79 | |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame] | 80 | /* FPGA Crypto Services */ |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 81 | #define INTEL_SIP_SMC_FCS_RANDOM_NUMBER 0xC200005A |
| 82 | #define INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT 0x4200008F |
| 83 | #define INTEL_SIP_SMC_FCS_CRYPTION 0x4200005B |
| 84 | #define INTEL_SIP_SMC_FCS_CRYPTION_EXT 0xC2000090 |
Sieu Mun Tang | 59357e8 | 2022-05-10 17:53:32 +0800 | [diff] [blame] | 85 | #define INTEL_SIP_SMC_FCS_SERVICE_REQUEST 0x4200005C |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 86 | #define INTEL_SIP_SMC_FCS_SEND_CERTIFICATE 0x4200005D |
Sieu Mun Tang | 758a2ad | 2022-05-11 10:23:13 +0800 | [diff] [blame] | 87 | #define INTEL_SIP_SMC_FCS_GET_PROVISION_DATA 0x4200005E |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 88 | #define INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH 0xC200005F |
| 89 | #define INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN 0xC2000064 |
| 90 | #define INTEL_SIP_SMC_FCS_CHIP_ID 0xC2000065 |
| 91 | #define INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY 0xC2000066 |
| 92 | #define INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS 0xC2000067 |
| 93 | #define INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT 0xC2000068 |
| 94 | #define INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD 0xC2000069 |
| 95 | #define INTEL_SIP_SMC_FCS_OPEN_CS_SESSION 0xC200006E |
| 96 | #define INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION 0xC200006F |
| 97 | #define INTEL_SIP_SMC_FCS_IMPORT_CS_KEY 0x42000070 |
| 98 | #define INTEL_SIP_SMC_FCS_EXPORT_CS_KEY 0xC2000071 |
| 99 | #define INTEL_SIP_SMC_FCS_REMOVE_CS_KEY 0xC2000072 |
| 100 | #define INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO 0xC2000073 |
| 101 | #define INTEL_SIP_SMC_FCS_AES_CRYPT_INIT 0xC2000074 |
| 102 | #define INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE 0x42000076 |
| 103 | #define INTEL_SIP_SMC_FCS_GET_DIGEST_INIT 0xC2000077 |
| 104 | #define INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE 0xC2000079 |
| 105 | #define INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT 0xC200007A |
| 106 | #define INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE 0xC200007C |
Sieu Mun Tang | 8aa05ad | 2022-05-10 17:50:30 +0800 | [diff] [blame] | 107 | #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT 0xC200007D |
| 108 | #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE 0xC200007F |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 109 | #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT 0xC2000080 |
| 110 | #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE 0xC2000082 |
Sieu Mun Tang | 59357e8 | 2022-05-10 17:53:32 +0800 | [diff] [blame] | 111 | #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT 0xC2000083 |
| 112 | #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE 0xC2000085 |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 113 | #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT 0xC2000086 |
| 114 | #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE 0xC2000088 |
| 115 | #define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT 0xC2000089 |
| 116 | #define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE 0xC200008B |
Sieu Mun Tang | 0675c22 | 2022-05-10 17:48:11 +0800 | [diff] [blame] | 117 | #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT 0xC200008C |
| 118 | #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE 0xC200008E |
Abdul Halim, Muhammad Hadi Asyrafi | ec164b6 | 2020-05-14 14:53:29 +0800 | [diff] [blame] | 119 | |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 120 | #define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF |
| 121 | #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF |
| 122 | #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U |
| 123 | #define INTEL_SIP_SMC_FCS_ECC_ALGO_MASK 0xF |
| 124 | |
Sieu Mun Tang | dbcc2cf | 2022-03-07 12:13:04 +0800 | [diff] [blame] | 125 | /* ECC DBE */ |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 126 | #define WARM_RESET_WFI_FLAG BIT(31) |
| 127 | #define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\ |
Sieu Mun Tang | e7a037f | 2022-05-10 17:18:19 +0800 | [diff] [blame] | 128 | SYSMGR_ECC_DDR0_MASK |\ |
| 129 | SYSMGR_ECC_DDR1_MASK) |
Sieu Mun Tang | dbcc2cf | 2022-03-07 12:13:04 +0800 | [diff] [blame] | 130 | |
Sieu Mun Tang | f9cb657 | 2022-04-27 18:24:06 +0800 | [diff] [blame] | 131 | /* Non-mailbox SMC Call */ |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 132 | #define INTEL_SIP_SMC_SVC_VERSION 0xC2000200 |
Sieu Mun Tang | f9cb657 | 2022-04-27 18:24:06 +0800 | [diff] [blame] | 133 | |
Sieu Mun Tang | 044ed48 | 2022-05-11 10:45:19 +0800 | [diff] [blame^] | 134 | /** |
| 135 | * SMC SiP service function identifier for version 2 |
| 136 | * Command code from 0x400 ~ 0x4FF |
| 137 | */ |
| 138 | |
| 139 | /* V2: Non-mailbox function identifier */ |
| 140 | #define INTEL_SIP_SMC_V2_GET_SVC_VERSION 0xC2000400 |
| 141 | #define INTEL_SIP_SMC_V2_REG_READ 0xC2000401 |
| 142 | #define INTEL_SIP_SMC_V2_REG_WRITE 0xC2000402 |
| 143 | #define INTEL_SIP_SMC_V2_REG_UPDATE 0xC2000403 |
| 144 | #define INTEL_SIP_SMC_V2_HPS_SET_BRIDGES 0xC2000404 |
| 145 | |
Hadi Asyrafi | ab1132f | 2019-10-22 10:31:45 +0800 | [diff] [blame] | 146 | /* SMC function IDs for SiP Service queries */ |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 147 | #define SIP_SVC_CALL_COUNT 0x8200ff00 |
| 148 | #define SIP_SVC_UID 0x8200ff01 |
| 149 | #define SIP_SVC_VERSION 0x8200ff03 |
Hadi Asyrafi | ab1132f | 2019-10-22 10:31:45 +0800 | [diff] [blame] | 150 | |
| 151 | /* SiP Service Calls version numbers */ |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 152 | #define SIP_SVC_VERSION_MAJOR 1 |
| 153 | #define SIP_SVC_VERSION_MINOR 0 |
Hadi Asyrafi | ab1132f | 2019-10-22 10:31:45 +0800 | [diff] [blame] | 154 | |
Abdul Halim, Muhammad Hadi Asyrafi | 20a07f3 | 2020-05-18 11:16:48 +0800 | [diff] [blame] | 155 | |
| 156 | /* Structure Definitions */ |
| 157 | struct fpga_config_info { |
| 158 | uint32_t addr; |
| 159 | int size; |
| 160 | int size_written; |
| 161 | uint32_t write_requested; |
| 162 | int subblocks_sent; |
| 163 | int block_number; |
| 164 | }; |
| 165 | |
| 166 | /* Function Definitions */ |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame] | 167 | bool is_size_4_bytes_aligned(uint32_t size); |
Abdul Halim, Muhammad Hadi Asyrafi | 20a07f3 | 2020-05-18 11:16:48 +0800 | [diff] [blame] | 168 | bool is_address_in_ddr_range(uint64_t addr, uint64_t size); |
| 169 | |
Sieu Mun Tang | dbcc2cf | 2022-03-07 12:13:04 +0800 | [diff] [blame] | 170 | /* ECC DBE */ |
| 171 | bool cold_reset_for_ecc_dbe(void); |
| 172 | uint32_t intel_ecc_dbe_notification(uint64_t dbe_value); |
| 173 | |
Sieu Mun Tang | 044ed48 | 2022-05-11 10:45:19 +0800 | [diff] [blame^] | 174 | /* Secure register access */ |
| 175 | uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval); |
| 176 | uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, |
| 177 | uint32_t *retval); |
| 178 | uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, |
| 179 | uint32_t val, uint32_t *retval); |
| 180 | |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 181 | /* Miscellaneous HPS services */ |
| 182 | uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask); |
| 183 | |
Sieu Mun Tang | 044ed48 | 2022-05-11 10:45:19 +0800 | [diff] [blame^] | 184 | /* SiP Service handler for version 2 */ |
| 185 | uintptr_t sip_smc_handler_v2(uint32_t smc_fid, |
| 186 | u_register_t x1, |
| 187 | u_register_t x2, |
| 188 | u_register_t x3, |
| 189 | u_register_t x4, |
| 190 | void *cookie, |
| 191 | void *handle, |
| 192 | u_register_t flags); |
| 193 | |
Hadi Asyrafi | ab1132f | 2019-10-22 10:31:45 +0800 | [diff] [blame] | 194 | #endif /* SOCFPGA_SIP_SVC_H */ |