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Hadi Asyrafiab1132f2019-10-22 10:31:45 +08001/*
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +08002 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
Hadi Asyrafiab1132f2019-10-22 10:31:45 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef SOCFPGA_SIP_SVC_H
8#define SOCFPGA_SIP_SVC_H
9
10
11/* SiP status response */
Sieu Mun Tangdcaab772022-05-11 10:16:40 +080012#define INTEL_SIP_SMC_STATUS_OK 0
13#define INTEL_SIP_SMC_STATUS_BUSY 0x1
14#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
15#define INTEL_SIP_SMC_STATUS_NO_RESPONSE 0x3
16#define INTEL_SIP_SMC_STATUS_ERROR 0x4
17#define INTEL_SIP_SMC_RSU_ERROR 0x7
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +080018
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +080019/* SiP mailbox error code */
Sieu Mun Tangdcaab772022-05-11 10:16:40 +080020#define GENERIC_RESPONSE_ERROR 0x3FF
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080021
22/* SMC SiP service function identifier */
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080023
24/* FPGA Reconfig */
Sieu Mun Tangdcaab772022-05-11 10:16:40 +080025#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
26#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
27#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
28#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
29#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080030
Sieu Mun Tang54064982022-04-28 22:40:58 +080031/* FPGA Bitstream Flag */
Sieu Mun Tangdcaab772022-05-11 10:16:40 +080032#define FLAG_PARTIAL_CONFIG BIT(0)
33#define FLAG_AUTHENTICATION BIT(1)
34#define CONFIG_TEST_FLAG(_flag, _type) (((flag) & FLAG_##_type) \
35 == FLAG_##_type)
Sieu Mun Tang54064982022-04-28 22:40:58 +080036
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080037/* Secure Register Access */
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080038#define INTEL_SIP_SMC_REG_READ 0xC2000007
39#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
40#define INTEL_SIP_SMC_REG_UPDATE 0xC2000009
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080041
42/* Remote System Update */
Sieu Mun Tangdcaab772022-05-11 10:16:40 +080043#define INTEL_SIP_SMC_RSU_STATUS 0xC200000B
44#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C
45#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E
46#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
47#define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010
48#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011
49#define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012
50#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013
51#define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014
52#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080053
Kris Chapline768dfa2021-06-25 11:31:52 +010054/* Hardware monitor */
Sieu Mun Tangdcaab772022-05-11 10:16:40 +080055#define INTEL_SIP_SMC_HWMON_READTEMP 0xC2000020
56#define INTEL_SIP_SMC_HWMON_READVOLT 0xC2000021
57#define TEMP_CHANNEL_MAX (1 << 15)
58#define VOLT_CHANNEL_MAX (1 << 15)
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +080059
60/* ECC */
Sieu Mun Tangdcaab772022-05-11 10:16:40 +080061#define INTEL_SIP_SMC_ECC_DBE 0xC200000D
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +080062
Sieu Mun Tanga34b8812022-03-17 03:11:55 +080063/* Generic Command */
Sieu Mun Tangdcaab772022-05-11 10:16:40 +080064#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E
65#define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F
66#define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032
67#define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040
Sieu Mun Tanga34b8812022-03-17 03:11:55 +080068
Sieu Mun Tangdcaab772022-05-11 10:16:40 +080069#define SERVICE_COMPLETED_MODE_ASYNC 0x00004F4E
Sieu Mun Tangfd8a8ad2022-05-07 00:50:37 +080070
Sieu Mun Tang2b8e0052022-04-27 18:57:29 +080071/* Mailbox Command */
Sieu Mun Tangdcaab772022-05-11 10:16:40 +080072#define INTEL_SIP_SMC_GET_USERCODE 0xC200003D
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080073
Sieu Mun Tang128d2a72022-05-11 09:49:25 +080074/* FPGA Crypto Services */
Sieu Mun Tangdcaab772022-05-11 10:16:40 +080075#define INTEL_SIP_SMC_FCS_RANDOM_NUMBER 0xC200005A
76#define INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT 0x4200008F
77#define INTEL_SIP_SMC_FCS_CRYPTION 0x4200005B
78#define INTEL_SIP_SMC_FCS_CRYPTION_EXT 0xC2000090
Sieu Mun Tang59357e82022-05-10 17:53:32 +080079#define INTEL_SIP_SMC_FCS_SERVICE_REQUEST 0x4200005C
Sieu Mun Tangdcaab772022-05-11 10:16:40 +080080#define INTEL_SIP_SMC_FCS_SEND_CERTIFICATE 0x4200005D
Sieu Mun Tang59357e82022-05-10 17:53:32 +080081#define INTEL_SIP_SMC_FCS_GET_PROVISION_DATA 0xC200005E
Sieu Mun Tangdcaab772022-05-11 10:16:40 +080082#define INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH 0xC200005F
83#define INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN 0xC2000064
84#define INTEL_SIP_SMC_FCS_CHIP_ID 0xC2000065
85#define INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY 0xC2000066
86#define INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS 0xC2000067
87#define INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT 0xC2000068
88#define INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD 0xC2000069
89#define INTEL_SIP_SMC_FCS_OPEN_CS_SESSION 0xC200006E
90#define INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION 0xC200006F
91#define INTEL_SIP_SMC_FCS_IMPORT_CS_KEY 0x42000070
92#define INTEL_SIP_SMC_FCS_EXPORT_CS_KEY 0xC2000071
93#define INTEL_SIP_SMC_FCS_REMOVE_CS_KEY 0xC2000072
94#define INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO 0xC2000073
95#define INTEL_SIP_SMC_FCS_AES_CRYPT_INIT 0xC2000074
96#define INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE 0x42000076
97#define INTEL_SIP_SMC_FCS_GET_DIGEST_INIT 0xC2000077
98#define INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE 0xC2000079
99#define INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT 0xC200007A
100#define INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE 0xC200007C
Sieu Mun Tang8aa05ad2022-05-10 17:50:30 +0800101#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT 0xC200007D
102#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE 0xC200007F
Sieu Mun Tangdcaab772022-05-11 10:16:40 +0800103#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT 0xC2000080
104#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE 0xC2000082
Sieu Mun Tang59357e82022-05-10 17:53:32 +0800105#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT 0xC2000083
106#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE 0xC2000085
Sieu Mun Tangdcaab772022-05-11 10:16:40 +0800107#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT 0xC2000086
108#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE 0xC2000088
109#define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT 0xC2000089
110#define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE 0xC200008B
Sieu Mun Tang0675c222022-05-10 17:48:11 +0800111#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT 0xC200008C
112#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE 0xC200008E
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800113
Sieu Mun Tangdcaab772022-05-11 10:16:40 +0800114#define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF
115#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF
116#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U
117#define INTEL_SIP_SMC_FCS_ECC_ALGO_MASK 0xF
118
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800119/* ECC DBE */
Sieu Mun Tangdcaab772022-05-11 10:16:40 +0800120#define WARM_RESET_WFI_FLAG BIT(31)
121#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
Sieu Mun Tange7a037f2022-05-10 17:18:19 +0800122 SYSMGR_ECC_DDR0_MASK |\
123 SYSMGR_ECC_DDR1_MASK)
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800124
Sieu Mun Tangf9cb6572022-04-27 18:24:06 +0800125/* Non-mailbox SMC Call */
Sieu Mun Tangdcaab772022-05-11 10:16:40 +0800126#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200
Sieu Mun Tangf9cb6572022-04-27 18:24:06 +0800127
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800128/* SMC function IDs for SiP Service queries */
Sieu Mun Tangdcaab772022-05-11 10:16:40 +0800129#define SIP_SVC_CALL_COUNT 0x8200ff00
130#define SIP_SVC_UID 0x8200ff01
131#define SIP_SVC_VERSION 0x8200ff03
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800132
133/* SiP Service Calls version numbers */
Sieu Mun Tangdcaab772022-05-11 10:16:40 +0800134#define SIP_SVC_VERSION_MAJOR 1
135#define SIP_SVC_VERSION_MINOR 0
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800136
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800137
138/* Structure Definitions */
139struct fpga_config_info {
140 uint32_t addr;
141 int size;
142 int size_written;
143 uint32_t write_requested;
144 int subblocks_sent;
145 int block_number;
146};
147
148/* Function Definitions */
Sieu Mun Tang128d2a72022-05-11 09:49:25 +0800149bool is_size_4_bytes_aligned(uint32_t size);
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800150bool is_address_in_ddr_range(uint64_t addr, uint64_t size);
151
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800152/* ECC DBE */
153bool cold_reset_for_ecc_dbe(void);
154uint32_t intel_ecc_dbe_notification(uint64_t dbe_value);
155
Sieu Mun Tang82cf5df2022-05-05 17:07:21 +0800156/* Miscellaneous HPS services */
157uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask);
158
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800159#endif /* SOCFPGA_SIP_SVC_H */