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git01.mediatek.com / filogic / atf / f9cb657b9063ee457d4b8d70a99e296b9eebc2ee / . / plat / intel / soc / common / include / socfpga_sip_svc.h
blob: df2a2fba4e060a512caafd3fb8e526f14b5914a8 [file] [log] [blame]
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]1/*
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800[diff] [blame]2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef SOCFPGA_SIP_SVC_H
8#define SOCFPGA_SIP_SVC_H
9
10
11/* SiP status response */
12#define INTEL_SIP_SMC_STATUS_OK 0
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]13#define INTEL_SIP_SMC_STATUS_BUSY 0x1
14#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +0800[diff] [blame]15#define INTEL_SIP_SMC_STATUS_ERROR 0x4
16#define INTEL_SIP_SMC_RSU_ERROR 0x7
17
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800[diff] [blame]18/* SiP mailbox error code */
19#define GENERIC_RESPONSE_ERROR 0x3FF
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]20
21/* SMC SiP service function identifier */
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800[diff] [blame]22
23/* FPGA Reconfig */
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]24#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
25#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
26#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
27#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
28#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800[diff] [blame]29
30/* Secure Register Access */
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]31#define INTEL_SIP_SMC_REG_READ 0xC2000007
32#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
33#define INTEL_SIP_SMC_REG_UPDATE 0xC2000009
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800[diff] [blame]34
35/* Remote System Update */
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]36#define INTEL_SIP_SMC_RSU_STATUS 0xC200000B
37#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]38#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E
39#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800[diff] [blame]40#define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010
41#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800[diff] [blame]42
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800[diff] [blame]43
44/* ECC */
45#define INTEL_SIP_SMC_ECC_DBE 0xC200000D
46
Sieu Mun Tanga34b8812022-03-17 03:11:55 +0800[diff] [blame]47/* Generic Command */
48#define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040
49
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800[diff] [blame]50/* Send Mailbox Command */
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800[diff] [blame]51#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]52
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800[diff] [blame]53
54/* SiP Definitions */
55
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800[diff] [blame]56/* ECC DBE */
57#define WARM_RESET_WFI_FLAG BIT(31)
58#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
59 SYSMGR_ECC_DDR0_MASK |\
60 SYSMGR_ECC_DDR1_MASK)
61
Sieu Mun Tangf9cb6572022-04-27 18:24:06 +0800[diff] [blame^]62/* Non-mailbox SMC Call */
63#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200
64
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]65/* SMC function IDs for SiP Service queries */
66#define SIP_SVC_CALL_COUNT 0x8200ff00
67#define SIP_SVC_UID 0x8200ff01
68#define SIP_SVC_VERSION 0x8200ff03
69
70/* SiP Service Calls version numbers */
Sieu Mun Tangf9cb6572022-04-27 18:24:06 +0800[diff] [blame^]71#define SIP_SVC_VERSION_MAJOR 1
72#define SIP_SVC_VERSION_MINOR 0
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]73
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800[diff] [blame]74
75/* Structure Definitions */
76struct fpga_config_info {
77 uint32_t addr;
78 int size;
79 int size_written;
80 uint32_t write_requested;
81 int subblocks_sent;
82 int block_number;
83};
84
85/* Function Definitions */
86
87bool is_address_in_ddr_range(uint64_t addr, uint64_t size);
88
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800[diff] [blame]89/* ECC DBE */
90bool cold_reset_for_ecc_dbe(void);
91uint32_t intel_ecc_dbe_notification(uint64_t dbe_value);
92
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]93#endif /* SOCFPGA_SIP_SVC_H */