developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * |
| 4 | * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> |
| 5 | * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> |
| 6 | * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> |
| 7 | */ |
| 8 | |
| 9 | #include <linux/of_device.h> |
| 10 | #include <linux/of_mdio.h> |
| 11 | #include <linux/of_net.h> |
| 12 | #include <linux/mfd/syscon.h> |
| 13 | #include <linux/regmap.h> |
| 14 | #include <linux/clk.h> |
| 15 | #include <linux/pm_runtime.h> |
| 16 | #include <linux/if_vlan.h> |
| 17 | #include <linux/reset.h> |
| 18 | #include <linux/tcp.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/pinctrl/devinfo.h> |
| 21 | #include <linux/phylink.h> |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 22 | #include <linux/gpio/consumer.h> |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 23 | #include <net/dsa.h> |
| 24 | |
| 25 | #include "mtk_eth_soc.h" |
| 26 | #include "mtk_eth_dbg.h" |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 27 | #include "mtk_eth_reset.h" |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 28 | |
| 29 | #if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE) |
| 30 | #include "mtk_hnat/nf_hnat_mtk.h" |
| 31 | #endif |
| 32 | |
| 33 | static int mtk_msg_level = -1; |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 34 | atomic_t reset_lock = ATOMIC_INIT(0); |
| 35 | atomic_t force = ATOMIC_INIT(0); |
| 36 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 37 | module_param_named(msg_level, mtk_msg_level, int, 0); |
| 38 | MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 39 | DECLARE_COMPLETION(wait_ser_done); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 40 | |
| 41 | #define MTK_ETHTOOL_STAT(x) { #x, \ |
| 42 | offsetof(struct mtk_hw_stats, x) / sizeof(u64) } |
| 43 | |
| 44 | /* strings used by ethtool */ |
| 45 | static const struct mtk_ethtool_stats { |
| 46 | char str[ETH_GSTRING_LEN]; |
| 47 | u32 offset; |
| 48 | } mtk_ethtool_stats[] = { |
| 49 | MTK_ETHTOOL_STAT(tx_bytes), |
| 50 | MTK_ETHTOOL_STAT(tx_packets), |
| 51 | MTK_ETHTOOL_STAT(tx_skip), |
| 52 | MTK_ETHTOOL_STAT(tx_collisions), |
| 53 | MTK_ETHTOOL_STAT(rx_bytes), |
| 54 | MTK_ETHTOOL_STAT(rx_packets), |
| 55 | MTK_ETHTOOL_STAT(rx_overflow), |
| 56 | MTK_ETHTOOL_STAT(rx_fcs_errors), |
| 57 | MTK_ETHTOOL_STAT(rx_short_errors), |
| 58 | MTK_ETHTOOL_STAT(rx_long_errors), |
| 59 | MTK_ETHTOOL_STAT(rx_checksum_errors), |
| 60 | MTK_ETHTOOL_STAT(rx_flow_control_packets), |
| 61 | }; |
| 62 | |
| 63 | static const char * const mtk_clks_source_name[] = { |
| 64 | "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", |
| 65 | "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", |
| 66 | "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", |
| 67 | "sgmii_ck", "eth2pll", "wocpu0","wocpu1", |
| 68 | }; |
| 69 | |
| 70 | void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) |
| 71 | { |
| 72 | __raw_writel(val, eth->base + reg); |
| 73 | } |
| 74 | |
| 75 | u32 mtk_r32(struct mtk_eth *eth, unsigned reg) |
| 76 | { |
| 77 | return __raw_readl(eth->base + reg); |
| 78 | } |
| 79 | |
| 80 | u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) |
| 81 | { |
| 82 | u32 val; |
| 83 | |
| 84 | val = mtk_r32(eth, reg); |
| 85 | val &= ~mask; |
| 86 | val |= set; |
| 87 | mtk_w32(eth, val, reg); |
| 88 | return reg; |
| 89 | } |
| 90 | |
| 91 | static int mtk_mdio_busy_wait(struct mtk_eth *eth) |
| 92 | { |
| 93 | unsigned long t_start = jiffies; |
| 94 | |
| 95 | while (1) { |
| 96 | if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) |
| 97 | return 0; |
| 98 | if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) |
| 99 | break; |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 100 | cond_resched(); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | dev_err(eth->dev, "mdio: MDIO timeout\n"); |
| 104 | return -1; |
| 105 | } |
| 106 | |
developer | 599cda4 | 2022-05-24 15:13:31 +0800 | [diff] [blame] | 107 | u32 _mtk_mdio_write(struct mtk_eth *eth, int phy_addr, |
| 108 | int phy_reg, u16 write_data) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 109 | { |
| 110 | if (mtk_mdio_busy_wait(eth)) |
| 111 | return -1; |
| 112 | |
| 113 | write_data &= 0xffff; |
| 114 | |
developer | 599cda4 | 2022-05-24 15:13:31 +0800 | [diff] [blame] | 115 | if (phy_reg & MII_ADDR_C45) { |
| 116 | mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_ADDR_C45 | |
| 117 | ((mdiobus_c45_devad(phy_reg) & 0x1f) << PHY_IAC_REG_SHIFT) | |
| 118 | ((phy_addr & 0x1f) << PHY_IAC_ADDR_SHIFT) | mdiobus_c45_regad(phy_reg), |
| 119 | MTK_PHY_IAC); |
| 120 | |
| 121 | if (mtk_mdio_busy_wait(eth)) |
| 122 | return -1; |
| 123 | |
| 124 | mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_WRITE | |
| 125 | ((mdiobus_c45_devad(phy_reg) & 0x1f) << PHY_IAC_REG_SHIFT) | |
| 126 | ((phy_addr & 0x1f) << PHY_IAC_ADDR_SHIFT) | write_data, |
| 127 | MTK_PHY_IAC); |
| 128 | } else { |
| 129 | mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | |
| 130 | ((phy_reg & 0x1f) << PHY_IAC_REG_SHIFT) | |
| 131 | ((phy_addr & 0x1f) << PHY_IAC_ADDR_SHIFT) | write_data, |
| 132 | MTK_PHY_IAC); |
| 133 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 134 | |
| 135 | if (mtk_mdio_busy_wait(eth)) |
| 136 | return -1; |
| 137 | |
| 138 | return 0; |
| 139 | } |
| 140 | |
developer | 599cda4 | 2022-05-24 15:13:31 +0800 | [diff] [blame] | 141 | u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 142 | { |
| 143 | u32 d; |
| 144 | |
| 145 | if (mtk_mdio_busy_wait(eth)) |
| 146 | return 0xffff; |
| 147 | |
developer | 599cda4 | 2022-05-24 15:13:31 +0800 | [diff] [blame] | 148 | if (phy_reg & MII_ADDR_C45) { |
| 149 | mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_ADDR_C45 | |
| 150 | ((mdiobus_c45_devad(phy_reg) & 0x1f) << PHY_IAC_REG_SHIFT) | |
| 151 | ((phy_addr & 0x1f) << PHY_IAC_ADDR_SHIFT) | mdiobus_c45_regad(phy_reg), |
| 152 | MTK_PHY_IAC); |
| 153 | |
| 154 | if (mtk_mdio_busy_wait(eth)) |
| 155 | return 0xffff; |
| 156 | |
| 157 | mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_READ_C45 | |
| 158 | ((mdiobus_c45_devad(phy_reg) & 0x1f) << PHY_IAC_REG_SHIFT) | |
| 159 | ((phy_addr & 0x1f) << PHY_IAC_ADDR_SHIFT), |
| 160 | MTK_PHY_IAC); |
| 161 | } else { |
| 162 | mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | |
| 163 | ((phy_reg & 0x1f) << PHY_IAC_REG_SHIFT) | |
| 164 | ((phy_addr & 0x1f) << PHY_IAC_ADDR_SHIFT), |
| 165 | MTK_PHY_IAC); |
| 166 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 167 | |
| 168 | if (mtk_mdio_busy_wait(eth)) |
| 169 | return 0xffff; |
| 170 | |
| 171 | d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; |
| 172 | |
| 173 | return d; |
| 174 | } |
| 175 | |
| 176 | static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, |
| 177 | int phy_reg, u16 val) |
| 178 | { |
| 179 | struct mtk_eth *eth = bus->priv; |
| 180 | |
| 181 | return _mtk_mdio_write(eth, phy_addr, phy_reg, val); |
| 182 | } |
| 183 | |
| 184 | static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) |
| 185 | { |
| 186 | struct mtk_eth *eth = bus->priv; |
| 187 | |
| 188 | return _mtk_mdio_read(eth, phy_addr, phy_reg); |
| 189 | } |
| 190 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 191 | static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, |
| 192 | phy_interface_t interface) |
| 193 | { |
| 194 | u32 val; |
| 195 | |
| 196 | /* Check DDR memory type. |
| 197 | * Currently TRGMII mode with DDR2 memory is not supported. |
| 198 | */ |
| 199 | regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); |
| 200 | if (interface == PHY_INTERFACE_MODE_TRGMII && |
| 201 | val & SYSCFG_DRAM_TYPE_DDR2) { |
| 202 | dev_err(eth->dev, |
| 203 | "TRGMII mode with DDR2 memory is not supported!\n"); |
| 204 | return -EOPNOTSUPP; |
| 205 | } |
| 206 | |
| 207 | val = (interface == PHY_INTERFACE_MODE_TRGMII) ? |
| 208 | ETHSYS_TRGMII_MT7621_DDR_PLL : 0; |
| 209 | |
| 210 | regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, |
| 211 | ETHSYS_TRGMII_MT7621_MASK, val); |
| 212 | |
| 213 | return 0; |
| 214 | } |
| 215 | |
| 216 | static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, |
| 217 | phy_interface_t interface, int speed) |
| 218 | { |
| 219 | u32 val; |
| 220 | int ret; |
| 221 | |
| 222 | if (interface == PHY_INTERFACE_MODE_TRGMII) { |
| 223 | mtk_w32(eth, TRGMII_MODE, INTF_MODE); |
| 224 | val = 500000000; |
| 225 | ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); |
| 226 | if (ret) |
| 227 | dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); |
| 228 | return; |
| 229 | } |
| 230 | |
| 231 | val = (speed == SPEED_1000) ? |
| 232 | INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; |
| 233 | mtk_w32(eth, val, INTF_MODE); |
| 234 | |
| 235 | regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, |
| 236 | ETHSYS_TRGMII_CLK_SEL362_5, |
| 237 | ETHSYS_TRGMII_CLK_SEL362_5); |
| 238 | |
| 239 | val = (speed == SPEED_1000) ? 250000000 : 500000000; |
| 240 | ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); |
| 241 | if (ret) |
| 242 | dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); |
| 243 | |
| 244 | val = (speed == SPEED_1000) ? |
| 245 | RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; |
| 246 | mtk_w32(eth, val, TRGMII_RCK_CTRL); |
| 247 | |
| 248 | val = (speed == SPEED_1000) ? |
| 249 | TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; |
| 250 | mtk_w32(eth, val, TRGMII_TCK_CTRL); |
| 251 | } |
| 252 | |
| 253 | static void mtk_mac_config(struct phylink_config *config, unsigned int mode, |
| 254 | const struct phylink_link_state *state) |
| 255 | { |
| 256 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
| 257 | phylink_config); |
| 258 | struct mtk_eth *eth = mac->hw; |
| 259 | u32 mcr_cur, mcr_new, sid, i; |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 260 | int val, ge_mode, err=0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 261 | |
| 262 | /* MT76x8 has no hardware settings between for the MAC */ |
| 263 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && |
| 264 | mac->interface != state->interface) { |
| 265 | /* Setup soc pin functions */ |
| 266 | switch (state->interface) { |
| 267 | case PHY_INTERFACE_MODE_TRGMII: |
| 268 | if (mac->id) |
| 269 | goto err_phy; |
| 270 | if (!MTK_HAS_CAPS(mac->hw->soc->caps, |
| 271 | MTK_GMAC1_TRGMII)) |
| 272 | goto err_phy; |
| 273 | /* fall through */ |
| 274 | case PHY_INTERFACE_MODE_RGMII_TXID: |
| 275 | case PHY_INTERFACE_MODE_RGMII_RXID: |
| 276 | case PHY_INTERFACE_MODE_RGMII_ID: |
| 277 | case PHY_INTERFACE_MODE_RGMII: |
| 278 | case PHY_INTERFACE_MODE_MII: |
| 279 | case PHY_INTERFACE_MODE_REVMII: |
| 280 | case PHY_INTERFACE_MODE_RMII: |
| 281 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { |
| 282 | err = mtk_gmac_rgmii_path_setup(eth, mac->id); |
| 283 | if (err) |
| 284 | goto init_err; |
| 285 | } |
| 286 | break; |
| 287 | case PHY_INTERFACE_MODE_1000BASEX: |
| 288 | case PHY_INTERFACE_MODE_2500BASEX: |
| 289 | case PHY_INTERFACE_MODE_SGMII: |
| 290 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { |
| 291 | err = mtk_gmac_sgmii_path_setup(eth, mac->id); |
| 292 | if (err) |
| 293 | goto init_err; |
| 294 | } |
| 295 | break; |
| 296 | case PHY_INTERFACE_MODE_GMII: |
| 297 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { |
| 298 | err = mtk_gmac_gephy_path_setup(eth, mac->id); |
| 299 | if (err) |
| 300 | goto init_err; |
| 301 | } |
| 302 | break; |
| 303 | default: |
| 304 | goto err_phy; |
| 305 | } |
| 306 | |
| 307 | /* Setup clock for 1st gmac */ |
| 308 | if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && |
| 309 | !phy_interface_mode_is_8023z(state->interface) && |
| 310 | MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { |
| 311 | if (MTK_HAS_CAPS(mac->hw->soc->caps, |
| 312 | MTK_TRGMII_MT7621_CLK)) { |
| 313 | if (mt7621_gmac0_rgmii_adjust(mac->hw, |
| 314 | state->interface)) |
| 315 | goto err_phy; |
| 316 | } else { |
| 317 | mtk_gmac0_rgmii_adjust(mac->hw, |
| 318 | state->interface, |
| 319 | state->speed); |
| 320 | |
| 321 | /* mt7623_pad_clk_setup */ |
| 322 | for (i = 0 ; i < NUM_TRGMII_CTRL; i++) |
| 323 | mtk_w32(mac->hw, |
| 324 | TD_DM_DRVP(8) | TD_DM_DRVN(8), |
| 325 | TRGMII_TD_ODT(i)); |
| 326 | |
| 327 | /* Assert/release MT7623 RXC reset */ |
| 328 | mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, |
| 329 | TRGMII_RCK_CTRL); |
| 330 | mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); |
| 331 | } |
| 332 | } |
| 333 | |
| 334 | ge_mode = 0; |
| 335 | switch (state->interface) { |
| 336 | case PHY_INTERFACE_MODE_MII: |
| 337 | case PHY_INTERFACE_MODE_GMII: |
| 338 | ge_mode = 1; |
| 339 | break; |
| 340 | case PHY_INTERFACE_MODE_REVMII: |
| 341 | ge_mode = 2; |
| 342 | break; |
| 343 | case PHY_INTERFACE_MODE_RMII: |
| 344 | if (mac->id) |
| 345 | goto err_phy; |
| 346 | ge_mode = 3; |
| 347 | break; |
| 348 | default: |
| 349 | break; |
| 350 | } |
| 351 | |
| 352 | /* put the gmac into the right mode */ |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 353 | spin_lock(ð->syscfg0_lock); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 354 | regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); |
| 355 | val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); |
| 356 | val |= SYSCFG0_GE_MODE(ge_mode, mac->id); |
| 357 | regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 358 | spin_unlock(ð->syscfg0_lock); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 359 | |
| 360 | mac->interface = state->interface; |
| 361 | } |
| 362 | |
| 363 | /* SGMII */ |
| 364 | if (state->interface == PHY_INTERFACE_MODE_SGMII || |
| 365 | phy_interface_mode_is_8023z(state->interface)) { |
| 366 | /* The path GMAC to SGMII will be enabled once the SGMIISYS is |
| 367 | * being setup done. |
| 368 | */ |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 369 | spin_lock(ð->syscfg0_lock); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 370 | regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); |
| 371 | |
| 372 | regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, |
| 373 | SYSCFG0_SGMII_MASK, |
| 374 | ~(u32)SYSCFG0_SGMII_MASK); |
| 375 | |
| 376 | /* Decide how GMAC and SGMIISYS be mapped */ |
| 377 | sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? |
| 378 | 0 : mac->id; |
| 379 | |
| 380 | /* Setup SGMIISYS with the determined property */ |
| 381 | if (state->interface != PHY_INTERFACE_MODE_SGMII) |
| 382 | err = mtk_sgmii_setup_mode_force(eth->sgmii, sid, |
| 383 | state); |
| 384 | else if (phylink_autoneg_inband(mode)) |
| 385 | err = mtk_sgmii_setup_mode_an(eth->sgmii, sid); |
| 386 | |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 387 | if (err) { |
| 388 | spin_unlock(ð->syscfg0_lock); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 389 | goto init_err; |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 390 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 391 | |
| 392 | regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, |
| 393 | SYSCFG0_SGMII_MASK, val); |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 394 | spin_unlock(ð->syscfg0_lock); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 395 | } else if (phylink_autoneg_inband(mode)) { |
| 396 | dev_err(eth->dev, |
| 397 | "In-band mode not supported in non SGMII mode!\n"); |
| 398 | return; |
| 399 | } |
| 400 | |
| 401 | /* Setup gmac */ |
| 402 | mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); |
| 403 | mcr_new = mcr_cur; |
| 404 | mcr_new &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | |
| 405 | MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | |
| 406 | MAC_MCR_FORCE_RX_FC); |
| 407 | mcr_new |= MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | |
| 408 | MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; |
| 409 | |
| 410 | switch (state->speed) { |
| 411 | case SPEED_2500: |
| 412 | case SPEED_1000: |
| 413 | mcr_new |= MAC_MCR_SPEED_1000; |
| 414 | break; |
| 415 | case SPEED_100: |
| 416 | mcr_new |= MAC_MCR_SPEED_100; |
| 417 | break; |
| 418 | } |
| 419 | if (state->duplex == DUPLEX_FULL) { |
| 420 | mcr_new |= MAC_MCR_FORCE_DPX; |
| 421 | if (state->pause & MLO_PAUSE_TX) |
| 422 | mcr_new |= MAC_MCR_FORCE_TX_FC; |
| 423 | if (state->pause & MLO_PAUSE_RX) |
| 424 | mcr_new |= MAC_MCR_FORCE_RX_FC; |
| 425 | } |
| 426 | |
| 427 | /* Only update control register when needed! */ |
| 428 | if (mcr_new != mcr_cur) |
| 429 | mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); |
| 430 | |
| 431 | return; |
| 432 | |
| 433 | err_phy: |
| 434 | dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, |
| 435 | mac->id, phy_modes(state->interface)); |
| 436 | return; |
| 437 | |
| 438 | init_err: |
| 439 | dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, |
| 440 | mac->id, phy_modes(state->interface), err); |
| 441 | } |
| 442 | |
| 443 | static int mtk_mac_link_state(struct phylink_config *config, |
| 444 | struct phylink_link_state *state) |
| 445 | { |
| 446 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
| 447 | phylink_config); |
| 448 | u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); |
| 449 | |
| 450 | state->link = (pmsr & MAC_MSR_LINK); |
| 451 | state->duplex = (pmsr & MAC_MSR_DPX) >> 1; |
| 452 | |
| 453 | switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { |
| 454 | case 0: |
| 455 | state->speed = SPEED_10; |
| 456 | break; |
| 457 | case MAC_MSR_SPEED_100: |
| 458 | state->speed = SPEED_100; |
| 459 | break; |
| 460 | case MAC_MSR_SPEED_1000: |
| 461 | state->speed = SPEED_1000; |
| 462 | break; |
| 463 | default: |
| 464 | state->speed = SPEED_UNKNOWN; |
| 465 | break; |
| 466 | } |
| 467 | |
| 468 | state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); |
| 469 | if (pmsr & MAC_MSR_RX_FC) |
| 470 | state->pause |= MLO_PAUSE_RX; |
| 471 | if (pmsr & MAC_MSR_TX_FC) |
| 472 | state->pause |= MLO_PAUSE_TX; |
| 473 | |
| 474 | return 1; |
| 475 | } |
| 476 | |
| 477 | static void mtk_mac_an_restart(struct phylink_config *config) |
| 478 | { |
| 479 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
| 480 | phylink_config); |
| 481 | |
| 482 | mtk_sgmii_restart_an(mac->hw, mac->id); |
| 483 | } |
| 484 | |
| 485 | static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, |
| 486 | phy_interface_t interface) |
| 487 | { |
| 488 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
| 489 | phylink_config); |
| 490 | u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); |
| 491 | |
| 492 | mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); |
| 493 | mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); |
| 494 | } |
| 495 | |
| 496 | static void mtk_mac_link_up(struct phylink_config *config, unsigned int mode, |
| 497 | phy_interface_t interface, |
| 498 | struct phy_device *phy) |
| 499 | { |
| 500 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
| 501 | phylink_config); |
| 502 | u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); |
| 503 | |
| 504 | mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; |
| 505 | mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); |
| 506 | } |
| 507 | |
| 508 | static void mtk_validate(struct phylink_config *config, |
| 509 | unsigned long *supported, |
| 510 | struct phylink_link_state *state) |
| 511 | { |
| 512 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
| 513 | phylink_config); |
| 514 | __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; |
| 515 | |
| 516 | if (state->interface != PHY_INTERFACE_MODE_NA && |
| 517 | state->interface != PHY_INTERFACE_MODE_MII && |
| 518 | state->interface != PHY_INTERFACE_MODE_GMII && |
| 519 | !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) && |
| 520 | phy_interface_mode_is_rgmii(state->interface)) && |
| 521 | !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && |
| 522 | !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) && |
| 523 | !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) && |
| 524 | (state->interface == PHY_INTERFACE_MODE_SGMII || |
| 525 | phy_interface_mode_is_8023z(state->interface)))) { |
| 526 | linkmode_zero(supported); |
| 527 | return; |
| 528 | } |
| 529 | |
| 530 | phylink_set_port_modes(mask); |
| 531 | phylink_set(mask, Autoneg); |
| 532 | |
| 533 | switch (state->interface) { |
| 534 | case PHY_INTERFACE_MODE_TRGMII: |
| 535 | phylink_set(mask, 1000baseT_Full); |
| 536 | break; |
| 537 | case PHY_INTERFACE_MODE_1000BASEX: |
| 538 | case PHY_INTERFACE_MODE_2500BASEX: |
| 539 | phylink_set(mask, 1000baseX_Full); |
| 540 | phylink_set(mask, 2500baseX_Full); |
| 541 | break; |
| 542 | case PHY_INTERFACE_MODE_GMII: |
| 543 | case PHY_INTERFACE_MODE_RGMII: |
| 544 | case PHY_INTERFACE_MODE_RGMII_ID: |
| 545 | case PHY_INTERFACE_MODE_RGMII_RXID: |
| 546 | case PHY_INTERFACE_MODE_RGMII_TXID: |
| 547 | phylink_set(mask, 1000baseT_Half); |
| 548 | /* fall through */ |
| 549 | case PHY_INTERFACE_MODE_SGMII: |
| 550 | phylink_set(mask, 1000baseT_Full); |
| 551 | phylink_set(mask, 1000baseX_Full); |
| 552 | /* fall through */ |
| 553 | case PHY_INTERFACE_MODE_MII: |
| 554 | case PHY_INTERFACE_MODE_RMII: |
| 555 | case PHY_INTERFACE_MODE_REVMII: |
| 556 | case PHY_INTERFACE_MODE_NA: |
| 557 | default: |
| 558 | phylink_set(mask, 10baseT_Half); |
| 559 | phylink_set(mask, 10baseT_Full); |
| 560 | phylink_set(mask, 100baseT_Half); |
| 561 | phylink_set(mask, 100baseT_Full); |
| 562 | break; |
| 563 | } |
| 564 | |
| 565 | if (state->interface == PHY_INTERFACE_MODE_NA) { |
| 566 | if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { |
| 567 | phylink_set(mask, 1000baseT_Full); |
| 568 | phylink_set(mask, 1000baseX_Full); |
| 569 | phylink_set(mask, 2500baseX_Full); |
| 570 | } |
| 571 | if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) { |
| 572 | phylink_set(mask, 1000baseT_Full); |
| 573 | phylink_set(mask, 1000baseT_Half); |
| 574 | phylink_set(mask, 1000baseX_Full); |
| 575 | } |
| 576 | if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) { |
| 577 | phylink_set(mask, 1000baseT_Full); |
| 578 | phylink_set(mask, 1000baseT_Half); |
| 579 | } |
| 580 | } |
| 581 | |
| 582 | phylink_set(mask, Pause); |
| 583 | phylink_set(mask, Asym_Pause); |
| 584 | |
| 585 | linkmode_and(supported, supported, mask); |
| 586 | linkmode_and(state->advertising, state->advertising, mask); |
| 587 | |
| 588 | /* We can only operate at 2500BaseX or 1000BaseX. If requested |
| 589 | * to advertise both, only report advertising at 2500BaseX. |
| 590 | */ |
| 591 | phylink_helper_basex_speed(state); |
| 592 | } |
| 593 | |
| 594 | static const struct phylink_mac_ops mtk_phylink_ops = { |
| 595 | .validate = mtk_validate, |
| 596 | .mac_link_state = mtk_mac_link_state, |
| 597 | .mac_an_restart = mtk_mac_an_restart, |
| 598 | .mac_config = mtk_mac_config, |
| 599 | .mac_link_down = mtk_mac_link_down, |
| 600 | .mac_link_up = mtk_mac_link_up, |
| 601 | }; |
| 602 | |
| 603 | static int mtk_mdio_init(struct mtk_eth *eth) |
| 604 | { |
| 605 | struct device_node *mii_np; |
| 606 | int ret; |
| 607 | |
| 608 | mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); |
| 609 | if (!mii_np) { |
| 610 | dev_err(eth->dev, "no %s child node found", "mdio-bus"); |
| 611 | return -ENODEV; |
| 612 | } |
| 613 | |
| 614 | if (!of_device_is_available(mii_np)) { |
| 615 | ret = -ENODEV; |
| 616 | goto err_put_node; |
| 617 | } |
| 618 | |
| 619 | eth->mii_bus = devm_mdiobus_alloc(eth->dev); |
| 620 | if (!eth->mii_bus) { |
| 621 | ret = -ENOMEM; |
| 622 | goto err_put_node; |
| 623 | } |
| 624 | |
| 625 | eth->mii_bus->name = "mdio"; |
| 626 | eth->mii_bus->read = mtk_mdio_read; |
| 627 | eth->mii_bus->write = mtk_mdio_write; |
| 628 | eth->mii_bus->priv = eth; |
| 629 | eth->mii_bus->parent = eth->dev; |
| 630 | |
developer | 6fd4656 | 2021-10-14 15:04:34 +0800 | [diff] [blame] | 631 | if(snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np) < 0) { |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 632 | ret = -ENOMEM; |
| 633 | goto err_put_node; |
| 634 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 635 | ret = of_mdiobus_register(eth->mii_bus, mii_np); |
| 636 | |
| 637 | err_put_node: |
| 638 | of_node_put(mii_np); |
| 639 | return ret; |
| 640 | } |
| 641 | |
| 642 | static void mtk_mdio_cleanup(struct mtk_eth *eth) |
| 643 | { |
| 644 | if (!eth->mii_bus) |
| 645 | return; |
| 646 | |
| 647 | mdiobus_unregister(eth->mii_bus); |
| 648 | } |
| 649 | |
| 650 | static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) |
| 651 | { |
| 652 | unsigned long flags; |
| 653 | u32 val; |
| 654 | |
| 655 | spin_lock_irqsave(ð->tx_irq_lock, flags); |
| 656 | val = mtk_r32(eth, eth->tx_int_mask_reg); |
| 657 | mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg); |
| 658 | spin_unlock_irqrestore(ð->tx_irq_lock, flags); |
| 659 | } |
| 660 | |
| 661 | static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) |
| 662 | { |
| 663 | unsigned long flags; |
| 664 | u32 val; |
| 665 | |
| 666 | spin_lock_irqsave(ð->tx_irq_lock, flags); |
| 667 | val = mtk_r32(eth, eth->tx_int_mask_reg); |
| 668 | mtk_w32(eth, val | mask, eth->tx_int_mask_reg); |
| 669 | spin_unlock_irqrestore(ð->tx_irq_lock, flags); |
| 670 | } |
| 671 | |
| 672 | static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) |
| 673 | { |
| 674 | unsigned long flags; |
| 675 | u32 val; |
| 676 | |
| 677 | spin_lock_irqsave(ð->rx_irq_lock, flags); |
| 678 | val = mtk_r32(eth, MTK_PDMA_INT_MASK); |
| 679 | mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); |
| 680 | spin_unlock_irqrestore(ð->rx_irq_lock, flags); |
| 681 | } |
| 682 | |
| 683 | static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) |
| 684 | { |
| 685 | unsigned long flags; |
| 686 | u32 val; |
| 687 | |
| 688 | spin_lock_irqsave(ð->rx_irq_lock, flags); |
| 689 | val = mtk_r32(eth, MTK_PDMA_INT_MASK); |
| 690 | mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); |
| 691 | spin_unlock_irqrestore(ð->rx_irq_lock, flags); |
| 692 | } |
| 693 | |
| 694 | static int mtk_set_mac_address(struct net_device *dev, void *p) |
| 695 | { |
| 696 | int ret = eth_mac_addr(dev, p); |
| 697 | struct mtk_mac *mac = netdev_priv(dev); |
| 698 | struct mtk_eth *eth = mac->hw; |
| 699 | const char *macaddr = dev->dev_addr; |
| 700 | |
| 701 | if (ret) |
| 702 | return ret; |
| 703 | |
| 704 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
| 705 | return -EBUSY; |
| 706 | |
| 707 | spin_lock_bh(&mac->hw->page_lock); |
| 708 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
| 709 | mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], |
| 710 | MT7628_SDM_MAC_ADRH); |
| 711 | mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | |
| 712 | (macaddr[4] << 8) | macaddr[5], |
| 713 | MT7628_SDM_MAC_ADRL); |
| 714 | } else { |
| 715 | mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], |
| 716 | MTK_GDMA_MAC_ADRH(mac->id)); |
| 717 | mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | |
| 718 | (macaddr[4] << 8) | macaddr[5], |
| 719 | MTK_GDMA_MAC_ADRL(mac->id)); |
| 720 | } |
| 721 | spin_unlock_bh(&mac->hw->page_lock); |
| 722 | |
| 723 | return 0; |
| 724 | } |
| 725 | |
| 726 | void mtk_stats_update_mac(struct mtk_mac *mac) |
| 727 | { |
| 728 | struct mtk_hw_stats *hw_stats = mac->hw_stats; |
| 729 | unsigned int base = MTK_GDM1_TX_GBCNT; |
| 730 | u64 stats; |
| 731 | |
| 732 | base += hw_stats->reg_offset; |
| 733 | |
| 734 | u64_stats_update_begin(&hw_stats->syncp); |
| 735 | |
| 736 | hw_stats->rx_bytes += mtk_r32(mac->hw, base); |
| 737 | stats = mtk_r32(mac->hw, base + 0x04); |
| 738 | if (stats) |
| 739 | hw_stats->rx_bytes += (stats << 32); |
| 740 | hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); |
| 741 | hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); |
| 742 | hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); |
| 743 | hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); |
| 744 | hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); |
| 745 | hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); |
| 746 | hw_stats->rx_flow_control_packets += |
| 747 | mtk_r32(mac->hw, base + 0x24); |
| 748 | hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); |
| 749 | hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); |
| 750 | hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); |
| 751 | stats = mtk_r32(mac->hw, base + 0x34); |
| 752 | if (stats) |
| 753 | hw_stats->tx_bytes += (stats << 32); |
| 754 | hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); |
| 755 | u64_stats_update_end(&hw_stats->syncp); |
| 756 | } |
| 757 | |
| 758 | static void mtk_stats_update(struct mtk_eth *eth) |
| 759 | { |
| 760 | int i; |
| 761 | |
| 762 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 763 | if (!eth->mac[i] || !eth->mac[i]->hw_stats) |
| 764 | continue; |
| 765 | if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { |
| 766 | mtk_stats_update_mac(eth->mac[i]); |
| 767 | spin_unlock(ð->mac[i]->hw_stats->stats_lock); |
| 768 | } |
| 769 | } |
| 770 | } |
| 771 | |
| 772 | static void mtk_get_stats64(struct net_device *dev, |
| 773 | struct rtnl_link_stats64 *storage) |
| 774 | { |
| 775 | struct mtk_mac *mac = netdev_priv(dev); |
| 776 | struct mtk_hw_stats *hw_stats = mac->hw_stats; |
| 777 | unsigned int start; |
| 778 | |
| 779 | if (netif_running(dev) && netif_device_present(dev)) { |
| 780 | if (spin_trylock_bh(&hw_stats->stats_lock)) { |
| 781 | mtk_stats_update_mac(mac); |
| 782 | spin_unlock_bh(&hw_stats->stats_lock); |
| 783 | } |
| 784 | } |
| 785 | |
| 786 | do { |
| 787 | start = u64_stats_fetch_begin_irq(&hw_stats->syncp); |
| 788 | storage->rx_packets = hw_stats->rx_packets; |
| 789 | storage->tx_packets = hw_stats->tx_packets; |
| 790 | storage->rx_bytes = hw_stats->rx_bytes; |
| 791 | storage->tx_bytes = hw_stats->tx_bytes; |
| 792 | storage->collisions = hw_stats->tx_collisions; |
| 793 | storage->rx_length_errors = hw_stats->rx_short_errors + |
| 794 | hw_stats->rx_long_errors; |
| 795 | storage->rx_over_errors = hw_stats->rx_overflow; |
| 796 | storage->rx_crc_errors = hw_stats->rx_fcs_errors; |
| 797 | storage->rx_errors = hw_stats->rx_checksum_errors; |
| 798 | storage->tx_aborted_errors = hw_stats->tx_skip; |
| 799 | } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); |
| 800 | |
| 801 | storage->tx_errors = dev->stats.tx_errors; |
| 802 | storage->rx_dropped = dev->stats.rx_dropped; |
| 803 | storage->tx_dropped = dev->stats.tx_dropped; |
| 804 | } |
| 805 | |
| 806 | static inline int mtk_max_frag_size(int mtu) |
| 807 | { |
| 808 | /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ |
| 809 | if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) |
| 810 | mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; |
| 811 | |
| 812 | return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + |
| 813 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
| 814 | } |
| 815 | |
| 816 | static inline int mtk_max_buf_size(int frag_size) |
| 817 | { |
| 818 | int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - |
| 819 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
| 820 | |
| 821 | WARN_ON(buf_size < MTK_MAX_RX_LENGTH); |
| 822 | |
| 823 | return buf_size; |
| 824 | } |
| 825 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 826 | static inline bool mtk_rx_get_desc(struct mtk_rx_dma *rxd, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 827 | struct mtk_rx_dma *dma_rxd) |
| 828 | { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 829 | rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 830 | if (!(rxd->rxd2 & RX_DMA_DONE)) |
| 831 | return false; |
| 832 | |
| 833 | rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 834 | rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); |
| 835 | rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); |
developer | a2bdbd5 | 2021-05-31 19:10:17 +0800 | [diff] [blame] | 836 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 837 | rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); |
| 838 | rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); |
| 839 | #endif |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 840 | return true; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 841 | } |
| 842 | |
| 843 | /* the qdma core needs scratch memory to be setup */ |
| 844 | static int mtk_init_fq_dma(struct mtk_eth *eth) |
| 845 | { |
| 846 | dma_addr_t phy_ring_tail; |
| 847 | int cnt = MTK_DMA_SIZE; |
| 848 | dma_addr_t dma_addr; |
| 849 | int i; |
| 850 | |
| 851 | if (!eth->soc->has_sram) { |
| 852 | eth->scratch_ring = dma_alloc_coherent(eth->dev, |
| 853 | cnt * sizeof(struct mtk_tx_dma), |
| 854 | ð->phy_scratch_ring, |
| 855 | GFP_ATOMIC); |
| 856 | } else { |
| 857 | eth->scratch_ring = eth->base + MTK_ETH_SRAM_OFFSET; |
| 858 | } |
| 859 | |
| 860 | if (unlikely(!eth->scratch_ring)) |
| 861 | return -ENOMEM; |
| 862 | |
| 863 | eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, |
| 864 | GFP_KERNEL); |
| 865 | if (unlikely(!eth->scratch_head)) |
| 866 | return -ENOMEM; |
| 867 | |
| 868 | dma_addr = dma_map_single(eth->dev, |
| 869 | eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, |
| 870 | DMA_FROM_DEVICE); |
| 871 | if (unlikely(dma_mapping_error(eth->dev, dma_addr))) |
| 872 | return -ENOMEM; |
| 873 | |
| 874 | phy_ring_tail = eth->phy_scratch_ring + |
| 875 | (sizeof(struct mtk_tx_dma) * (cnt - 1)); |
| 876 | |
| 877 | for (i = 0; i < cnt; i++) { |
| 878 | eth->scratch_ring[i].txd1 = |
| 879 | (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); |
| 880 | if (i < cnt - 1) |
| 881 | eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + |
| 882 | ((i + 1) * sizeof(struct mtk_tx_dma))); |
| 883 | eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); |
| 884 | |
| 885 | eth->scratch_ring[i].txd4 = 0; |
| 886 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 887 | if (eth->soc->has_sram && ((sizeof(struct mtk_tx_dma)) > 16)) { |
| 888 | eth->scratch_ring[i].txd5 = 0; |
| 889 | eth->scratch_ring[i].txd6 = 0; |
| 890 | eth->scratch_ring[i].txd7 = 0; |
| 891 | eth->scratch_ring[i].txd8 = 0; |
| 892 | } |
| 893 | #endif |
| 894 | } |
| 895 | |
| 896 | mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); |
| 897 | mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); |
| 898 | mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); |
| 899 | mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); |
| 900 | |
| 901 | return 0; |
| 902 | } |
| 903 | |
| 904 | static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) |
| 905 | { |
| 906 | void *ret = ring->dma; |
| 907 | |
| 908 | return ret + (desc - ring->phys); |
| 909 | } |
| 910 | |
| 911 | static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, |
| 912 | struct mtk_tx_dma *txd) |
| 913 | { |
| 914 | int idx = txd - ring->dma; |
| 915 | |
| 916 | return &ring->buf[idx]; |
| 917 | } |
| 918 | |
| 919 | static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, |
| 920 | struct mtk_tx_dma *dma) |
| 921 | { |
| 922 | return ring->dma_pdma - ring->dma + dma; |
| 923 | } |
| 924 | |
| 925 | static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma) |
| 926 | { |
| 927 | return ((void *)dma - (void *)ring->dma) / sizeof(*dma); |
| 928 | } |
| 929 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 930 | static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, |
| 931 | bool napi) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 932 | { |
| 933 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 934 | if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { |
| 935 | dma_unmap_single(eth->dev, |
| 936 | dma_unmap_addr(tx_buf, dma_addr0), |
| 937 | dma_unmap_len(tx_buf, dma_len0), |
| 938 | DMA_TO_DEVICE); |
| 939 | } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { |
| 940 | dma_unmap_page(eth->dev, |
| 941 | dma_unmap_addr(tx_buf, dma_addr0), |
| 942 | dma_unmap_len(tx_buf, dma_len0), |
| 943 | DMA_TO_DEVICE); |
| 944 | } |
| 945 | } else { |
| 946 | if (dma_unmap_len(tx_buf, dma_len0)) { |
| 947 | dma_unmap_page(eth->dev, |
| 948 | dma_unmap_addr(tx_buf, dma_addr0), |
| 949 | dma_unmap_len(tx_buf, dma_len0), |
| 950 | DMA_TO_DEVICE); |
| 951 | } |
| 952 | |
| 953 | if (dma_unmap_len(tx_buf, dma_len1)) { |
| 954 | dma_unmap_page(eth->dev, |
| 955 | dma_unmap_addr(tx_buf, dma_addr1), |
| 956 | dma_unmap_len(tx_buf, dma_len1), |
| 957 | DMA_TO_DEVICE); |
| 958 | } |
| 959 | } |
| 960 | |
| 961 | tx_buf->flags = 0; |
| 962 | if (tx_buf->skb && |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 963 | (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) { |
| 964 | if (napi) |
| 965 | napi_consume_skb(tx_buf->skb, napi); |
| 966 | else |
| 967 | dev_kfree_skb_any(tx_buf->skb); |
| 968 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 969 | tx_buf->skb = NULL; |
| 970 | } |
| 971 | |
| 972 | static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, |
| 973 | struct mtk_tx_dma *txd, dma_addr_t mapped_addr, |
| 974 | size_t size, int idx) |
| 975 | { |
| 976 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 977 | dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); |
| 978 | dma_unmap_len_set(tx_buf, dma_len0, size); |
| 979 | } else { |
| 980 | if (idx & 1) { |
| 981 | txd->txd3 = mapped_addr; |
| 982 | txd->txd2 |= TX_DMA_PLEN1(size); |
| 983 | dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); |
| 984 | dma_unmap_len_set(tx_buf, dma_len1, size); |
| 985 | } else { |
| 986 | tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; |
| 987 | txd->txd1 = mapped_addr; |
| 988 | txd->txd2 = TX_DMA_PLEN0(size); |
| 989 | dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); |
| 990 | dma_unmap_len_set(tx_buf, dma_len0, size); |
| 991 | } |
| 992 | } |
| 993 | } |
| 994 | |
| 995 | static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, |
| 996 | int tx_num, struct mtk_tx_ring *ring, bool gso) |
| 997 | { |
| 998 | struct mtk_mac *mac = netdev_priv(dev); |
| 999 | struct mtk_eth *eth = mac->hw; |
| 1000 | struct mtk_tx_dma *itxd, *txd; |
| 1001 | struct mtk_tx_dma *itxd_pdma, *txd_pdma; |
| 1002 | struct mtk_tx_buf *itx_buf, *tx_buf; |
| 1003 | dma_addr_t mapped_addr; |
| 1004 | unsigned int nr_frags; |
| 1005 | int i, n_desc = 1; |
developer | 54bf974 | 2021-12-13 15:29:42 +0800 | [diff] [blame] | 1006 | u32 txd4 = 0, txd5 = 0, txd6 = 0; |
| 1007 | u32 fport; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1008 | u32 qid = 0; |
| 1009 | int k = 0; |
| 1010 | |
| 1011 | itxd = ring->next_free; |
| 1012 | itxd_pdma = qdma_to_pdma(ring, itxd); |
| 1013 | if (itxd == ring->last_free) |
| 1014 | return -ENOMEM; |
| 1015 | |
| 1016 | itx_buf = mtk_desc_to_tx_buf(ring, itxd); |
| 1017 | memset(itx_buf, 0, sizeof(*itx_buf)); |
| 1018 | |
| 1019 | mapped_addr = dma_map_single(eth->dev, skb->data, |
| 1020 | skb_headlen(skb), DMA_TO_DEVICE); |
| 1021 | if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) |
| 1022 | return -ENOMEM; |
| 1023 | |
| 1024 | WRITE_ONCE(itxd->txd1, mapped_addr); |
| 1025 | itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; |
| 1026 | itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : |
| 1027 | MTK_TX_FLAGS_FPORT1; |
| 1028 | setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb), |
| 1029 | k++); |
| 1030 | |
| 1031 | nr_frags = skb_shinfo(skb)->nr_frags; |
| 1032 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1033 | qid = skb->mark & (MTK_QDMA_TX_MASK); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1034 | |
developer | dc0d45f | 2021-12-27 13:01:22 +0800 | [diff] [blame] | 1035 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 1036 | if(!qid && mac->id) |
| 1037 | qid = MTK_QDMA_GMAC2_QID; |
| 1038 | #endif |
| 1039 | |
developer | a2bdbd5 | 2021-05-31 19:10:17 +0800 | [diff] [blame] | 1040 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1041 | /* set the forward port */ |
| 1042 | fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; |
| 1043 | txd4 |= fport; |
| 1044 | |
| 1045 | if (gso) |
| 1046 | txd5 |= TX_DMA_TSO_V2; |
| 1047 | |
| 1048 | /* TX Checksum offload */ |
| 1049 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
| 1050 | txd5 |= TX_DMA_CHKSUM_V2; |
| 1051 | |
| 1052 | /* VLAN header offload */ |
| 1053 | if (skb_vlan_tag_present(skb)) |
| 1054 | txd6 |= TX_DMA_INS_VLAN_V2 | skb_vlan_tag_get(skb); |
| 1055 | |
| 1056 | txd4 = txd4 | TX_DMA_SWC_V2; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1057 | } else { |
| 1058 | /* set the forward port */ |
| 1059 | fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; |
| 1060 | txd4 |= fport; |
| 1061 | |
| 1062 | if (gso) |
| 1063 | txd4 |= TX_DMA_TSO; |
| 1064 | |
| 1065 | /* TX Checksum offload */ |
| 1066 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
| 1067 | txd4 |= TX_DMA_CHKSUM; |
| 1068 | |
| 1069 | /* VLAN header offload */ |
| 1070 | if (skb_vlan_tag_present(skb)) |
| 1071 | txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1072 | } |
| 1073 | /* TX SG offload */ |
| 1074 | txd = itxd; |
| 1075 | txd_pdma = qdma_to_pdma(ring, txd); |
| 1076 | |
| 1077 | #if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE) |
| 1078 | if (HNAT_SKB_CB2(skb)->magic == 0x78681415) { |
developer | a2bdbd5 | 2021-05-31 19:10:17 +0800 | [diff] [blame] | 1079 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1080 | txd4 &= ~(0xf << TX_DMA_FPORT_SHIFT_V2); |
| 1081 | txd4 |= 0x4 << TX_DMA_FPORT_SHIFT_V2; |
| 1082 | } else { |
| 1083 | txd4 &= ~(0x7 << TX_DMA_FPORT_SHIFT); |
| 1084 | txd4 |= 0x4 << TX_DMA_FPORT_SHIFT; |
| 1085 | } |
| 1086 | } |
| 1087 | |
| 1088 | trace_printk("[%s] nr_frags=%x HNAT_SKB_CB2(skb)->magic=%x txd4=%x<-----\n", |
| 1089 | __func__, nr_frags, HNAT_SKB_CB2(skb)->magic, txd4); |
| 1090 | #endif |
| 1091 | |
| 1092 | for (i = 0; i < nr_frags; i++) { |
| 1093 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
| 1094 | unsigned int offset = 0; |
| 1095 | int frag_size = skb_frag_size(frag); |
| 1096 | |
| 1097 | while (frag_size) { |
| 1098 | bool last_frag = false; |
| 1099 | unsigned int frag_map_size; |
| 1100 | bool new_desc = true; |
| 1101 | |
| 1102 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) || |
| 1103 | (i & 0x1)) { |
| 1104 | txd = mtk_qdma_phys_to_virt(ring, txd->txd2); |
| 1105 | txd_pdma = qdma_to_pdma(ring, txd); |
| 1106 | if (txd == ring->last_free) |
| 1107 | goto err_dma; |
| 1108 | |
| 1109 | n_desc++; |
| 1110 | } else { |
| 1111 | new_desc = false; |
| 1112 | } |
| 1113 | |
| 1114 | |
| 1115 | frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); |
| 1116 | mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, |
| 1117 | frag_map_size, |
| 1118 | DMA_TO_DEVICE); |
| 1119 | if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) |
| 1120 | goto err_dma; |
| 1121 | |
| 1122 | if (i == nr_frags - 1 && |
| 1123 | (frag_size - frag_map_size) == 0) |
| 1124 | last_frag = true; |
| 1125 | |
| 1126 | WRITE_ONCE(txd->txd1, mapped_addr); |
| 1127 | |
developer | a2bdbd5 | 2021-05-31 19:10:17 +0800 | [diff] [blame] | 1128 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1129 | WRITE_ONCE(txd->txd3, (TX_DMA_PLEN0(frag_map_size) | |
| 1130 | last_frag * TX_DMA_LS0)); |
| 1131 | WRITE_ONCE(txd->txd4, fport | TX_DMA_SWC_V2 | |
| 1132 | QID_BITS_V2(qid)); |
| 1133 | } else { |
| 1134 | WRITE_ONCE(txd->txd3, |
| 1135 | (TX_DMA_SWC | QID_LOW_BITS(qid) | |
| 1136 | TX_DMA_PLEN0(frag_map_size) | |
| 1137 | last_frag * TX_DMA_LS0)); |
| 1138 | WRITE_ONCE(txd->txd4, |
| 1139 | fport | QID_HIGH_BITS(qid)); |
| 1140 | } |
| 1141 | |
| 1142 | tx_buf = mtk_desc_to_tx_buf(ring, txd); |
| 1143 | if (new_desc) |
| 1144 | memset(tx_buf, 0, sizeof(*tx_buf)); |
| 1145 | tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; |
| 1146 | tx_buf->flags |= MTK_TX_FLAGS_PAGE0; |
| 1147 | tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : |
| 1148 | MTK_TX_FLAGS_FPORT1; |
| 1149 | |
| 1150 | setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr, |
| 1151 | frag_map_size, k++); |
| 1152 | |
| 1153 | frag_size -= frag_map_size; |
| 1154 | offset += frag_map_size; |
| 1155 | } |
| 1156 | } |
| 1157 | |
| 1158 | /* store skb to cleanup */ |
| 1159 | itx_buf->skb = skb; |
| 1160 | |
developer | 54bf974 | 2021-12-13 15:29:42 +0800 | [diff] [blame] | 1161 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 1162 | WRITE_ONCE(itxd->txd5, txd5); |
| 1163 | WRITE_ONCE(itxd->txd6, txd6); |
| 1164 | WRITE_ONCE(itxd->txd7, 0); |
| 1165 | WRITE_ONCE(itxd->txd8, 0); |
| 1166 | #endif |
| 1167 | |
| 1168 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1169 | WRITE_ONCE(itxd->txd4, txd4 | QID_BITS_V2(qid)); |
developer | 54bf974 | 2021-12-13 15:29:42 +0800 | [diff] [blame] | 1170 | WRITE_ONCE(itxd->txd3, (TX_DMA_PLEN0(skb_headlen(skb)) | |
| 1171 | (!nr_frags * TX_DMA_LS0))); |
| 1172 | } else { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1173 | WRITE_ONCE(itxd->txd4, txd4 | QID_HIGH_BITS(qid)); |
developer | 54bf974 | 2021-12-13 15:29:42 +0800 | [diff] [blame] | 1174 | WRITE_ONCE(itxd->txd3, |
| 1175 | TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | |
| 1176 | (!nr_frags * TX_DMA_LS0) | QID_LOW_BITS(qid)); |
| 1177 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1178 | |
| 1179 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 1180 | if (k & 0x1) |
| 1181 | txd_pdma->txd2 |= TX_DMA_LS0; |
| 1182 | else |
| 1183 | txd_pdma->txd2 |= TX_DMA_LS1; |
| 1184 | } |
| 1185 | |
| 1186 | netdev_sent_queue(dev, skb->len); |
| 1187 | skb_tx_timestamp(skb); |
| 1188 | |
| 1189 | ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); |
| 1190 | atomic_sub(n_desc, &ring->free_count); |
| 1191 | |
| 1192 | /* make sure that all changes to the dma ring are flushed before we |
| 1193 | * continue |
| 1194 | */ |
| 1195 | wmb(); |
| 1196 | |
| 1197 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 1198 | if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || |
| 1199 | !netdev_xmit_more()) |
| 1200 | mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); |
| 1201 | } else { |
| 1202 | int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd), |
| 1203 | ring->dma_size); |
| 1204 | mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); |
| 1205 | } |
| 1206 | |
| 1207 | return 0; |
| 1208 | |
| 1209 | err_dma: |
| 1210 | do { |
| 1211 | tx_buf = mtk_desc_to_tx_buf(ring, itxd); |
| 1212 | |
| 1213 | /* unmap dma */ |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1214 | mtk_tx_unmap(eth, tx_buf, false); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1215 | |
| 1216 | itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; |
| 1217 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
| 1218 | itxd_pdma->txd2 = TX_DMA_DESP2_DEF; |
| 1219 | |
| 1220 | itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); |
| 1221 | itxd_pdma = qdma_to_pdma(ring, itxd); |
| 1222 | } while (itxd != txd); |
| 1223 | |
| 1224 | return -ENOMEM; |
| 1225 | } |
| 1226 | |
| 1227 | static inline int mtk_cal_txd_req(struct sk_buff *skb) |
| 1228 | { |
| 1229 | int i, nfrags; |
| 1230 | skb_frag_t *frag; |
| 1231 | |
| 1232 | nfrags = 1; |
| 1233 | if (skb_is_gso(skb)) { |
| 1234 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
| 1235 | frag = &skb_shinfo(skb)->frags[i]; |
| 1236 | nfrags += DIV_ROUND_UP(skb_frag_size(frag), |
| 1237 | MTK_TX_DMA_BUF_LEN); |
| 1238 | } |
| 1239 | } else { |
| 1240 | nfrags += skb_shinfo(skb)->nr_frags; |
| 1241 | } |
| 1242 | |
| 1243 | return nfrags; |
| 1244 | } |
| 1245 | |
| 1246 | static int mtk_queue_stopped(struct mtk_eth *eth) |
| 1247 | { |
| 1248 | int i; |
| 1249 | |
| 1250 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 1251 | if (!eth->netdev[i]) |
| 1252 | continue; |
| 1253 | if (netif_queue_stopped(eth->netdev[i])) |
| 1254 | return 1; |
| 1255 | } |
| 1256 | |
| 1257 | return 0; |
| 1258 | } |
| 1259 | |
| 1260 | static void mtk_wake_queue(struct mtk_eth *eth) |
| 1261 | { |
| 1262 | int i; |
| 1263 | |
| 1264 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 1265 | if (!eth->netdev[i]) |
| 1266 | continue; |
| 1267 | netif_wake_queue(eth->netdev[i]); |
| 1268 | } |
| 1269 | } |
| 1270 | |
| 1271 | static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) |
| 1272 | { |
| 1273 | struct mtk_mac *mac = netdev_priv(dev); |
| 1274 | struct mtk_eth *eth = mac->hw; |
| 1275 | struct mtk_tx_ring *ring = ð->tx_ring; |
| 1276 | struct net_device_stats *stats = &dev->stats; |
| 1277 | bool gso = false; |
| 1278 | int tx_num; |
| 1279 | |
| 1280 | /* normally we can rely on the stack not calling this more than once, |
| 1281 | * however we have 2 queues running on the same ring so we need to lock |
| 1282 | * the ring access |
| 1283 | */ |
| 1284 | spin_lock(ð->page_lock); |
| 1285 | |
| 1286 | if (unlikely(test_bit(MTK_RESETTING, ð->state))) |
| 1287 | goto drop; |
| 1288 | |
| 1289 | tx_num = mtk_cal_txd_req(skb); |
| 1290 | if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { |
| 1291 | netif_stop_queue(dev); |
| 1292 | netif_err(eth, tx_queued, dev, |
| 1293 | "Tx Ring full when queue awake!\n"); |
| 1294 | spin_unlock(ð->page_lock); |
| 1295 | return NETDEV_TX_BUSY; |
| 1296 | } |
| 1297 | |
| 1298 | /* TSO: fill MSS info in tcp checksum field */ |
| 1299 | if (skb_is_gso(skb)) { |
| 1300 | if (skb_cow_head(skb, 0)) { |
| 1301 | netif_warn(eth, tx_err, dev, |
| 1302 | "GSO expand head fail.\n"); |
| 1303 | goto drop; |
| 1304 | } |
| 1305 | |
| 1306 | if (skb_shinfo(skb)->gso_type & |
| 1307 | (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { |
| 1308 | gso = true; |
| 1309 | tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); |
| 1310 | } |
| 1311 | } |
| 1312 | |
| 1313 | if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) |
| 1314 | goto drop; |
| 1315 | |
| 1316 | if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) |
| 1317 | netif_stop_queue(dev); |
| 1318 | |
| 1319 | spin_unlock(ð->page_lock); |
| 1320 | |
| 1321 | return NETDEV_TX_OK; |
| 1322 | |
| 1323 | drop: |
| 1324 | spin_unlock(ð->page_lock); |
| 1325 | stats->tx_dropped++; |
| 1326 | dev_kfree_skb_any(skb); |
| 1327 | return NETDEV_TX_OK; |
| 1328 | } |
| 1329 | |
| 1330 | static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) |
| 1331 | { |
| 1332 | int i; |
| 1333 | struct mtk_rx_ring *ring; |
| 1334 | int idx; |
| 1335 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1336 | for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 1337 | if (!IS_NORMAL_RING(i) && !IS_HW_LRO_RING(i)) |
| 1338 | continue; |
| 1339 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1340 | ring = ð->rx_ring[i]; |
| 1341 | idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); |
| 1342 | if (ring->dma[idx].rxd2 & RX_DMA_DONE) { |
| 1343 | ring->calc_idx_update = true; |
| 1344 | return ring; |
| 1345 | } |
| 1346 | } |
| 1347 | |
| 1348 | return NULL; |
| 1349 | } |
| 1350 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1351 | static void mtk_update_rx_cpu_idx(struct mtk_eth *eth, struct mtk_rx_ring *ring) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1352 | { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1353 | int i; |
| 1354 | |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 1355 | if (!eth->hwlro) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1356 | mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 1357 | else { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1358 | for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { |
| 1359 | ring = ð->rx_ring[i]; |
| 1360 | if (ring->calc_idx_update) { |
| 1361 | ring->calc_idx_update = false; |
| 1362 | mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); |
| 1363 | } |
| 1364 | } |
| 1365 | } |
| 1366 | } |
| 1367 | |
| 1368 | static int mtk_poll_rx(struct napi_struct *napi, int budget, |
| 1369 | struct mtk_eth *eth) |
| 1370 | { |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1371 | struct mtk_napi *rx_napi = container_of(napi, struct mtk_napi, napi); |
| 1372 | struct mtk_rx_ring *ring = rx_napi->rx_ring; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1373 | int idx; |
| 1374 | struct sk_buff *skb; |
| 1375 | u8 *data, *new_data; |
| 1376 | struct mtk_rx_dma *rxd, trxd; |
| 1377 | int done = 0; |
| 1378 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1379 | if (unlikely(!ring)) |
| 1380 | goto rx_done; |
| 1381 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1382 | while (done < budget) { |
| 1383 | struct net_device *netdev; |
| 1384 | unsigned int pktlen; |
| 1385 | dma_addr_t dma_addr; |
| 1386 | int mac; |
| 1387 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1388 | if (eth->hwlro) |
| 1389 | ring = mtk_get_rx_ring(eth); |
| 1390 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1391 | if (unlikely(!ring)) |
| 1392 | goto rx_done; |
| 1393 | |
| 1394 | idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); |
| 1395 | rxd = &ring->dma[idx]; |
| 1396 | data = ring->data[idx]; |
| 1397 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1398 | if (!mtk_rx_get_desc(&trxd, rxd)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1399 | break; |
| 1400 | |
| 1401 | /* find out which mac the packet come from. values start at 1 */ |
| 1402 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
| 1403 | mac = 0; |
| 1404 | } else { |
developer | a2bdbd5 | 2021-05-31 19:10:17 +0800 | [diff] [blame] | 1405 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 1406 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1407 | mac = RX_DMA_GET_SPORT(trxd.rxd5) - 1; |
| 1408 | else |
| 1409 | #endif |
| 1410 | mac = (trxd.rxd4 & RX_DMA_SPECIAL_TAG) ? |
| 1411 | 0 : RX_DMA_GET_SPORT(trxd.rxd4) - 1; |
| 1412 | } |
| 1413 | |
| 1414 | if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || |
| 1415 | !eth->netdev[mac])) |
| 1416 | goto release_desc; |
| 1417 | |
| 1418 | netdev = eth->netdev[mac]; |
| 1419 | |
| 1420 | if (unlikely(test_bit(MTK_RESETTING, ð->state))) |
| 1421 | goto release_desc; |
| 1422 | |
| 1423 | /* alloc new buffer */ |
| 1424 | new_data = napi_alloc_frag(ring->frag_size); |
| 1425 | if (unlikely(!new_data)) { |
| 1426 | netdev->stats.rx_dropped++; |
| 1427 | goto release_desc; |
| 1428 | } |
| 1429 | dma_addr = dma_map_single(eth->dev, |
| 1430 | new_data + NET_SKB_PAD + |
| 1431 | eth->ip_align, |
| 1432 | ring->buf_size, |
| 1433 | DMA_FROM_DEVICE); |
| 1434 | if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { |
| 1435 | skb_free_frag(new_data); |
| 1436 | netdev->stats.rx_dropped++; |
| 1437 | goto release_desc; |
| 1438 | } |
| 1439 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1440 | dma_unmap_single(eth->dev, trxd.rxd1, |
| 1441 | ring->buf_size, DMA_FROM_DEVICE); |
| 1442 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1443 | /* receive data */ |
| 1444 | skb = build_skb(data, ring->frag_size); |
| 1445 | if (unlikely(!skb)) { |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1446 | skb_free_frag(data); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1447 | netdev->stats.rx_dropped++; |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1448 | goto skip_rx; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1449 | } |
| 1450 | skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); |
| 1451 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1452 | pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); |
| 1453 | skb->dev = netdev; |
| 1454 | skb_put(skb, pktlen); |
| 1455 | |
developer | a2bdbd5 | 2021-05-31 19:10:17 +0800 | [diff] [blame] | 1456 | if ((!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1457 | (trxd.rxd4 & eth->rx_dma_l4_valid)) || |
developer | a2bdbd5 | 2021-05-31 19:10:17 +0800 | [diff] [blame] | 1458 | (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1459 | (trxd.rxd3 & eth->rx_dma_l4_valid))) |
| 1460 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 1461 | else |
| 1462 | skb_checksum_none_assert(skb); |
| 1463 | skb->protocol = eth_type_trans(skb, netdev); |
| 1464 | |
| 1465 | if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { |
developer | a2bdbd5 | 2021-05-31 19:10:17 +0800 | [diff] [blame] | 1466 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 1467 | if (trxd.rxd3 & RX_DMA_VTAG_V2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1468 | __vlan_hwaccel_put_tag(skb, |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 1469 | htons(RX_DMA_VPID_V2(trxd.rxd4)), |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1470 | RX_DMA_VID_V2(trxd.rxd4)); |
| 1471 | } else { |
| 1472 | if (trxd.rxd2 & RX_DMA_VTAG) |
| 1473 | __vlan_hwaccel_put_tag(skb, |
| 1474 | htons(RX_DMA_VPID(trxd.rxd3)), |
| 1475 | RX_DMA_VID(trxd.rxd3)); |
| 1476 | } |
| 1477 | |
| 1478 | /* If netdev is attached to dsa switch, the special |
| 1479 | * tag inserted in VLAN field by switch hardware can |
| 1480 | * be offload by RX HW VLAN offload. Clears the VLAN |
| 1481 | * information from @skb to avoid unexpected 8021d |
| 1482 | * handler before packet enter dsa framework. |
| 1483 | */ |
| 1484 | if (netdev_uses_dsa(netdev)) |
| 1485 | __vlan_hwaccel_clear_tag(skb); |
| 1486 | } |
| 1487 | |
| 1488 | #if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE) |
developer | a2bdbd5 | 2021-05-31 19:10:17 +0800 | [diff] [blame] | 1489 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 1490 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1491 | *(u32 *)(skb->head) = trxd.rxd5; |
| 1492 | else |
| 1493 | #endif |
| 1494 | *(u32 *)(skb->head) = trxd.rxd4; |
| 1495 | |
| 1496 | skb_hnat_alg(skb) = 0; |
developer | fdfe157 | 2021-09-13 16:56:33 +0800 | [diff] [blame] | 1497 | skb_hnat_filled(skb) = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1498 | skb_hnat_magic_tag(skb) = HNAT_MAGIC_TAG; |
| 1499 | |
| 1500 | if (skb_hnat_reason(skb) == HIT_BIND_FORCE_TO_CPU) { |
| 1501 | trace_printk("[%s] reason=0x%x(force to CPU) from WAN to Ext\n", |
| 1502 | __func__, skb_hnat_reason(skb)); |
| 1503 | skb->pkt_type = PACKET_HOST; |
| 1504 | } |
| 1505 | |
| 1506 | trace_printk("[%s] rxd:(entry=%x,sport=%x,reason=%x,alg=%x\n", |
| 1507 | __func__, skb_hnat_entry(skb), skb_hnat_sport(skb), |
| 1508 | skb_hnat_reason(skb), skb_hnat_alg(skb)); |
| 1509 | #endif |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 1510 | if (mtk_hwlro_stats_ebl && |
| 1511 | IS_HW_LRO_RING(ring->ring_no) && eth->hwlro) { |
| 1512 | hw_lro_stats_update(ring->ring_no, &trxd); |
| 1513 | hw_lro_flush_stats_update(ring->ring_no, &trxd); |
| 1514 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1515 | |
| 1516 | skb_record_rx_queue(skb, 0); |
| 1517 | napi_gro_receive(napi, skb); |
| 1518 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1519 | skip_rx: |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1520 | ring->data[idx] = new_data; |
| 1521 | rxd->rxd1 = (unsigned int)dma_addr; |
| 1522 | |
| 1523 | release_desc: |
| 1524 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) |
| 1525 | rxd->rxd2 = RX_DMA_LSO; |
| 1526 | else |
| 1527 | rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); |
| 1528 | |
| 1529 | ring->calc_idx = idx; |
| 1530 | |
| 1531 | done++; |
| 1532 | } |
| 1533 | |
| 1534 | rx_done: |
| 1535 | if (done) { |
| 1536 | /* make sure that all changes to the dma ring are flushed before |
| 1537 | * we continue |
| 1538 | */ |
| 1539 | wmb(); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1540 | mtk_update_rx_cpu_idx(eth, ring); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1541 | } |
| 1542 | |
| 1543 | return done; |
| 1544 | } |
| 1545 | |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 1546 | static void mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1547 | unsigned int *done, unsigned int *bytes) |
| 1548 | { |
| 1549 | struct mtk_tx_ring *ring = ð->tx_ring; |
| 1550 | struct mtk_tx_dma *desc; |
| 1551 | struct sk_buff *skb; |
| 1552 | struct mtk_tx_buf *tx_buf; |
| 1553 | u32 cpu, dma; |
| 1554 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1555 | cpu = ring->last_free_ptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1556 | dma = mtk_r32(eth, MTK_QTX_DRX_PTR); |
| 1557 | |
| 1558 | desc = mtk_qdma_phys_to_virt(ring, cpu); |
| 1559 | |
| 1560 | while ((cpu != dma) && budget) { |
| 1561 | u32 next_cpu = desc->txd2; |
| 1562 | int mac = 0; |
| 1563 | |
| 1564 | if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) |
| 1565 | break; |
| 1566 | |
| 1567 | desc = mtk_qdma_phys_to_virt(ring, desc->txd2); |
| 1568 | |
| 1569 | tx_buf = mtk_desc_to_tx_buf(ring, desc); |
| 1570 | if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) |
| 1571 | mac = 1; |
| 1572 | |
| 1573 | skb = tx_buf->skb; |
| 1574 | if (!skb) |
| 1575 | break; |
| 1576 | |
| 1577 | if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { |
| 1578 | bytes[mac] += skb->len; |
| 1579 | done[mac]++; |
| 1580 | budget--; |
| 1581 | } |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1582 | mtk_tx_unmap(eth, tx_buf, true); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1583 | |
| 1584 | ring->last_free = desc; |
| 1585 | atomic_inc(&ring->free_count); |
| 1586 | |
| 1587 | cpu = next_cpu; |
| 1588 | } |
| 1589 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1590 | ring->last_free_ptr = cpu; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1591 | mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1592 | } |
| 1593 | |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 1594 | static void mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1595 | unsigned int *done, unsigned int *bytes) |
| 1596 | { |
| 1597 | struct mtk_tx_ring *ring = ð->tx_ring; |
| 1598 | struct mtk_tx_dma *desc; |
| 1599 | struct sk_buff *skb; |
| 1600 | struct mtk_tx_buf *tx_buf; |
| 1601 | u32 cpu, dma; |
| 1602 | |
| 1603 | cpu = ring->cpu_idx; |
| 1604 | dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); |
| 1605 | |
| 1606 | while ((cpu != dma) && budget) { |
| 1607 | tx_buf = &ring->buf[cpu]; |
| 1608 | skb = tx_buf->skb; |
| 1609 | if (!skb) |
| 1610 | break; |
| 1611 | |
| 1612 | if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { |
| 1613 | bytes[0] += skb->len; |
| 1614 | done[0]++; |
| 1615 | budget--; |
| 1616 | } |
| 1617 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1618 | mtk_tx_unmap(eth, tx_buf, true); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1619 | |
| 1620 | desc = &ring->dma[cpu]; |
| 1621 | ring->last_free = desc; |
| 1622 | atomic_inc(&ring->free_count); |
| 1623 | |
| 1624 | cpu = NEXT_DESP_IDX(cpu, ring->dma_size); |
| 1625 | } |
| 1626 | |
| 1627 | ring->cpu_idx = cpu; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1628 | } |
| 1629 | |
| 1630 | static int mtk_poll_tx(struct mtk_eth *eth, int budget) |
| 1631 | { |
| 1632 | struct mtk_tx_ring *ring = ð->tx_ring; |
| 1633 | unsigned int done[MTK_MAX_DEVS]; |
| 1634 | unsigned int bytes[MTK_MAX_DEVS]; |
| 1635 | int total = 0, i; |
| 1636 | |
| 1637 | memset(done, 0, sizeof(done)); |
| 1638 | memset(bytes, 0, sizeof(bytes)); |
| 1639 | |
| 1640 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 1641 | mtk_poll_tx_qdma(eth, budget, done, bytes); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1642 | else |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 1643 | mtk_poll_tx_pdma(eth, budget, done, bytes); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1644 | |
| 1645 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 1646 | if (!eth->netdev[i] || !done[i]) |
| 1647 | continue; |
| 1648 | netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); |
| 1649 | total += done[i]; |
| 1650 | } |
| 1651 | |
| 1652 | if (mtk_queue_stopped(eth) && |
| 1653 | (atomic_read(&ring->free_count) > ring->thresh)) |
| 1654 | mtk_wake_queue(eth); |
| 1655 | |
| 1656 | return total; |
| 1657 | } |
| 1658 | |
| 1659 | static void mtk_handle_status_irq(struct mtk_eth *eth) |
| 1660 | { |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 1661 | u32 status2 = mtk_r32(eth, MTK_FE_INT_STATUS); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1662 | |
| 1663 | if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { |
| 1664 | mtk_stats_update(eth); |
| 1665 | mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 1666 | MTK_FE_INT_STATUS); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1667 | } |
| 1668 | } |
| 1669 | |
| 1670 | static int mtk_napi_tx(struct napi_struct *napi, int budget) |
| 1671 | { |
| 1672 | struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); |
| 1673 | u32 status, mask; |
| 1674 | int tx_done = 0; |
| 1675 | |
| 1676 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
| 1677 | mtk_handle_status_irq(eth); |
| 1678 | mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg); |
| 1679 | tx_done = mtk_poll_tx(eth, budget); |
| 1680 | |
| 1681 | if (unlikely(netif_msg_intr(eth))) { |
| 1682 | status = mtk_r32(eth, eth->tx_int_status_reg); |
| 1683 | mask = mtk_r32(eth, eth->tx_int_mask_reg); |
| 1684 | dev_info(eth->dev, |
| 1685 | "done tx %d, intr 0x%08x/0x%x\n", |
| 1686 | tx_done, status, mask); |
| 1687 | } |
| 1688 | |
| 1689 | if (tx_done == budget) |
| 1690 | return budget; |
| 1691 | |
| 1692 | status = mtk_r32(eth, eth->tx_int_status_reg); |
| 1693 | if (status & MTK_TX_DONE_INT) |
| 1694 | return budget; |
| 1695 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1696 | if (napi_complete(napi)) |
| 1697 | mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1698 | |
| 1699 | return tx_done; |
| 1700 | } |
| 1701 | |
| 1702 | static int mtk_napi_rx(struct napi_struct *napi, int budget) |
| 1703 | { |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1704 | struct mtk_napi *rx_napi = container_of(napi, struct mtk_napi, napi); |
| 1705 | struct mtk_eth *eth = rx_napi->eth; |
| 1706 | struct mtk_rx_ring *ring = rx_napi->rx_ring; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1707 | u32 status, mask; |
| 1708 | int rx_done = 0; |
| 1709 | int remain_budget = budget; |
| 1710 | |
| 1711 | mtk_handle_status_irq(eth); |
| 1712 | |
| 1713 | poll_again: |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1714 | mtk_w32(eth, MTK_RX_DONE_INT(ring->ring_no), MTK_PDMA_INT_STATUS); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1715 | rx_done = mtk_poll_rx(napi, remain_budget, eth); |
| 1716 | |
| 1717 | if (unlikely(netif_msg_intr(eth))) { |
| 1718 | status = mtk_r32(eth, MTK_PDMA_INT_STATUS); |
| 1719 | mask = mtk_r32(eth, MTK_PDMA_INT_MASK); |
| 1720 | dev_info(eth->dev, |
| 1721 | "done rx %d, intr 0x%08x/0x%x\n", |
| 1722 | rx_done, status, mask); |
| 1723 | } |
| 1724 | if (rx_done == remain_budget) |
| 1725 | return budget; |
| 1726 | |
| 1727 | status = mtk_r32(eth, MTK_PDMA_INT_STATUS); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1728 | if (status & MTK_RX_DONE_INT(ring->ring_no)) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1729 | remain_budget -= rx_done; |
| 1730 | goto poll_again; |
| 1731 | } |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1732 | |
| 1733 | if (napi_complete(napi)) |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1734 | mtk_rx_irq_enable(eth, MTK_RX_DONE_INT(ring->ring_no)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1735 | |
| 1736 | return rx_done + budget - remain_budget; |
| 1737 | } |
| 1738 | |
| 1739 | static int mtk_tx_alloc(struct mtk_eth *eth) |
| 1740 | { |
| 1741 | struct mtk_tx_ring *ring = ð->tx_ring; |
| 1742 | int i, sz = sizeof(*ring->dma); |
| 1743 | |
| 1744 | ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), |
| 1745 | GFP_KERNEL); |
| 1746 | if (!ring->buf) |
| 1747 | goto no_tx_mem; |
| 1748 | |
| 1749 | if (!eth->soc->has_sram) |
| 1750 | ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, |
| 1751 | &ring->phys, GFP_ATOMIC); |
| 1752 | else { |
| 1753 | ring->dma = eth->scratch_ring + MTK_DMA_SIZE; |
| 1754 | ring->phys = eth->phy_scratch_ring + MTK_DMA_SIZE * sz; |
| 1755 | } |
| 1756 | |
| 1757 | if (!ring->dma) |
| 1758 | goto no_tx_mem; |
| 1759 | |
| 1760 | for (i = 0; i < MTK_DMA_SIZE; i++) { |
| 1761 | int next = (i + 1) % MTK_DMA_SIZE; |
| 1762 | u32 next_ptr = ring->phys + next * sz; |
| 1763 | |
| 1764 | ring->dma[i].txd2 = next_ptr; |
| 1765 | ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; |
| 1766 | ring->dma[i].txd4 = 0; |
| 1767 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 1768 | if (eth->soc->has_sram && ( sz > 16)) { |
| 1769 | ring->dma[i].txd5 = 0; |
| 1770 | ring->dma[i].txd6 = 0; |
| 1771 | ring->dma[i].txd7 = 0; |
| 1772 | ring->dma[i].txd8 = 0; |
| 1773 | } |
| 1774 | #endif |
| 1775 | } |
| 1776 | |
| 1777 | /* On MT7688 (PDMA only) this driver uses the ring->dma structs |
| 1778 | * only as the framework. The real HW descriptors are the PDMA |
| 1779 | * descriptors in ring->dma_pdma. |
| 1780 | */ |
| 1781 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 1782 | ring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, |
| 1783 | &ring->phys_pdma, |
| 1784 | GFP_ATOMIC); |
| 1785 | if (!ring->dma_pdma) |
| 1786 | goto no_tx_mem; |
| 1787 | |
| 1788 | for (i = 0; i < MTK_DMA_SIZE; i++) { |
| 1789 | ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; |
| 1790 | ring->dma_pdma[i].txd4 = 0; |
| 1791 | } |
| 1792 | } |
| 1793 | |
| 1794 | ring->dma_size = MTK_DMA_SIZE; |
| 1795 | atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); |
| 1796 | ring->next_free = &ring->dma[0]; |
| 1797 | ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1798 | ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1799 | ring->thresh = MAX_SKB_FRAGS; |
| 1800 | |
| 1801 | /* make sure that all changes to the dma ring are flushed before we |
| 1802 | * continue |
| 1803 | */ |
| 1804 | wmb(); |
| 1805 | |
| 1806 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 1807 | mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); |
| 1808 | mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); |
| 1809 | mtk_w32(eth, |
| 1810 | ring->phys + ((MTK_DMA_SIZE - 1) * sz), |
| 1811 | MTK_QTX_CRX_PTR); |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1812 | mtk_w32(eth, ring->last_free_ptr, MTK_QTX_DRX_PTR); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1813 | mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, |
| 1814 | MTK_QTX_CFG(0)); |
| 1815 | } else { |
| 1816 | mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); |
| 1817 | mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0); |
| 1818 | mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); |
| 1819 | mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX); |
| 1820 | } |
| 1821 | |
| 1822 | return 0; |
| 1823 | |
| 1824 | no_tx_mem: |
| 1825 | return -ENOMEM; |
| 1826 | } |
| 1827 | |
| 1828 | static void mtk_tx_clean(struct mtk_eth *eth) |
| 1829 | { |
| 1830 | struct mtk_tx_ring *ring = ð->tx_ring; |
| 1831 | int i; |
| 1832 | |
| 1833 | if (ring->buf) { |
| 1834 | for (i = 0; i < MTK_DMA_SIZE; i++) |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1835 | mtk_tx_unmap(eth, &ring->buf[i], false); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1836 | kfree(ring->buf); |
| 1837 | ring->buf = NULL; |
| 1838 | } |
| 1839 | |
| 1840 | if (!eth->soc->has_sram && ring->dma) { |
| 1841 | dma_free_coherent(eth->dev, |
| 1842 | MTK_DMA_SIZE * sizeof(*ring->dma), |
| 1843 | ring->dma, |
| 1844 | ring->phys); |
| 1845 | ring->dma = NULL; |
| 1846 | } |
| 1847 | |
| 1848 | if (ring->dma_pdma) { |
| 1849 | dma_free_coherent(eth->dev, |
| 1850 | MTK_DMA_SIZE * sizeof(*ring->dma_pdma), |
| 1851 | ring->dma_pdma, |
| 1852 | ring->phys_pdma); |
| 1853 | ring->dma_pdma = NULL; |
| 1854 | } |
| 1855 | } |
| 1856 | |
| 1857 | static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) |
| 1858 | { |
| 1859 | struct mtk_rx_ring *ring; |
| 1860 | int rx_data_len, rx_dma_size; |
| 1861 | int i; |
| 1862 | |
| 1863 | if (rx_flag == MTK_RX_FLAGS_QDMA) { |
| 1864 | if (ring_no) |
| 1865 | return -EINVAL; |
| 1866 | ring = ð->rx_ring_qdma; |
| 1867 | } else { |
| 1868 | ring = ð->rx_ring[ring_no]; |
| 1869 | } |
| 1870 | |
| 1871 | if (rx_flag == MTK_RX_FLAGS_HWLRO) { |
| 1872 | rx_data_len = MTK_MAX_LRO_RX_LENGTH; |
| 1873 | rx_dma_size = MTK_HW_LRO_DMA_SIZE; |
| 1874 | } else { |
| 1875 | rx_data_len = ETH_DATA_LEN; |
| 1876 | rx_dma_size = MTK_DMA_SIZE; |
| 1877 | } |
| 1878 | |
| 1879 | ring->frag_size = mtk_max_frag_size(rx_data_len); |
| 1880 | ring->buf_size = mtk_max_buf_size(ring->frag_size); |
| 1881 | ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), |
| 1882 | GFP_KERNEL); |
| 1883 | if (!ring->data) |
| 1884 | return -ENOMEM; |
| 1885 | |
| 1886 | for (i = 0; i < rx_dma_size; i++) { |
| 1887 | ring->data[i] = netdev_alloc_frag(ring->frag_size); |
| 1888 | if (!ring->data[i]) |
| 1889 | return -ENOMEM; |
| 1890 | } |
| 1891 | |
| 1892 | if ((!eth->soc->has_sram) || (eth->soc->has_sram |
| 1893 | && (rx_flag != MTK_RX_FLAGS_NORMAL))) |
| 1894 | ring->dma = dma_alloc_coherent(eth->dev, |
| 1895 | rx_dma_size * sizeof(*ring->dma), |
| 1896 | &ring->phys, GFP_ATOMIC); |
| 1897 | else { |
| 1898 | struct mtk_tx_ring *tx_ring = ð->tx_ring; |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1899 | ring->dma = (struct mtk_rx_dma *)(tx_ring->dma + |
| 1900 | MTK_DMA_SIZE * (ring_no + 1)); |
| 1901 | ring->phys = tx_ring->phys + MTK_DMA_SIZE * |
| 1902 | sizeof(*tx_ring->dma) * (ring_no + 1); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1903 | } |
| 1904 | |
| 1905 | if (!ring->dma) |
| 1906 | return -ENOMEM; |
| 1907 | |
| 1908 | for (i = 0; i < rx_dma_size; i++) { |
| 1909 | dma_addr_t dma_addr = dma_map_single(eth->dev, |
| 1910 | ring->data[i] + NET_SKB_PAD + eth->ip_align, |
| 1911 | ring->buf_size, |
| 1912 | DMA_FROM_DEVICE); |
| 1913 | if (unlikely(dma_mapping_error(eth->dev, dma_addr))) |
| 1914 | return -ENOMEM; |
| 1915 | ring->dma[i].rxd1 = (unsigned int)dma_addr; |
| 1916 | |
| 1917 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) |
| 1918 | ring->dma[i].rxd2 = RX_DMA_LSO; |
| 1919 | else |
| 1920 | ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); |
| 1921 | |
| 1922 | ring->dma[i].rxd3 = 0; |
| 1923 | ring->dma[i].rxd4 = 0; |
developer | a2bdbd5 | 2021-05-31 19:10:17 +0800 | [diff] [blame] | 1924 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1925 | if (eth->soc->has_sram && ((sizeof(struct mtk_rx_dma)) > 16)) { |
| 1926 | ring->dma[i].rxd5 = 0; |
| 1927 | ring->dma[i].rxd6 = 0; |
| 1928 | ring->dma[i].rxd7 = 0; |
| 1929 | ring->dma[i].rxd8 = 0; |
| 1930 | } |
| 1931 | #endif |
| 1932 | } |
| 1933 | ring->dma_size = rx_dma_size; |
| 1934 | ring->calc_idx_update = false; |
| 1935 | ring->calc_idx = rx_dma_size - 1; |
| 1936 | ring->crx_idx_reg = (rx_flag == MTK_RX_FLAGS_QDMA) ? |
| 1937 | MTK_QRX_CRX_IDX_CFG(ring_no) : |
| 1938 | MTK_PRX_CRX_IDX_CFG(ring_no); |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 1939 | ring->ring_no = ring_no; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1940 | /* make sure that all changes to the dma ring are flushed before we |
| 1941 | * continue |
| 1942 | */ |
| 1943 | wmb(); |
| 1944 | |
| 1945 | if (rx_flag == MTK_RX_FLAGS_QDMA) { |
| 1946 | mtk_w32(eth, ring->phys, MTK_QRX_BASE_PTR_CFG(ring_no)); |
| 1947 | mtk_w32(eth, rx_dma_size, MTK_QRX_MAX_CNT_CFG(ring_no)); |
| 1948 | mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); |
| 1949 | mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_QDMA_RST_IDX); |
| 1950 | } else { |
| 1951 | mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no)); |
| 1952 | mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no)); |
| 1953 | mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); |
| 1954 | mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX); |
| 1955 | } |
| 1956 | |
| 1957 | return 0; |
| 1958 | } |
| 1959 | |
| 1960 | static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, int in_sram) |
| 1961 | { |
| 1962 | int i; |
| 1963 | |
| 1964 | if (ring->data && ring->dma) { |
| 1965 | for (i = 0; i < ring->dma_size; i++) { |
| 1966 | if (!ring->data[i]) |
| 1967 | continue; |
| 1968 | if (!ring->dma[i].rxd1) |
| 1969 | continue; |
| 1970 | dma_unmap_single(eth->dev, |
| 1971 | ring->dma[i].rxd1, |
| 1972 | ring->buf_size, |
| 1973 | DMA_FROM_DEVICE); |
| 1974 | skb_free_frag(ring->data[i]); |
| 1975 | } |
| 1976 | kfree(ring->data); |
| 1977 | ring->data = NULL; |
| 1978 | } |
| 1979 | |
| 1980 | if(in_sram) |
| 1981 | return; |
| 1982 | |
| 1983 | if (ring->dma) { |
| 1984 | dma_free_coherent(eth->dev, |
| 1985 | ring->dma_size * sizeof(*ring->dma), |
| 1986 | ring->dma, |
| 1987 | ring->phys); |
| 1988 | ring->dma = NULL; |
| 1989 | } |
| 1990 | } |
| 1991 | |
| 1992 | static int mtk_hwlro_rx_init(struct mtk_eth *eth) |
| 1993 | { |
| 1994 | int i; |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 1995 | u32 val; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1996 | u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; |
| 1997 | u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; |
| 1998 | |
| 1999 | /* set LRO rings to auto-learn modes */ |
| 2000 | ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; |
| 2001 | |
| 2002 | /* validate LRO ring */ |
| 2003 | ring_ctrl_dw2 |= MTK_RING_VLD; |
| 2004 | |
| 2005 | /* set AGE timer (unit: 20us) */ |
| 2006 | ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; |
| 2007 | ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; |
| 2008 | |
| 2009 | /* set max AGG timer (unit: 20us) */ |
| 2010 | ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; |
| 2011 | |
| 2012 | /* set max LRO AGG count */ |
| 2013 | ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; |
| 2014 | ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; |
| 2015 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2016 | for (i = 1; i <= MTK_HW_LRO_RING_NUM; i++) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2017 | mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); |
| 2018 | mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); |
| 2019 | mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); |
| 2020 | } |
| 2021 | |
| 2022 | /* IPv4 checksum update enable */ |
| 2023 | lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; |
| 2024 | |
| 2025 | /* switch priority comparison to packet count mode */ |
| 2026 | lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; |
| 2027 | |
| 2028 | /* bandwidth threshold setting */ |
| 2029 | mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); |
| 2030 | |
| 2031 | /* auto-learn score delta setting */ |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2032 | mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_LRO_ALT_SCORE_DELTA); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2033 | |
| 2034 | /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ |
| 2035 | mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, |
| 2036 | MTK_PDMA_LRO_ALT_REFRESH_TIMER); |
| 2037 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2038 | /* the minimal remaining room of SDL0 in RXD for lro aggregation */ |
| 2039 | lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; |
| 2040 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2041 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { |
| 2042 | val = mtk_r32(eth, MTK_PDMA_RX_CFG); |
| 2043 | mtk_w32(eth, val | (MTK_PDMA_LRO_SDL << MTK_RX_CFG_SDL_OFFSET), |
| 2044 | MTK_PDMA_RX_CFG); |
| 2045 | |
| 2046 | lro_ctrl_dw0 |= MTK_PDMA_LRO_SDL << MTK_CTRL_DW0_SDL_OFFSET; |
| 2047 | } else { |
| 2048 | /* set HW LRO mode & the max aggregation count for rx packets */ |
| 2049 | lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); |
| 2050 | } |
| 2051 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2052 | /* enable HW LRO */ |
| 2053 | lro_ctrl_dw0 |= MTK_LRO_EN; |
| 2054 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2055 | /* enable cpu reason black list */ |
| 2056 | lro_ctrl_dw0 |= MTK_LRO_CRSN_BNW; |
| 2057 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2058 | mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); |
| 2059 | mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); |
| 2060 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2061 | /* no use PPE cpu reason */ |
| 2062 | mtk_w32(eth, 0xffffffff, MTK_PDMA_LRO_CTRL_DW1); |
| 2063 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2064 | return 0; |
| 2065 | } |
| 2066 | |
| 2067 | static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) |
| 2068 | { |
| 2069 | int i; |
| 2070 | u32 val; |
| 2071 | |
| 2072 | /* relinquish lro rings, flush aggregated packets */ |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2073 | mtk_w32(eth, MTK_LRO_RING_RELINGUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2074 | |
| 2075 | /* wait for relinquishments done */ |
| 2076 | for (i = 0; i < 10; i++) { |
| 2077 | val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2078 | if (val & MTK_LRO_RING_RELINGUISH_DONE) { |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2079 | mdelay(20); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2080 | continue; |
| 2081 | } |
| 2082 | break; |
| 2083 | } |
| 2084 | |
| 2085 | /* invalidate lro rings */ |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2086 | for (i = 1; i <= MTK_HW_LRO_RING_NUM; i++) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2087 | mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); |
| 2088 | |
| 2089 | /* disable HW LRO */ |
| 2090 | mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); |
| 2091 | } |
| 2092 | |
| 2093 | static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) |
| 2094 | { |
| 2095 | u32 reg_val; |
| 2096 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2097 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) |
| 2098 | idx += 1; |
| 2099 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2100 | reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); |
| 2101 | |
| 2102 | /* invalidate the IP setting */ |
| 2103 | mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); |
| 2104 | |
| 2105 | mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); |
| 2106 | |
| 2107 | /* validate the IP setting */ |
| 2108 | mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); |
| 2109 | } |
| 2110 | |
| 2111 | static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) |
| 2112 | { |
| 2113 | u32 reg_val; |
| 2114 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2115 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) |
| 2116 | idx += 1; |
| 2117 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2118 | reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); |
| 2119 | |
| 2120 | /* invalidate the IP setting */ |
| 2121 | mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); |
| 2122 | |
| 2123 | mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); |
| 2124 | } |
| 2125 | |
| 2126 | static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) |
| 2127 | { |
| 2128 | int cnt = 0; |
| 2129 | int i; |
| 2130 | |
| 2131 | for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { |
| 2132 | if (mac->hwlro_ip[i]) |
| 2133 | cnt++; |
| 2134 | } |
| 2135 | |
| 2136 | return cnt; |
| 2137 | } |
| 2138 | |
| 2139 | static int mtk_hwlro_add_ipaddr(struct net_device *dev, |
| 2140 | struct ethtool_rxnfc *cmd) |
| 2141 | { |
| 2142 | struct ethtool_rx_flow_spec *fsp = |
| 2143 | (struct ethtool_rx_flow_spec *)&cmd->fs; |
| 2144 | struct mtk_mac *mac = netdev_priv(dev); |
| 2145 | struct mtk_eth *eth = mac->hw; |
| 2146 | int hwlro_idx; |
| 2147 | |
| 2148 | if ((fsp->flow_type != TCP_V4_FLOW) || |
| 2149 | (!fsp->h_u.tcp_ip4_spec.ip4dst) || |
| 2150 | (fsp->location > 1)) |
| 2151 | return -EINVAL; |
| 2152 | |
| 2153 | mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); |
| 2154 | hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; |
| 2155 | |
| 2156 | mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); |
| 2157 | |
| 2158 | mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); |
| 2159 | |
| 2160 | return 0; |
| 2161 | } |
| 2162 | |
| 2163 | static int mtk_hwlro_del_ipaddr(struct net_device *dev, |
| 2164 | struct ethtool_rxnfc *cmd) |
| 2165 | { |
| 2166 | struct ethtool_rx_flow_spec *fsp = |
| 2167 | (struct ethtool_rx_flow_spec *)&cmd->fs; |
| 2168 | struct mtk_mac *mac = netdev_priv(dev); |
| 2169 | struct mtk_eth *eth = mac->hw; |
| 2170 | int hwlro_idx; |
| 2171 | |
| 2172 | if (fsp->location > 1) |
| 2173 | return -EINVAL; |
| 2174 | |
| 2175 | mac->hwlro_ip[fsp->location] = 0; |
| 2176 | hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; |
| 2177 | |
| 2178 | mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); |
| 2179 | |
| 2180 | mtk_hwlro_inval_ipaddr(eth, hwlro_idx); |
| 2181 | |
| 2182 | return 0; |
| 2183 | } |
| 2184 | |
| 2185 | static void mtk_hwlro_netdev_disable(struct net_device *dev) |
| 2186 | { |
| 2187 | struct mtk_mac *mac = netdev_priv(dev); |
| 2188 | struct mtk_eth *eth = mac->hw; |
| 2189 | int i, hwlro_idx; |
| 2190 | |
| 2191 | for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { |
| 2192 | mac->hwlro_ip[i] = 0; |
| 2193 | hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; |
| 2194 | |
| 2195 | mtk_hwlro_inval_ipaddr(eth, hwlro_idx); |
| 2196 | } |
| 2197 | |
| 2198 | mac->hwlro_ip_cnt = 0; |
| 2199 | } |
| 2200 | |
| 2201 | static int mtk_hwlro_get_fdir_entry(struct net_device *dev, |
| 2202 | struct ethtool_rxnfc *cmd) |
| 2203 | { |
| 2204 | struct mtk_mac *mac = netdev_priv(dev); |
| 2205 | struct ethtool_rx_flow_spec *fsp = |
| 2206 | (struct ethtool_rx_flow_spec *)&cmd->fs; |
| 2207 | |
| 2208 | /* only tcp dst ipv4 is meaningful, others are meaningless */ |
| 2209 | fsp->flow_type = TCP_V4_FLOW; |
| 2210 | fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); |
| 2211 | fsp->m_u.tcp_ip4_spec.ip4dst = 0; |
| 2212 | |
| 2213 | fsp->h_u.tcp_ip4_spec.ip4src = 0; |
| 2214 | fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; |
| 2215 | fsp->h_u.tcp_ip4_spec.psrc = 0; |
| 2216 | fsp->m_u.tcp_ip4_spec.psrc = 0xffff; |
| 2217 | fsp->h_u.tcp_ip4_spec.pdst = 0; |
| 2218 | fsp->m_u.tcp_ip4_spec.pdst = 0xffff; |
| 2219 | fsp->h_u.tcp_ip4_spec.tos = 0; |
| 2220 | fsp->m_u.tcp_ip4_spec.tos = 0xff; |
| 2221 | |
| 2222 | return 0; |
| 2223 | } |
| 2224 | |
| 2225 | static int mtk_hwlro_get_fdir_all(struct net_device *dev, |
| 2226 | struct ethtool_rxnfc *cmd, |
| 2227 | u32 *rule_locs) |
| 2228 | { |
| 2229 | struct mtk_mac *mac = netdev_priv(dev); |
| 2230 | int cnt = 0; |
| 2231 | int i; |
| 2232 | |
| 2233 | for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { |
| 2234 | if (mac->hwlro_ip[i]) { |
| 2235 | rule_locs[cnt] = i; |
| 2236 | cnt++; |
| 2237 | } |
| 2238 | } |
| 2239 | |
| 2240 | cmd->rule_cnt = cnt; |
| 2241 | |
| 2242 | return 0; |
| 2243 | } |
| 2244 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2245 | static int mtk_rss_init(struct mtk_eth *eth) |
| 2246 | { |
| 2247 | u32 val; |
| 2248 | |
| 2249 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { |
| 2250 | /* Set RSS rings to PSE modes */ |
| 2251 | val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(1)); |
| 2252 | val |= MTK_RING_PSE_MODE; |
| 2253 | mtk_w32(eth, val, MTK_LRO_CTRL_DW2_CFG(1)); |
| 2254 | |
| 2255 | /* Enable non-lro multiple rx */ |
| 2256 | val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); |
| 2257 | val |= MTK_NON_LRO_MULTI_EN; |
| 2258 | mtk_w32(eth, val, MTK_PDMA_LRO_CTRL_DW0); |
| 2259 | |
| 2260 | /* Enable RSS dly int supoort */ |
| 2261 | val |= MTK_LRO_DLY_INT_EN; |
| 2262 | mtk_w32(eth, val, MTK_PDMA_LRO_CTRL_DW0); |
| 2263 | |
| 2264 | /* Set RSS delay config int ring1 */ |
| 2265 | mtk_w32(eth, MTK_MAX_DELAY_INT, MTK_LRO_RX1_DLY_INT); |
| 2266 | } |
| 2267 | |
| 2268 | /* Hash Type */ |
| 2269 | val = mtk_r32(eth, MTK_PDMA_RSS_GLO_CFG); |
| 2270 | val |= MTK_RSS_IPV4_STATIC_HASH; |
| 2271 | val |= MTK_RSS_IPV6_STATIC_HASH; |
| 2272 | mtk_w32(eth, val, MTK_PDMA_RSS_GLO_CFG); |
| 2273 | |
| 2274 | /* Select the size of indirection table */ |
| 2275 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW0); |
| 2276 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW1); |
| 2277 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW2); |
| 2278 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW3); |
| 2279 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW4); |
| 2280 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW5); |
| 2281 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW6); |
| 2282 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW7); |
| 2283 | |
| 2284 | /* Pause */ |
| 2285 | val |= MTK_RSS_CFG_REQ; |
| 2286 | mtk_w32(eth, val, MTK_PDMA_RSS_GLO_CFG); |
| 2287 | |
| 2288 | /* Enable RSS*/ |
| 2289 | val |= MTK_RSS_EN; |
| 2290 | mtk_w32(eth, val, MTK_PDMA_RSS_GLO_CFG); |
| 2291 | |
| 2292 | /* Release pause */ |
| 2293 | val &= ~(MTK_RSS_CFG_REQ); |
| 2294 | mtk_w32(eth, val, MTK_PDMA_RSS_GLO_CFG); |
| 2295 | |
| 2296 | /* Set perRSS GRP INT */ |
| 2297 | mtk_w32(eth, MTK_RX_DONE_INT(MTK_RSS_RING1), MTK_PDMA_INT_GRP3); |
| 2298 | |
| 2299 | /* Set GRP INT */ |
| 2300 | mtk_w32(eth, 0x21021030, MTK_FE_INT_GRP); |
| 2301 | |
| 2302 | return 0; |
| 2303 | } |
| 2304 | |
| 2305 | static void mtk_rss_uninit(struct mtk_eth *eth) |
| 2306 | { |
| 2307 | u32 val; |
| 2308 | |
| 2309 | /* Pause */ |
| 2310 | val = mtk_r32(eth, MTK_PDMA_RSS_GLO_CFG); |
| 2311 | val |= MTK_RSS_CFG_REQ; |
| 2312 | mtk_w32(eth, val, MTK_PDMA_RSS_GLO_CFG); |
| 2313 | |
| 2314 | /* Disable RSS*/ |
| 2315 | val &= ~(MTK_RSS_EN); |
| 2316 | mtk_w32(eth, val, MTK_PDMA_RSS_GLO_CFG); |
| 2317 | |
| 2318 | /* Release pause */ |
| 2319 | val &= ~(MTK_RSS_CFG_REQ); |
| 2320 | mtk_w32(eth, val, MTK_PDMA_RSS_GLO_CFG); |
| 2321 | } |
| 2322 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2323 | static netdev_features_t mtk_fix_features(struct net_device *dev, |
| 2324 | netdev_features_t features) |
| 2325 | { |
| 2326 | if (!(features & NETIF_F_LRO)) { |
| 2327 | struct mtk_mac *mac = netdev_priv(dev); |
| 2328 | int ip_cnt = mtk_hwlro_get_ip_cnt(mac); |
| 2329 | |
| 2330 | if (ip_cnt) { |
| 2331 | netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); |
| 2332 | |
| 2333 | features |= NETIF_F_LRO; |
| 2334 | } |
| 2335 | } |
| 2336 | |
| 2337 | if ((features & NETIF_F_HW_VLAN_CTAG_TX) && netdev_uses_dsa(dev)) { |
| 2338 | netdev_info(dev, "TX vlan offload cannot be enabled when dsa is attached.\n"); |
| 2339 | |
| 2340 | features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
| 2341 | } |
| 2342 | |
| 2343 | return features; |
| 2344 | } |
| 2345 | |
| 2346 | static int mtk_set_features(struct net_device *dev, netdev_features_t features) |
| 2347 | { |
| 2348 | struct mtk_mac *mac = netdev_priv(dev); |
| 2349 | struct mtk_eth *eth = mac->hw; |
| 2350 | int err = 0; |
| 2351 | |
| 2352 | if (!((dev->features ^ features) & MTK_SET_FEATURES)) |
| 2353 | return 0; |
| 2354 | |
| 2355 | if (!(features & NETIF_F_LRO)) |
| 2356 | mtk_hwlro_netdev_disable(dev); |
| 2357 | |
| 2358 | if (!(features & NETIF_F_HW_VLAN_CTAG_RX)) |
| 2359 | mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); |
| 2360 | else |
| 2361 | mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); |
| 2362 | |
| 2363 | return err; |
| 2364 | } |
| 2365 | |
| 2366 | /* wait for DMA to finish whatever it is doing before we start using it again */ |
| 2367 | static int mtk_dma_busy_wait(struct mtk_eth *eth) |
| 2368 | { |
| 2369 | unsigned long t_start = jiffies; |
| 2370 | |
| 2371 | while (1) { |
| 2372 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 2373 | if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & |
| 2374 | (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) |
| 2375 | return 0; |
| 2376 | } else { |
| 2377 | if (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) & |
| 2378 | (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) |
| 2379 | return 0; |
| 2380 | } |
| 2381 | |
| 2382 | if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) |
| 2383 | break; |
| 2384 | } |
| 2385 | |
| 2386 | dev_err(eth->dev, "DMA init timeout\n"); |
| 2387 | return -1; |
| 2388 | } |
| 2389 | |
| 2390 | static int mtk_dma_init(struct mtk_eth *eth) |
| 2391 | { |
| 2392 | int err; |
| 2393 | u32 i; |
| 2394 | |
| 2395 | if (mtk_dma_busy_wait(eth)) |
| 2396 | return -EBUSY; |
| 2397 | |
| 2398 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 2399 | /* QDMA needs scratch memory for internal reordering of the |
| 2400 | * descriptors |
| 2401 | */ |
| 2402 | err = mtk_init_fq_dma(eth); |
| 2403 | if (err) |
| 2404 | return err; |
| 2405 | } |
| 2406 | |
| 2407 | err = mtk_tx_alloc(eth); |
| 2408 | if (err) |
| 2409 | return err; |
| 2410 | |
| 2411 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 2412 | err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); |
| 2413 | if (err) |
| 2414 | return err; |
| 2415 | } |
| 2416 | |
| 2417 | err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); |
| 2418 | if (err) |
| 2419 | return err; |
| 2420 | |
| 2421 | if (eth->hwlro) { |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2422 | i = (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ? 4 : 1; |
| 2423 | for (; i < MTK_MAX_RX_RING_NUM; i++) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2424 | err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); |
| 2425 | if (err) |
| 2426 | return err; |
| 2427 | } |
| 2428 | err = mtk_hwlro_rx_init(eth); |
| 2429 | if (err) |
| 2430 | return err; |
| 2431 | } |
| 2432 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2433 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 2434 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) { |
| 2435 | err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_NORMAL); |
| 2436 | if (err) |
| 2437 | return err; |
| 2438 | } |
| 2439 | err = mtk_rss_init(eth); |
| 2440 | if (err) |
| 2441 | return err; |
| 2442 | } |
| 2443 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2444 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 2445 | /* Enable random early drop and set drop threshold |
| 2446 | * automatically |
| 2447 | */ |
| 2448 | mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | |
| 2449 | FC_THRES_MIN, MTK_QDMA_FC_THRES); |
| 2450 | mtk_w32(eth, 0x0, MTK_QDMA_HRED2); |
| 2451 | } |
| 2452 | |
| 2453 | return 0; |
| 2454 | } |
| 2455 | |
| 2456 | static void mtk_dma_free(struct mtk_eth *eth) |
| 2457 | { |
| 2458 | int i; |
| 2459 | |
| 2460 | for (i = 0; i < MTK_MAC_COUNT; i++) |
| 2461 | if (eth->netdev[i]) |
| 2462 | netdev_reset_queue(eth->netdev[i]); |
| 2463 | if ( !eth->soc->has_sram && eth->scratch_ring) { |
| 2464 | dma_free_coherent(eth->dev, |
| 2465 | MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), |
| 2466 | eth->scratch_ring, |
| 2467 | eth->phy_scratch_ring); |
| 2468 | eth->scratch_ring = NULL; |
| 2469 | eth->phy_scratch_ring = 0; |
| 2470 | } |
| 2471 | mtk_tx_clean(eth); |
developer | b3ce86f | 2022-06-30 13:31:47 +0800 | [diff] [blame] | 2472 | mtk_rx_clean(eth, ð->rx_ring[0],eth->soc->has_sram); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2473 | mtk_rx_clean(eth, ð->rx_ring_qdma,0); |
| 2474 | |
| 2475 | if (eth->hwlro) { |
| 2476 | mtk_hwlro_rx_uninit(eth); |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2477 | |
| 2478 | i = (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ? 4 : 1; |
| 2479 | for (; i < MTK_MAX_RX_RING_NUM; i++) |
| 2480 | mtk_rx_clean(eth, ð->rx_ring[i], 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2481 | } |
| 2482 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2483 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 2484 | mtk_rss_uninit(eth); |
| 2485 | |
| 2486 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) |
| 2487 | mtk_rx_clean(eth, ð->rx_ring[i], 1); |
| 2488 | } |
| 2489 | |
developer | 94008d9 | 2021-09-23 09:47:41 +0800 | [diff] [blame] | 2490 | if (eth->scratch_head) { |
| 2491 | kfree(eth->scratch_head); |
| 2492 | eth->scratch_head = NULL; |
| 2493 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2494 | } |
| 2495 | |
| 2496 | static void mtk_tx_timeout(struct net_device *dev) |
| 2497 | { |
| 2498 | struct mtk_mac *mac = netdev_priv(dev); |
| 2499 | struct mtk_eth *eth = mac->hw; |
| 2500 | |
| 2501 | eth->netdev[mac->id]->stats.tx_errors++; |
| 2502 | netif_err(eth, tx_err, dev, |
| 2503 | "transmit timed out\n"); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2504 | |
| 2505 | if (atomic_read(&reset_lock) == 0) |
| 2506 | schedule_work(ð->pending_work); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2507 | } |
| 2508 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2509 | static irqreturn_t mtk_handle_irq_rx(int irq, void *priv) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2510 | { |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2511 | struct mtk_napi *rx_napi = priv; |
| 2512 | struct mtk_eth *eth = rx_napi->eth; |
| 2513 | struct mtk_rx_ring *ring = rx_napi->rx_ring; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2514 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2515 | if (likely(napi_schedule_prep(&rx_napi->napi))) { |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2516 | mtk_rx_irq_disable(eth, MTK_RX_DONE_INT(ring->ring_no)); |
developer | 6bbe70d | 2021-08-06 09:34:55 +0800 | [diff] [blame] | 2517 | __napi_schedule(&rx_napi->napi); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2518 | } |
| 2519 | |
| 2520 | return IRQ_HANDLED; |
| 2521 | } |
| 2522 | |
| 2523 | static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) |
| 2524 | { |
| 2525 | struct mtk_eth *eth = _eth; |
| 2526 | |
| 2527 | if (likely(napi_schedule_prep(ð->tx_napi))) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2528 | mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); |
developer | 6bbe70d | 2021-08-06 09:34:55 +0800 | [diff] [blame] | 2529 | __napi_schedule(ð->tx_napi); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2530 | } |
| 2531 | |
| 2532 | return IRQ_HANDLED; |
| 2533 | } |
| 2534 | |
| 2535 | static irqreturn_t mtk_handle_irq(int irq, void *_eth) |
| 2536 | { |
| 2537 | struct mtk_eth *eth = _eth; |
| 2538 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2539 | if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT(0)) { |
| 2540 | if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT(0)) |
| 2541 | mtk_handle_irq_rx(irq, ð->rx_napi[0]); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2542 | } |
| 2543 | if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) { |
| 2544 | if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT) |
| 2545 | mtk_handle_irq_tx(irq, _eth); |
| 2546 | } |
| 2547 | |
| 2548 | return IRQ_HANDLED; |
| 2549 | } |
| 2550 | |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 2551 | static irqreturn_t mtk_handle_irq_fixed_link(int irq, void *_mac) |
| 2552 | { |
| 2553 | struct mtk_mac *mac = _mac; |
| 2554 | struct mtk_eth *eth = mac->hw; |
| 2555 | struct mtk_phylink_priv *phylink_priv = &mac->phylink_priv; |
| 2556 | struct net_device *dev = phylink_priv->dev; |
| 2557 | int link_old, link_new; |
| 2558 | |
| 2559 | // clear interrupt status for gpy211 |
| 2560 | _mtk_mdio_read(eth, phylink_priv->phyaddr, 0x1A); |
| 2561 | |
| 2562 | link_old = phylink_priv->link; |
| 2563 | link_new = _mtk_mdio_read(eth, phylink_priv->phyaddr, MII_BMSR) & BMSR_LSTATUS; |
| 2564 | |
| 2565 | if (link_old != link_new) { |
| 2566 | phylink_priv->link = link_new; |
| 2567 | if (link_new) { |
| 2568 | printk("phylink.%d %s: Link is Up\n", phylink_priv->id, dev->name); |
| 2569 | if (dev) |
| 2570 | netif_carrier_on(dev); |
| 2571 | } else { |
| 2572 | printk("phylink.%d %s: Link is Down\n", phylink_priv->id, dev->name); |
| 2573 | if (dev) |
| 2574 | netif_carrier_off(dev); |
| 2575 | } |
| 2576 | } |
| 2577 | |
| 2578 | return IRQ_HANDLED; |
| 2579 | } |
| 2580 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2581 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 2582 | static void mtk_poll_controller(struct net_device *dev) |
| 2583 | { |
| 2584 | struct mtk_mac *mac = netdev_priv(dev); |
| 2585 | struct mtk_eth *eth = mac->hw; |
| 2586 | |
| 2587 | mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2588 | mtk_rx_irq_disable(eth, MTK_RX_DONE_INT(0)); |
| 2589 | mtk_handle_irq_rx(eth->irq[2], ð->rx_napi[0]); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2590 | mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2591 | mtk_rx_irq_enable(eth, MTK_RX_DONE_INT(0)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2592 | } |
| 2593 | #endif |
| 2594 | |
| 2595 | static int mtk_start_dma(struct mtk_eth *eth) |
| 2596 | { |
| 2597 | u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2598 | int val, err; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2599 | |
| 2600 | err = mtk_dma_init(eth); |
| 2601 | if (err) { |
| 2602 | mtk_dma_free(eth); |
| 2603 | return err; |
| 2604 | } |
| 2605 | |
| 2606 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
developer | 15d0d28 | 2021-07-14 16:40:44 +0800 | [diff] [blame] | 2607 | val = mtk_r32(eth, MTK_QDMA_GLO_CFG); |
developer | 19d8456 | 2022-04-21 17:01:06 +0800 | [diff] [blame] | 2608 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { |
| 2609 | val &= ~MTK_RESV_BUF_MASK; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2610 | mtk_w32(eth, |
developer | 15d0d28 | 2021-07-14 16:40:44 +0800 | [diff] [blame] | 2611 | val | MTK_TX_DMA_EN | MTK_RX_DMA_EN | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2612 | MTK_DMA_SIZE_32DWORDS | MTK_TX_WB_DDONE | |
| 2613 | MTK_NDP_CO_PRO | MTK_MUTLI_CNT | |
| 2614 | MTK_RESV_BUF | MTK_WCOMP_EN | |
| 2615 | MTK_DMAD_WR_WDONE | MTK_CHK_DDONE_EN | |
developer | 58ab584 | 2022-06-01 15:10:25 +0800 | [diff] [blame] | 2616 | MTK_RX_2B_OFFSET | MTK_PKT_RX_WDONE, MTK_QDMA_GLO_CFG); |
developer | 19d8456 | 2022-04-21 17:01:06 +0800 | [diff] [blame] | 2617 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2618 | else |
| 2619 | mtk_w32(eth, |
developer | 15d0d28 | 2021-07-14 16:40:44 +0800 | [diff] [blame] | 2620 | val | MTK_TX_DMA_EN | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2621 | MTK_DMA_SIZE_32DWORDS | MTK_NDP_CO_PRO | |
| 2622 | MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | |
| 2623 | MTK_RX_BT_32DWORDS, |
| 2624 | MTK_QDMA_GLO_CFG); |
| 2625 | |
developer | 15d0d28 | 2021-07-14 16:40:44 +0800 | [diff] [blame] | 2626 | val = mtk_r32(eth, MTK_PDMA_GLO_CFG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2627 | mtk_w32(eth, |
developer | 15d0d28 | 2021-07-14 16:40:44 +0800 | [diff] [blame] | 2628 | val | MTK_RX_DMA_EN | rx_2b_offset | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2629 | MTK_RX_BT_32DWORDS | MTK_MULTI_EN, |
| 2630 | MTK_PDMA_GLO_CFG); |
| 2631 | } else { |
| 2632 | mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | |
| 2633 | MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, |
| 2634 | MTK_PDMA_GLO_CFG); |
| 2635 | } |
| 2636 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2637 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && eth->hwlro) { |
| 2638 | val = mtk_r32(eth, MTK_PDMA_GLO_CFG); |
| 2639 | mtk_w32(eth, val | MTK_RX_DMA_LRO_EN, MTK_PDMA_GLO_CFG); |
| 2640 | } |
| 2641 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2642 | return 0; |
| 2643 | } |
| 2644 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2645 | void mtk_gdm_config(struct mtk_eth *eth, u32 config) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2646 | { |
| 2647 | int i; |
| 2648 | |
| 2649 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) |
| 2650 | return; |
| 2651 | |
| 2652 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 2653 | u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); |
| 2654 | |
| 2655 | /* default setup the forward port to send frame to PDMA */ |
| 2656 | val &= ~0xffff; |
| 2657 | |
| 2658 | /* Enable RX checksum */ |
| 2659 | val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; |
| 2660 | |
| 2661 | val |= config; |
| 2662 | |
| 2663 | if (eth->netdev[i] && netdev_uses_dsa(eth->netdev[i])) |
| 2664 | val |= MTK_GDMA_SPECIAL_TAG; |
| 2665 | |
| 2666 | mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); |
| 2667 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2668 | } |
| 2669 | |
| 2670 | static int mtk_open(struct net_device *dev) |
| 2671 | { |
| 2672 | struct mtk_mac *mac = netdev_priv(dev); |
| 2673 | struct mtk_eth *eth = mac->hw; |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 2674 | struct mtk_phylink_priv *phylink_priv = &mac->phylink_priv; |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2675 | int err, i; |
developer | 3a5969e | 2022-02-09 15:36:36 +0800 | [diff] [blame] | 2676 | struct device_node *phy_node; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2677 | |
| 2678 | err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); |
| 2679 | if (err) { |
| 2680 | netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, |
| 2681 | err); |
| 2682 | return err; |
| 2683 | } |
| 2684 | |
| 2685 | /* we run 2 netdevs on the same dma ring so we only bring it up once */ |
| 2686 | if (!refcount_read(ð->dma_refcnt)) { |
| 2687 | int err = mtk_start_dma(eth); |
| 2688 | |
| 2689 | if (err) |
| 2690 | return err; |
| 2691 | |
| 2692 | mtk_gdm_config(eth, MTK_GDMA_TO_PDMA); |
| 2693 | |
| 2694 | /* Indicates CDM to parse the MTK special tag from CPU */ |
| 2695 | if (netdev_uses_dsa(dev)) { |
| 2696 | u32 val; |
| 2697 | val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); |
| 2698 | mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); |
| 2699 | val = mtk_r32(eth, MTK_CDMP_IG_CTRL); |
| 2700 | mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); |
| 2701 | } |
| 2702 | |
| 2703 | napi_enable(ð->tx_napi); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2704 | napi_enable(ð->rx_napi[0].napi); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2705 | mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2706 | mtk_rx_irq_enable(eth, MTK_RX_DONE_INT(0)); |
| 2707 | |
| 2708 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 2709 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) { |
| 2710 | napi_enable(ð->rx_napi[i].napi); |
| 2711 | mtk_rx_irq_enable(eth, MTK_RX_DONE_INT(i)); |
| 2712 | } |
| 2713 | } |
| 2714 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2715 | refcount_set(ð->dma_refcnt, 1); |
| 2716 | } |
| 2717 | else |
| 2718 | refcount_inc(ð->dma_refcnt); |
| 2719 | |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 2720 | if (phylink_priv->desc) { |
| 2721 | /*Notice: This programming sequence is only for GPY211 single PHY chip. |
| 2722 | If single PHY chip is not GPY211, the following step you should do: |
| 2723 | 1. Contact your Single PHY chip vendor and get the details of |
| 2724 | - how to enables link status change interrupt |
| 2725 | - how to clears interrupt source |
| 2726 | */ |
| 2727 | |
| 2728 | // clear interrupt source for gpy211 |
| 2729 | _mtk_mdio_read(eth, phylink_priv->phyaddr, 0x1A); |
| 2730 | |
| 2731 | // enable link status change interrupt for gpy211 |
| 2732 | _mtk_mdio_write(eth, phylink_priv->phyaddr, 0x19, 0x0001); |
| 2733 | |
| 2734 | phylink_priv->dev = dev; |
| 2735 | |
| 2736 | // override dev pointer for single PHY chip 0 |
| 2737 | if (phylink_priv->id == 0) { |
| 2738 | struct net_device *tmp; |
| 2739 | |
| 2740 | tmp = __dev_get_by_name(&init_net, phylink_priv->label); |
| 2741 | if (tmp) |
| 2742 | phylink_priv->dev = tmp; |
| 2743 | else |
| 2744 | phylink_priv->dev = NULL; |
| 2745 | } |
| 2746 | } |
| 2747 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2748 | phylink_start(mac->phylink); |
| 2749 | netif_start_queue(dev); |
developer | 3a5969e | 2022-02-09 15:36:36 +0800 | [diff] [blame] | 2750 | phy_node = of_parse_phandle(mac->of_node, "phy-handle", 0); |
developer | 793f7b4 | 2022-05-20 13:54:51 +0800 | [diff] [blame] | 2751 | if (!phy_node && eth->sgmii->regmap[mac->id]) { |
developer | 1a63ef9 | 2022-04-15 17:17:32 +0800 | [diff] [blame] | 2752 | regmap_write(eth->sgmii->regmap[mac->id], SGMSYS_QPHY_PWR_STATE_CTRL, 0); |
developer | 3a5969e | 2022-02-09 15:36:36 +0800 | [diff] [blame] | 2753 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2754 | return 0; |
| 2755 | } |
| 2756 | |
| 2757 | static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) |
| 2758 | { |
| 2759 | u32 val; |
| 2760 | int i; |
| 2761 | |
| 2762 | /* stop the dma engine */ |
| 2763 | spin_lock_bh(ð->page_lock); |
| 2764 | val = mtk_r32(eth, glo_cfg); |
| 2765 | mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), |
| 2766 | glo_cfg); |
| 2767 | spin_unlock_bh(ð->page_lock); |
| 2768 | |
| 2769 | /* wait for dma stop */ |
| 2770 | for (i = 0; i < 10; i++) { |
| 2771 | val = mtk_r32(eth, glo_cfg); |
| 2772 | if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2773 | mdelay(20); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2774 | continue; |
| 2775 | } |
| 2776 | break; |
| 2777 | } |
| 2778 | } |
| 2779 | |
| 2780 | static int mtk_stop(struct net_device *dev) |
| 2781 | { |
| 2782 | struct mtk_mac *mac = netdev_priv(dev); |
| 2783 | struct mtk_eth *eth = mac->hw; |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2784 | int i; |
developer | 3a5969e | 2022-02-09 15:36:36 +0800 | [diff] [blame] | 2785 | u32 val = 0; |
| 2786 | struct device_node *phy_node; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2787 | |
| 2788 | netif_tx_disable(dev); |
| 2789 | |
developer | 3a5969e | 2022-02-09 15:36:36 +0800 | [diff] [blame] | 2790 | phy_node = of_parse_phandle(mac->of_node, "phy-handle", 0); |
| 2791 | if (phy_node) { |
| 2792 | val = _mtk_mdio_read(eth, 0, 0); |
| 2793 | val |= BMCR_PDOWN; |
| 2794 | _mtk_mdio_write(eth, 0, 0, val); |
developer | 793f7b4 | 2022-05-20 13:54:51 +0800 | [diff] [blame] | 2795 | } else if (eth->sgmii->regmap[mac->id]) { |
developer | 1a63ef9 | 2022-04-15 17:17:32 +0800 | [diff] [blame] | 2796 | regmap_read(eth->sgmii->regmap[mac->id], SGMSYS_QPHY_PWR_STATE_CTRL, &val); |
developer | 3a5969e | 2022-02-09 15:36:36 +0800 | [diff] [blame] | 2797 | val |= SGMII_PHYA_PWD; |
developer | 1a63ef9 | 2022-04-15 17:17:32 +0800 | [diff] [blame] | 2798 | regmap_write(eth->sgmii->regmap[mac->id], SGMSYS_QPHY_PWR_STATE_CTRL, val); |
developer | 3a5969e | 2022-02-09 15:36:36 +0800 | [diff] [blame] | 2799 | } |
| 2800 | |
| 2801 | //GMAC RX disable |
| 2802 | val = mtk_r32(eth, MTK_MAC_MCR(mac->id)); |
| 2803 | mtk_w32(eth, val & ~(MAC_MCR_RX_EN), MTK_MAC_MCR(mac->id)); |
| 2804 | |
| 2805 | phylink_stop(mac->phylink); |
| 2806 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2807 | phylink_disconnect_phy(mac->phylink); |
| 2808 | |
| 2809 | /* only shutdown DMA if this is the last user */ |
| 2810 | if (!refcount_dec_and_test(ð->dma_refcnt)) |
| 2811 | return 0; |
| 2812 | |
| 2813 | mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); |
| 2814 | |
| 2815 | mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2816 | mtk_rx_irq_disable(eth, MTK_RX_DONE_INT(0)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2817 | napi_disable(ð->tx_napi); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2818 | napi_disable(ð->rx_napi[0].napi); |
| 2819 | |
| 2820 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 2821 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) { |
| 2822 | mtk_rx_irq_disable(eth, MTK_RX_DONE_INT(i)); |
| 2823 | napi_disable(ð->rx_napi[i].napi); |
| 2824 | } |
| 2825 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2826 | |
| 2827 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
| 2828 | mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); |
| 2829 | mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); |
| 2830 | |
| 2831 | mtk_dma_free(eth); |
| 2832 | |
| 2833 | return 0; |
| 2834 | } |
| 2835 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2836 | void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2837 | { |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2838 | u32 val = 0, i = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2839 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2840 | regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2841 | reset_bits, reset_bits); |
| 2842 | |
| 2843 | while (i++ < 5000) { |
| 2844 | mdelay(1); |
| 2845 | regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); |
| 2846 | |
| 2847 | if ((val & reset_bits) == reset_bits) { |
| 2848 | mtk_reset_event_update(eth, MTK_EVENT_COLD_CNT); |
| 2849 | regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, |
| 2850 | reset_bits, ~reset_bits); |
| 2851 | break; |
| 2852 | } |
| 2853 | } |
| 2854 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2855 | mdelay(10); |
| 2856 | } |
| 2857 | |
| 2858 | static void mtk_clk_disable(struct mtk_eth *eth) |
| 2859 | { |
| 2860 | int clk; |
| 2861 | |
| 2862 | for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) |
| 2863 | clk_disable_unprepare(eth->clks[clk]); |
| 2864 | } |
| 2865 | |
| 2866 | static int mtk_clk_enable(struct mtk_eth *eth) |
| 2867 | { |
| 2868 | int clk, ret; |
| 2869 | |
| 2870 | for (clk = 0; clk < MTK_CLK_MAX ; clk++) { |
| 2871 | ret = clk_prepare_enable(eth->clks[clk]); |
| 2872 | if (ret) |
| 2873 | goto err_disable_clks; |
| 2874 | } |
| 2875 | |
| 2876 | return 0; |
| 2877 | |
| 2878 | err_disable_clks: |
| 2879 | while (--clk >= 0) |
| 2880 | clk_disable_unprepare(eth->clks[clk]); |
| 2881 | |
| 2882 | return ret; |
| 2883 | } |
| 2884 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2885 | static int mtk_napi_init(struct mtk_eth *eth) |
| 2886 | { |
| 2887 | struct mtk_napi *rx_napi = ð->rx_napi[0]; |
| 2888 | int i; |
| 2889 | |
| 2890 | rx_napi->eth = eth; |
| 2891 | rx_napi->rx_ring = ð->rx_ring[0]; |
| 2892 | rx_napi->irq_grp_no = 2; |
| 2893 | |
| 2894 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 2895 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) { |
| 2896 | rx_napi = ð->rx_napi[i]; |
| 2897 | rx_napi->eth = eth; |
| 2898 | rx_napi->rx_ring = ð->rx_ring[i]; |
| 2899 | rx_napi->irq_grp_no = 2 + i; |
| 2900 | } |
| 2901 | } |
| 2902 | |
| 2903 | return 0; |
| 2904 | } |
| 2905 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2906 | static int mtk_hw_init(struct mtk_eth *eth, u32 type) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2907 | { |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2908 | int i, ret = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2909 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2910 | pr_info("[%s] reset_lock:%d, force:%d\n", __func__, |
| 2911 | atomic_read(&reset_lock), atomic_read(&force)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2912 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2913 | if (atomic_read(&reset_lock) == 0) { |
| 2914 | if (test_and_set_bit(MTK_HW_INIT, ð->state)) |
| 2915 | return 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2916 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2917 | pm_runtime_enable(eth->dev); |
| 2918 | pm_runtime_get_sync(eth->dev); |
| 2919 | |
| 2920 | ret = mtk_clk_enable(eth); |
| 2921 | if (ret) |
| 2922 | goto err_disable_pm; |
| 2923 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2924 | |
| 2925 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
| 2926 | ret = device_reset(eth->dev); |
| 2927 | if (ret) { |
| 2928 | dev_err(eth->dev, "MAC reset failed!\n"); |
| 2929 | goto err_disable_pm; |
| 2930 | } |
| 2931 | |
| 2932 | /* enable interrupt delay for RX */ |
| 2933 | mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); |
| 2934 | |
| 2935 | /* disable delay and normal interrupt */ |
| 2936 | mtk_tx_irq_disable(eth, ~0); |
| 2937 | mtk_rx_irq_disable(eth, ~0); |
| 2938 | |
| 2939 | return 0; |
| 2940 | } |
| 2941 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2942 | pr_info("[%s] execute fe %s reset\n", __func__, |
| 2943 | (type == MTK_TYPE_WARM_RESET) ? "warm" : "cold"); |
developer | 545abf0 | 2021-07-15 17:47:01 +0800 | [diff] [blame] | 2944 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2945 | if (type == MTK_TYPE_WARM_RESET) |
| 2946 | mtk_eth_warm_reset(eth); |
developer | 545abf0 | 2021-07-15 17:47:01 +0800 | [diff] [blame] | 2947 | else |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2948 | mtk_eth_cold_reset(eth); |
developer | 545abf0 | 2021-07-15 17:47:01 +0800 | [diff] [blame] | 2949 | |
| 2950 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { |
developer | 545abf0 | 2021-07-15 17:47:01 +0800 | [diff] [blame] | 2951 | /* Set FE to PDMAv2 if necessary */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2952 | mtk_w32(eth, mtk_r32(eth, MTK_FE_GLO_MISC) | MTK_PDMA_V2, MTK_FE_GLO_MISC); |
developer | 545abf0 | 2021-07-15 17:47:01 +0800 | [diff] [blame] | 2953 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2954 | |
| 2955 | if (eth->pctl) { |
| 2956 | /* Set GE2 driving and slew rate */ |
| 2957 | regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); |
| 2958 | |
| 2959 | /* set GE2 TDSEL */ |
| 2960 | regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); |
| 2961 | |
| 2962 | /* set GE2 TUNE */ |
| 2963 | regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); |
| 2964 | } |
| 2965 | |
| 2966 | /* Set linkdown as the default for each GMAC. Its own MCR would be set |
| 2967 | * up with the more appropriate value when mtk_mac_config call is being |
| 2968 | * invoked. |
| 2969 | */ |
| 2970 | for (i = 0; i < MTK_MAC_COUNT; i++) |
| 2971 | mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); |
| 2972 | |
| 2973 | /* Enable RX VLan Offloading */ |
developer | 41294e3 | 2021-05-07 16:11:23 +0800 | [diff] [blame] | 2974 | if (eth->soc->hw_features & NETIF_F_HW_VLAN_CTAG_RX) |
| 2975 | mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); |
| 2976 | else |
| 2977 | mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2978 | |
| 2979 | /* enable interrupt delay for RX/TX */ |
| 2980 | mtk_w32(eth, 0x8f0f8f0f, MTK_PDMA_DELAY_INT); |
| 2981 | mtk_w32(eth, 0x8f0f8f0f, MTK_QDMA_DELAY_INT); |
| 2982 | |
| 2983 | mtk_tx_irq_disable(eth, ~0); |
| 2984 | mtk_rx_irq_disable(eth, ~0); |
| 2985 | |
| 2986 | /* FE int grouping */ |
| 2987 | mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2988 | mtk_w32(eth, MTK_RX_DONE_INT(0), MTK_PDMA_INT_GRP2); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2989 | mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2990 | mtk_w32(eth, MTK_RX_DONE_INT(0), MTK_QDMA_INT_GRP2); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2991 | mtk_w32(eth, 0x21021003, MTK_FE_INT_GRP); |
developer | be97172 | 2022-05-23 13:51:05 +0800 | [diff] [blame] | 2992 | mtk_w32(eth, MTK_FE_INT_TSO_FAIL | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2993 | MTK_FE_INT_TSO_ILLEGAL | MTK_FE_INT_TSO_ALIGN | |
| 2994 | MTK_FE_INT_RFIFO_OV | MTK_FE_INT_RFIFO_UF, MTK_FE_INT_ENABLE); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2995 | |
developer | a2bdbd5 | 2021-05-31 19:10:17 +0800 | [diff] [blame] | 2996 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { |
developer | fef9efd | 2021-06-16 18:28:09 +0800 | [diff] [blame] | 2997 | /* PSE Free Queue Flow Control */ |
| 2998 | mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); |
| 2999 | |
developer | 459b78e | 2022-07-01 17:25:10 +0800 | [diff] [blame] | 3000 | /* PSE should not drop port8 and port9 packets from WDMA Tx */ |
| 3001 | mtk_w32(eth, 0x00000300, PSE_NO_DROP_CFG); |
| 3002 | |
| 3003 | /* PSE should drop p8 and p9 packets when WDMA Rx ring full*/ |
| 3004 | mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); |
developer | 81bcad3 | 2021-07-15 14:14:38 +0800 | [diff] [blame] | 3005 | |
developer | fef9efd | 2021-06-16 18:28:09 +0800 | [diff] [blame] | 3006 | /* PSE config input queue threshold */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3007 | mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); |
| 3008 | mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); |
| 3009 | mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); |
| 3010 | mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); |
| 3011 | mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); |
| 3012 | mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); |
| 3013 | mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); |
developer | fd5f915 | 2022-01-05 16:29:42 +0800 | [diff] [blame] | 3014 | mtk_w32(eth, 0x002a000e, PSE_IQ_REV(8)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3015 | |
developer | fef9efd | 2021-06-16 18:28:09 +0800 | [diff] [blame] | 3016 | /* PSE config output queue threshold */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3017 | mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); |
| 3018 | mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); |
| 3019 | mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); |
| 3020 | mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); |
| 3021 | mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); |
| 3022 | mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); |
| 3023 | mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); |
| 3024 | mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); |
developer | fef9efd | 2021-06-16 18:28:09 +0800 | [diff] [blame] | 3025 | |
| 3026 | /* GDM and CDM Threshold */ |
| 3027 | mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); |
| 3028 | mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); |
| 3029 | mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); |
| 3030 | mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); |
| 3031 | mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); |
| 3032 | mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3033 | } |
| 3034 | |
| 3035 | return 0; |
| 3036 | |
| 3037 | err_disable_pm: |
| 3038 | pm_runtime_put_sync(eth->dev); |
| 3039 | pm_runtime_disable(eth->dev); |
| 3040 | |
| 3041 | return ret; |
| 3042 | } |
| 3043 | |
| 3044 | static int mtk_hw_deinit(struct mtk_eth *eth) |
| 3045 | { |
| 3046 | if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) |
| 3047 | return 0; |
| 3048 | |
| 3049 | mtk_clk_disable(eth); |
| 3050 | |
| 3051 | pm_runtime_put_sync(eth->dev); |
| 3052 | pm_runtime_disable(eth->dev); |
| 3053 | |
| 3054 | return 0; |
| 3055 | } |
| 3056 | |
| 3057 | static int __init mtk_init(struct net_device *dev) |
| 3058 | { |
| 3059 | struct mtk_mac *mac = netdev_priv(dev); |
| 3060 | struct mtk_eth *eth = mac->hw; |
| 3061 | const char *mac_addr; |
| 3062 | |
| 3063 | mac_addr = of_get_mac_address(mac->of_node); |
| 3064 | if (!IS_ERR(mac_addr)) |
| 3065 | ether_addr_copy(dev->dev_addr, mac_addr); |
| 3066 | |
| 3067 | /* If the mac address is invalid, use random mac address */ |
| 3068 | if (!is_valid_ether_addr(dev->dev_addr)) { |
| 3069 | eth_hw_addr_random(dev); |
| 3070 | dev_err(eth->dev, "generated random MAC address %pM\n", |
| 3071 | dev->dev_addr); |
| 3072 | } |
| 3073 | |
| 3074 | return 0; |
| 3075 | } |
| 3076 | |
| 3077 | static void mtk_uninit(struct net_device *dev) |
| 3078 | { |
| 3079 | struct mtk_mac *mac = netdev_priv(dev); |
| 3080 | struct mtk_eth *eth = mac->hw; |
| 3081 | |
| 3082 | phylink_disconnect_phy(mac->phylink); |
| 3083 | mtk_tx_irq_disable(eth, ~0); |
| 3084 | mtk_rx_irq_disable(eth, ~0); |
| 3085 | } |
| 3086 | |
| 3087 | static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
| 3088 | { |
| 3089 | struct mtk_mac *mac = netdev_priv(dev); |
| 3090 | |
| 3091 | switch (cmd) { |
| 3092 | case SIOCGMIIPHY: |
| 3093 | case SIOCGMIIREG: |
| 3094 | case SIOCSMIIREG: |
| 3095 | return phylink_mii_ioctl(mac->phylink, ifr, cmd); |
| 3096 | default: |
| 3097 | /* default invoke the mtk_eth_dbg handler */ |
| 3098 | return mtk_do_priv_ioctl(dev, ifr, cmd); |
| 3099 | break; |
| 3100 | } |
| 3101 | |
| 3102 | return -EOPNOTSUPP; |
| 3103 | } |
| 3104 | |
| 3105 | static void mtk_pending_work(struct work_struct *work) |
| 3106 | { |
| 3107 | struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3108 | struct device_node *phy_node = NULL; |
| 3109 | struct mtk_mac *mac = NULL; |
| 3110 | int err, i = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3111 | unsigned long restart = 0; |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3112 | u32 val = 0; |
| 3113 | |
| 3114 | atomic_inc(&reset_lock); |
| 3115 | val = mtk_r32(eth, MTK_FE_INT_STATUS); |
| 3116 | if (!mtk_check_reset_event(eth, val)) { |
| 3117 | atomic_dec(&reset_lock); |
| 3118 | pr_info("[%s] No need to do FE reset !\n", __func__); |
| 3119 | return; |
| 3120 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3121 | |
| 3122 | rtnl_lock(); |
| 3123 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3124 | /* Disabe FE P3 and P4 */ |
| 3125 | val = mtk_r32(eth, MTK_FE_GLO_CFG); |
| 3126 | val |= MTK_FE_LINK_DOWN_P3; |
| 3127 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) |
| 3128 | val |= MTK_FE_LINK_DOWN_P4; |
| 3129 | mtk_w32(eth, val, MTK_FE_GLO_CFG); |
| 3130 | |
| 3131 | /* Adjust PPE configurations to prepare for reset */ |
| 3132 | mtk_prepare_reset_ppe(eth, 0); |
| 3133 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) |
| 3134 | mtk_prepare_reset_ppe(eth, 1); |
| 3135 | |
| 3136 | /* Adjust FE configurations to prepare for reset */ |
| 3137 | mtk_prepare_reset_fe(eth); |
| 3138 | |
| 3139 | /* Trigger Wifi SER reset */ |
| 3140 | call_netdevice_notifiers(MTK_FE_START_RESET, eth->netdev[0]); |
| 3141 | rtnl_unlock(); |
| 3142 | wait_for_completion_timeout(&wait_ser_done, 5000); |
| 3143 | rtnl_lock(); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3144 | |
| 3145 | while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) |
| 3146 | cpu_relax(); |
| 3147 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3148 | del_timer_sync(ð->mtk_dma_monitor_timer); |
| 3149 | pr_info("[%s] mtk_stop starts !\n", __func__); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3150 | /* stop all devices to make sure that dma is properly shut down */ |
| 3151 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 3152 | if (!eth->netdev[i]) |
| 3153 | continue; |
| 3154 | mtk_stop(eth->netdev[i]); |
| 3155 | __set_bit(i, &restart); |
| 3156 | } |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3157 | pr_info("[%s] mtk_stop ends !\n", __func__); |
| 3158 | mdelay(15); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3159 | |
| 3160 | if (eth->dev->pins) |
| 3161 | pinctrl_select_state(eth->dev->pins->p, |
| 3162 | eth->dev->pins->default_state); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3163 | |
| 3164 | pr_info("[%s] mtk_hw_init starts !\n", __func__); |
| 3165 | mtk_hw_init(eth, MTK_TYPE_WARM_RESET); |
| 3166 | pr_info("[%s] mtk_hw_init ends !\n", __func__); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3167 | |
| 3168 | /* restart DMA and enable IRQs */ |
| 3169 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 3170 | if (!test_bit(i, &restart)) |
| 3171 | continue; |
| 3172 | err = mtk_open(eth->netdev[i]); |
| 3173 | if (err) { |
| 3174 | netif_alert(eth, ifup, eth->netdev[i], |
| 3175 | "Driver up/down cycle failed, closing device.\n"); |
| 3176 | dev_close(eth->netdev[i]); |
| 3177 | } |
| 3178 | } |
| 3179 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3180 | /* Set KA tick select */ |
| 3181 | mtk_m32(eth, MTK_PPE_TICK_SEL_MASK, 0, MTK_PPE_TB_CFG(0)); |
| 3182 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) |
| 3183 | mtk_m32(eth, MTK_PPE_TICK_SEL_MASK, 0, MTK_PPE_TB_CFG(1)); |
| 3184 | |
| 3185 | /* Enabe FE P3 and P4*/ |
| 3186 | val = mtk_r32(eth, MTK_FE_GLO_CFG); |
| 3187 | val &= ~MTK_FE_LINK_DOWN_P3; |
| 3188 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) |
| 3189 | val &= ~MTK_FE_LINK_DOWN_P4; |
| 3190 | mtk_w32(eth, val, MTK_FE_GLO_CFG); |
| 3191 | |
| 3192 | /* Power up sgmii */ |
| 3193 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 3194 | mac = netdev_priv(eth->netdev[i]); |
| 3195 | phy_node = of_parse_phandle(mac->of_node, "phy-handle", 0); |
developer | 793f7b4 | 2022-05-20 13:54:51 +0800 | [diff] [blame] | 3196 | if (!phy_node && eth->sgmii->regmap[i]) { |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3197 | mtk_gmac_sgmii_path_setup(eth, i); |
| 3198 | regmap_write(eth->sgmii->regmap[i], SGMSYS_QPHY_PWR_STATE_CTRL, 0); |
| 3199 | } |
| 3200 | } |
| 3201 | |
| 3202 | call_netdevice_notifiers(MTK_FE_RESET_NAT_DONE, eth->netdev[0]); |
| 3203 | pr_info("[%s] HNAT reset done !\n", __func__); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3204 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3205 | call_netdevice_notifiers(MTK_FE_RESET_DONE, eth->netdev[0]); |
| 3206 | pr_info("[%s] WiFi SER reset done !\n", __func__); |
| 3207 | |
| 3208 | atomic_dec(&reset_lock); |
| 3209 | if (atomic_read(&force) > 0) |
| 3210 | atomic_dec(&force); |
| 3211 | |
| 3212 | timer_setup(ð->mtk_dma_monitor_timer, mtk_dma_monitor, 0); |
| 3213 | eth->mtk_dma_monitor_timer.expires = jiffies; |
| 3214 | add_timer(ð->mtk_dma_monitor_timer); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3215 | clear_bit_unlock(MTK_RESETTING, ð->state); |
| 3216 | |
| 3217 | rtnl_unlock(); |
| 3218 | } |
| 3219 | |
| 3220 | static int mtk_free_dev(struct mtk_eth *eth) |
| 3221 | { |
| 3222 | int i; |
| 3223 | |
| 3224 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 3225 | if (!eth->netdev[i]) |
| 3226 | continue; |
| 3227 | free_netdev(eth->netdev[i]); |
| 3228 | } |
| 3229 | |
| 3230 | return 0; |
| 3231 | } |
| 3232 | |
| 3233 | static int mtk_unreg_dev(struct mtk_eth *eth) |
| 3234 | { |
| 3235 | int i; |
| 3236 | |
| 3237 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 3238 | if (!eth->netdev[i]) |
| 3239 | continue; |
| 3240 | unregister_netdev(eth->netdev[i]); |
| 3241 | } |
| 3242 | |
| 3243 | return 0; |
| 3244 | } |
| 3245 | |
| 3246 | static int mtk_cleanup(struct mtk_eth *eth) |
| 3247 | { |
| 3248 | mtk_unreg_dev(eth); |
| 3249 | mtk_free_dev(eth); |
| 3250 | cancel_work_sync(ð->pending_work); |
| 3251 | |
| 3252 | return 0; |
| 3253 | } |
| 3254 | |
| 3255 | static int mtk_get_link_ksettings(struct net_device *ndev, |
| 3256 | struct ethtool_link_ksettings *cmd) |
| 3257 | { |
| 3258 | struct mtk_mac *mac = netdev_priv(ndev); |
| 3259 | |
| 3260 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
| 3261 | return -EBUSY; |
| 3262 | |
| 3263 | return phylink_ethtool_ksettings_get(mac->phylink, cmd); |
| 3264 | } |
| 3265 | |
| 3266 | static int mtk_set_link_ksettings(struct net_device *ndev, |
| 3267 | const struct ethtool_link_ksettings *cmd) |
| 3268 | { |
| 3269 | struct mtk_mac *mac = netdev_priv(ndev); |
| 3270 | |
| 3271 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
| 3272 | return -EBUSY; |
| 3273 | |
| 3274 | return phylink_ethtool_ksettings_set(mac->phylink, cmd); |
| 3275 | } |
| 3276 | |
| 3277 | static void mtk_get_drvinfo(struct net_device *dev, |
| 3278 | struct ethtool_drvinfo *info) |
| 3279 | { |
| 3280 | struct mtk_mac *mac = netdev_priv(dev); |
| 3281 | |
| 3282 | strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); |
| 3283 | strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); |
| 3284 | info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); |
| 3285 | } |
| 3286 | |
| 3287 | static u32 mtk_get_msglevel(struct net_device *dev) |
| 3288 | { |
| 3289 | struct mtk_mac *mac = netdev_priv(dev); |
| 3290 | |
| 3291 | return mac->hw->msg_enable; |
| 3292 | } |
| 3293 | |
| 3294 | static void mtk_set_msglevel(struct net_device *dev, u32 value) |
| 3295 | { |
| 3296 | struct mtk_mac *mac = netdev_priv(dev); |
| 3297 | |
| 3298 | mac->hw->msg_enable = value; |
| 3299 | } |
| 3300 | |
| 3301 | static int mtk_nway_reset(struct net_device *dev) |
| 3302 | { |
| 3303 | struct mtk_mac *mac = netdev_priv(dev); |
| 3304 | |
| 3305 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
| 3306 | return -EBUSY; |
| 3307 | |
| 3308 | if (!mac->phylink) |
| 3309 | return -ENOTSUPP; |
| 3310 | |
| 3311 | return phylink_ethtool_nway_reset(mac->phylink); |
| 3312 | } |
| 3313 | |
| 3314 | static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
| 3315 | { |
| 3316 | int i; |
| 3317 | |
| 3318 | switch (stringset) { |
| 3319 | case ETH_SS_STATS: |
| 3320 | for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { |
| 3321 | memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); |
| 3322 | data += ETH_GSTRING_LEN; |
| 3323 | } |
| 3324 | break; |
| 3325 | } |
| 3326 | } |
| 3327 | |
| 3328 | static int mtk_get_sset_count(struct net_device *dev, int sset) |
| 3329 | { |
| 3330 | switch (sset) { |
| 3331 | case ETH_SS_STATS: |
| 3332 | return ARRAY_SIZE(mtk_ethtool_stats); |
| 3333 | default: |
| 3334 | return -EOPNOTSUPP; |
| 3335 | } |
| 3336 | } |
| 3337 | |
| 3338 | static void mtk_get_ethtool_stats(struct net_device *dev, |
| 3339 | struct ethtool_stats *stats, u64 *data) |
| 3340 | { |
| 3341 | struct mtk_mac *mac = netdev_priv(dev); |
| 3342 | struct mtk_hw_stats *hwstats = mac->hw_stats; |
| 3343 | u64 *data_src, *data_dst; |
| 3344 | unsigned int start; |
| 3345 | int i; |
| 3346 | |
| 3347 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
| 3348 | return; |
| 3349 | |
| 3350 | if (netif_running(dev) && netif_device_present(dev)) { |
| 3351 | if (spin_trylock_bh(&hwstats->stats_lock)) { |
| 3352 | mtk_stats_update_mac(mac); |
| 3353 | spin_unlock_bh(&hwstats->stats_lock); |
| 3354 | } |
| 3355 | } |
| 3356 | |
| 3357 | data_src = (u64 *)hwstats; |
| 3358 | |
| 3359 | do { |
| 3360 | data_dst = data; |
| 3361 | start = u64_stats_fetch_begin_irq(&hwstats->syncp); |
| 3362 | |
| 3363 | for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) |
| 3364 | *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); |
| 3365 | } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); |
| 3366 | } |
| 3367 | |
| 3368 | static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, |
| 3369 | u32 *rule_locs) |
| 3370 | { |
| 3371 | int ret = -EOPNOTSUPP; |
| 3372 | |
| 3373 | switch (cmd->cmd) { |
| 3374 | case ETHTOOL_GRXRINGS: |
| 3375 | if (dev->hw_features & NETIF_F_LRO) { |
| 3376 | cmd->data = MTK_MAX_RX_RING_NUM; |
| 3377 | ret = 0; |
| 3378 | } |
| 3379 | break; |
| 3380 | case ETHTOOL_GRXCLSRLCNT: |
| 3381 | if (dev->hw_features & NETIF_F_LRO) { |
| 3382 | struct mtk_mac *mac = netdev_priv(dev); |
| 3383 | |
| 3384 | cmd->rule_cnt = mac->hwlro_ip_cnt; |
| 3385 | ret = 0; |
| 3386 | } |
| 3387 | break; |
| 3388 | case ETHTOOL_GRXCLSRULE: |
| 3389 | if (dev->hw_features & NETIF_F_LRO) |
| 3390 | ret = mtk_hwlro_get_fdir_entry(dev, cmd); |
| 3391 | break; |
| 3392 | case ETHTOOL_GRXCLSRLALL: |
| 3393 | if (dev->hw_features & NETIF_F_LRO) |
| 3394 | ret = mtk_hwlro_get_fdir_all(dev, cmd, |
| 3395 | rule_locs); |
| 3396 | break; |
| 3397 | default: |
| 3398 | break; |
| 3399 | } |
| 3400 | |
| 3401 | return ret; |
| 3402 | } |
| 3403 | |
| 3404 | static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) |
| 3405 | { |
| 3406 | int ret = -EOPNOTSUPP; |
| 3407 | |
| 3408 | switch (cmd->cmd) { |
| 3409 | case ETHTOOL_SRXCLSRLINS: |
| 3410 | if (dev->hw_features & NETIF_F_LRO) |
| 3411 | ret = mtk_hwlro_add_ipaddr(dev, cmd); |
| 3412 | break; |
| 3413 | case ETHTOOL_SRXCLSRLDEL: |
| 3414 | if (dev->hw_features & NETIF_F_LRO) |
| 3415 | ret = mtk_hwlro_del_ipaddr(dev, cmd); |
| 3416 | break; |
| 3417 | default: |
| 3418 | break; |
| 3419 | } |
| 3420 | |
| 3421 | return ret; |
| 3422 | } |
| 3423 | |
| 3424 | static const struct ethtool_ops mtk_ethtool_ops = { |
| 3425 | .get_link_ksettings = mtk_get_link_ksettings, |
| 3426 | .set_link_ksettings = mtk_set_link_ksettings, |
| 3427 | .get_drvinfo = mtk_get_drvinfo, |
| 3428 | .get_msglevel = mtk_get_msglevel, |
| 3429 | .set_msglevel = mtk_set_msglevel, |
| 3430 | .nway_reset = mtk_nway_reset, |
| 3431 | .get_link = ethtool_op_get_link, |
| 3432 | .get_strings = mtk_get_strings, |
| 3433 | .get_sset_count = mtk_get_sset_count, |
| 3434 | .get_ethtool_stats = mtk_get_ethtool_stats, |
| 3435 | .get_rxnfc = mtk_get_rxnfc, |
| 3436 | .set_rxnfc = mtk_set_rxnfc, |
| 3437 | }; |
| 3438 | |
| 3439 | static const struct net_device_ops mtk_netdev_ops = { |
| 3440 | .ndo_init = mtk_init, |
| 3441 | .ndo_uninit = mtk_uninit, |
| 3442 | .ndo_open = mtk_open, |
| 3443 | .ndo_stop = mtk_stop, |
| 3444 | .ndo_start_xmit = mtk_start_xmit, |
| 3445 | .ndo_set_mac_address = mtk_set_mac_address, |
| 3446 | .ndo_validate_addr = eth_validate_addr, |
| 3447 | .ndo_do_ioctl = mtk_do_ioctl, |
| 3448 | .ndo_tx_timeout = mtk_tx_timeout, |
| 3449 | .ndo_get_stats64 = mtk_get_stats64, |
| 3450 | .ndo_fix_features = mtk_fix_features, |
| 3451 | .ndo_set_features = mtk_set_features, |
| 3452 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 3453 | .ndo_poll_controller = mtk_poll_controller, |
| 3454 | #endif |
| 3455 | }; |
| 3456 | |
| 3457 | static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) |
| 3458 | { |
| 3459 | const __be32 *_id = of_get_property(np, "reg", NULL); |
| 3460 | struct phylink *phylink; |
| 3461 | int phy_mode, id, err; |
| 3462 | struct mtk_mac *mac; |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 3463 | struct mtk_phylink_priv *phylink_priv; |
| 3464 | struct fwnode_handle *fixed_node; |
| 3465 | struct gpio_desc *desc; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3466 | |
| 3467 | if (!_id) { |
| 3468 | dev_err(eth->dev, "missing mac id\n"); |
| 3469 | return -EINVAL; |
| 3470 | } |
| 3471 | |
| 3472 | id = be32_to_cpup(_id); |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 3473 | if (id < 0 || id >= MTK_MAC_COUNT) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3474 | dev_err(eth->dev, "%d is not a valid mac id\n", id); |
| 3475 | return -EINVAL; |
| 3476 | } |
| 3477 | |
| 3478 | if (eth->netdev[id]) { |
| 3479 | dev_err(eth->dev, "duplicate mac id found: %d\n", id); |
| 3480 | return -EINVAL; |
| 3481 | } |
| 3482 | |
| 3483 | eth->netdev[id] = alloc_etherdev(sizeof(*mac)); |
| 3484 | if (!eth->netdev[id]) { |
| 3485 | dev_err(eth->dev, "alloc_etherdev failed\n"); |
| 3486 | return -ENOMEM; |
| 3487 | } |
| 3488 | mac = netdev_priv(eth->netdev[id]); |
| 3489 | eth->mac[id] = mac; |
| 3490 | mac->id = id; |
| 3491 | mac->hw = eth; |
| 3492 | mac->of_node = np; |
| 3493 | |
| 3494 | memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); |
| 3495 | mac->hwlro_ip_cnt = 0; |
| 3496 | |
| 3497 | mac->hw_stats = devm_kzalloc(eth->dev, |
| 3498 | sizeof(*mac->hw_stats), |
| 3499 | GFP_KERNEL); |
| 3500 | if (!mac->hw_stats) { |
| 3501 | dev_err(eth->dev, "failed to allocate counter memory\n"); |
| 3502 | err = -ENOMEM; |
| 3503 | goto free_netdev; |
| 3504 | } |
| 3505 | spin_lock_init(&mac->hw_stats->stats_lock); |
| 3506 | u64_stats_init(&mac->hw_stats->syncp); |
| 3507 | mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; |
| 3508 | |
| 3509 | /* phylink create */ |
| 3510 | phy_mode = of_get_phy_mode(np); |
| 3511 | if (phy_mode < 0) { |
| 3512 | dev_err(eth->dev, "incorrect phy-mode\n"); |
| 3513 | err = -EINVAL; |
| 3514 | goto free_netdev; |
| 3515 | } |
| 3516 | |
| 3517 | /* mac config is not set */ |
| 3518 | mac->interface = PHY_INTERFACE_MODE_NA; |
| 3519 | mac->mode = MLO_AN_PHY; |
| 3520 | mac->speed = SPEED_UNKNOWN; |
| 3521 | |
| 3522 | mac->phylink_config.dev = ð->netdev[id]->dev; |
| 3523 | mac->phylink_config.type = PHYLINK_NETDEV; |
| 3524 | |
| 3525 | phylink = phylink_create(&mac->phylink_config, |
| 3526 | of_fwnode_handle(mac->of_node), |
| 3527 | phy_mode, &mtk_phylink_ops); |
| 3528 | if (IS_ERR(phylink)) { |
| 3529 | err = PTR_ERR(phylink); |
| 3530 | goto free_netdev; |
| 3531 | } |
| 3532 | |
| 3533 | mac->phylink = phylink; |
| 3534 | |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 3535 | fixed_node = fwnode_get_named_child_node(of_fwnode_handle(mac->of_node), |
| 3536 | "fixed-link"); |
| 3537 | if (fixed_node) { |
| 3538 | desc = fwnode_get_named_gpiod(fixed_node, "link-gpio", |
| 3539 | 0, GPIOD_IN, "?"); |
| 3540 | if (!IS_ERR(desc)) { |
| 3541 | struct device_node *phy_np; |
| 3542 | const char *label; |
| 3543 | int irq, phyaddr; |
| 3544 | |
| 3545 | phylink_priv = &mac->phylink_priv; |
| 3546 | |
| 3547 | phylink_priv->desc = desc; |
| 3548 | phylink_priv->id = id; |
| 3549 | phylink_priv->link = -1; |
| 3550 | |
| 3551 | irq = gpiod_to_irq(desc); |
| 3552 | if (irq > 0) { |
| 3553 | devm_request_irq(eth->dev, irq, mtk_handle_irq_fixed_link, |
| 3554 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, |
| 3555 | "ethernet:fixed link", mac); |
| 3556 | } |
| 3557 | |
| 3558 | if (!of_property_read_string(to_of_node(fixed_node), "label", &label)) |
| 3559 | strcpy(phylink_priv->label, label); |
| 3560 | |
| 3561 | phy_np = of_parse_phandle(to_of_node(fixed_node), "phy-handle", 0); |
| 3562 | if (phy_np) { |
| 3563 | if (!of_property_read_u32(phy_np, "reg", &phyaddr)) |
| 3564 | phylink_priv->phyaddr = phyaddr; |
| 3565 | } |
| 3566 | } |
| 3567 | fwnode_handle_put(fixed_node); |
| 3568 | } |
| 3569 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3570 | SET_NETDEV_DEV(eth->netdev[id], eth->dev); |
| 3571 | eth->netdev[id]->watchdog_timeo = 5 * HZ; |
| 3572 | eth->netdev[id]->netdev_ops = &mtk_netdev_ops; |
| 3573 | eth->netdev[id]->base_addr = (unsigned long)eth->base; |
| 3574 | |
| 3575 | eth->netdev[id]->hw_features = eth->soc->hw_features; |
| 3576 | if (eth->hwlro) |
| 3577 | eth->netdev[id]->hw_features |= NETIF_F_LRO; |
| 3578 | |
| 3579 | eth->netdev[id]->vlan_features = eth->soc->hw_features & |
| 3580 | ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); |
| 3581 | eth->netdev[id]->features |= eth->soc->hw_features; |
| 3582 | eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; |
| 3583 | |
| 3584 | eth->netdev[id]->irq = eth->irq[0]; |
| 3585 | eth->netdev[id]->dev.of_node = np; |
| 3586 | |
| 3587 | return 0; |
| 3588 | |
| 3589 | free_netdev: |
| 3590 | free_netdev(eth->netdev[id]); |
| 3591 | return err; |
| 3592 | } |
| 3593 | |
| 3594 | static int mtk_probe(struct platform_device *pdev) |
| 3595 | { |
| 3596 | struct device_node *mac_np; |
| 3597 | struct mtk_eth *eth; |
| 3598 | int err, i; |
| 3599 | |
| 3600 | eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); |
| 3601 | if (!eth) |
| 3602 | return -ENOMEM; |
| 3603 | |
| 3604 | eth->soc = of_device_get_match_data(&pdev->dev); |
| 3605 | |
| 3606 | eth->dev = &pdev->dev; |
| 3607 | eth->base = devm_platform_ioremap_resource(pdev, 0); |
| 3608 | if (IS_ERR(eth->base)) |
| 3609 | return PTR_ERR(eth->base); |
| 3610 | |
| 3611 | if(eth->soc->has_sram) { |
| 3612 | struct resource *res; |
| 3613 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
developer | 4c32b7a | 2021-11-13 16:46:43 +0800 | [diff] [blame] | 3614 | if (unlikely(!res)) |
| 3615 | return -EINVAL; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3616 | eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; |
| 3617 | } |
| 3618 | |
| 3619 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 3620 | eth->tx_int_mask_reg = MTK_QDMA_INT_MASK; |
| 3621 | eth->tx_int_status_reg = MTK_QDMA_INT_STATUS; |
| 3622 | } else { |
| 3623 | eth->tx_int_mask_reg = MTK_PDMA_INT_MASK; |
| 3624 | eth->tx_int_status_reg = MTK_PDMA_INT_STATUS; |
| 3625 | } |
| 3626 | |
| 3627 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
| 3628 | eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA; |
| 3629 | eth->ip_align = NET_IP_ALIGN; |
| 3630 | } else { |
developer | a2bdbd5 | 2021-05-31 19:10:17 +0800 | [diff] [blame] | 3631 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3632 | eth->rx_dma_l4_valid = RX_DMA_L4_VALID_V2; |
| 3633 | else |
| 3634 | eth->rx_dma_l4_valid = RX_DMA_L4_VALID; |
| 3635 | } |
| 3636 | |
| 3637 | spin_lock_init(ð->page_lock); |
| 3638 | spin_lock_init(ð->tx_irq_lock); |
| 3639 | spin_lock_init(ð->rx_irq_lock); |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 3640 | spin_lock_init(ð->syscfg0_lock); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3641 | |
| 3642 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
| 3643 | eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| 3644 | "mediatek,ethsys"); |
| 3645 | if (IS_ERR(eth->ethsys)) { |
| 3646 | dev_err(&pdev->dev, "no ethsys regmap found\n"); |
| 3647 | return PTR_ERR(eth->ethsys); |
| 3648 | } |
| 3649 | } |
| 3650 | |
| 3651 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { |
| 3652 | eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| 3653 | "mediatek,infracfg"); |
| 3654 | if (IS_ERR(eth->infra)) { |
| 3655 | dev_err(&pdev->dev, "no infracfg regmap found\n"); |
| 3656 | return PTR_ERR(eth->infra); |
| 3657 | } |
| 3658 | } |
| 3659 | |
| 3660 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { |
| 3661 | eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), |
| 3662 | GFP_KERNEL); |
| 3663 | if (!eth->sgmii) |
| 3664 | return -ENOMEM; |
| 3665 | |
| 3666 | err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, |
| 3667 | eth->soc->ana_rgc3); |
| 3668 | |
| 3669 | if (err) |
| 3670 | return err; |
| 3671 | } |
| 3672 | |
| 3673 | if (eth->soc->required_pctl) { |
| 3674 | eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| 3675 | "mediatek,pctl"); |
| 3676 | if (IS_ERR(eth->pctl)) { |
| 3677 | dev_err(&pdev->dev, "no pctl regmap found\n"); |
| 3678 | return PTR_ERR(eth->pctl); |
| 3679 | } |
| 3680 | } |
| 3681 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3682 | for (i = 0; i < MTK_MAX_IRQ_NUM; i++) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3683 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) |
| 3684 | eth->irq[i] = eth->irq[0]; |
| 3685 | else |
| 3686 | eth->irq[i] = platform_get_irq(pdev, i); |
| 3687 | if (eth->irq[i] < 0) { |
| 3688 | dev_err(&pdev->dev, "no IRQ%d resource found\n", i); |
| 3689 | return -ENXIO; |
| 3690 | } |
| 3691 | } |
| 3692 | |
| 3693 | for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { |
| 3694 | eth->clks[i] = devm_clk_get(eth->dev, |
| 3695 | mtk_clks_source_name[i]); |
| 3696 | if (IS_ERR(eth->clks[i])) { |
| 3697 | if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) |
| 3698 | return -EPROBE_DEFER; |
| 3699 | if (eth->soc->required_clks & BIT(i)) { |
| 3700 | dev_err(&pdev->dev, "clock %s not found\n", |
| 3701 | mtk_clks_source_name[i]); |
| 3702 | return -EINVAL; |
| 3703 | } |
| 3704 | eth->clks[i] = NULL; |
| 3705 | } |
| 3706 | } |
| 3707 | |
| 3708 | eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); |
| 3709 | INIT_WORK(ð->pending_work, mtk_pending_work); |
| 3710 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3711 | err = mtk_hw_init(eth, MTK_TYPE_COLD_RESET); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3712 | if (err) |
| 3713 | return err; |
| 3714 | |
| 3715 | eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); |
| 3716 | |
| 3717 | for_each_child_of_node(pdev->dev.of_node, mac_np) { |
| 3718 | if (!of_device_is_compatible(mac_np, |
| 3719 | "mediatek,eth-mac")) |
| 3720 | continue; |
| 3721 | |
| 3722 | if (!of_device_is_available(mac_np)) |
| 3723 | continue; |
| 3724 | |
| 3725 | err = mtk_add_mac(eth, mac_np); |
| 3726 | if (err) { |
| 3727 | of_node_put(mac_np); |
| 3728 | goto err_deinit_hw; |
| 3729 | } |
| 3730 | } |
| 3731 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3732 | err = mtk_napi_init(eth); |
| 3733 | if (err) |
| 3734 | goto err_free_dev; |
| 3735 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3736 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { |
| 3737 | err = devm_request_irq(eth->dev, eth->irq[0], |
| 3738 | mtk_handle_irq, 0, |
| 3739 | dev_name(eth->dev), eth); |
| 3740 | } else { |
| 3741 | err = devm_request_irq(eth->dev, eth->irq[1], |
| 3742 | mtk_handle_irq_tx, 0, |
| 3743 | dev_name(eth->dev), eth); |
| 3744 | if (err) |
| 3745 | goto err_free_dev; |
| 3746 | |
| 3747 | err = devm_request_irq(eth->dev, eth->irq[2], |
| 3748 | mtk_handle_irq_rx, 0, |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3749 | dev_name(eth->dev), ð->rx_napi[0]); |
| 3750 | if (err) |
| 3751 | goto err_free_dev; |
| 3752 | |
developer | 793f7b4 | 2022-05-20 13:54:51 +0800 | [diff] [blame] | 3753 | if (MTK_MAX_IRQ_NUM > 3) { |
| 3754 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 3755 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) { |
| 3756 | err = devm_request_irq(eth->dev, |
| 3757 | eth->irq[2 + i], |
| 3758 | mtk_handle_irq_rx, 0, |
| 3759 | dev_name(eth->dev), |
| 3760 | ð->rx_napi[i]); |
| 3761 | if (err) |
| 3762 | goto err_free_dev; |
| 3763 | } |
| 3764 | } else { |
| 3765 | err = devm_request_irq(eth->dev, eth->irq[3], |
| 3766 | mtk_handle_fe_irq, 0, |
| 3767 | dev_name(eth->dev), eth); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3768 | if (err) |
| 3769 | goto err_free_dev; |
| 3770 | } |
| 3771 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3772 | } |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3773 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3774 | if (err) |
| 3775 | goto err_free_dev; |
| 3776 | |
| 3777 | /* No MT7628/88 support yet */ |
| 3778 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
| 3779 | err = mtk_mdio_init(eth); |
| 3780 | if (err) |
| 3781 | goto err_free_dev; |
| 3782 | } |
| 3783 | |
| 3784 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
| 3785 | if (!eth->netdev[i]) |
| 3786 | continue; |
| 3787 | |
| 3788 | err = register_netdev(eth->netdev[i]); |
| 3789 | if (err) { |
| 3790 | dev_err(eth->dev, "error bringing up device\n"); |
| 3791 | goto err_deinit_mdio; |
| 3792 | } else |
| 3793 | netif_info(eth, probe, eth->netdev[i], |
| 3794 | "mediatek frame engine at 0x%08lx, irq %d\n", |
| 3795 | eth->netdev[i]->base_addr, eth->irq[0]); |
| 3796 | } |
| 3797 | |
| 3798 | /* we run 2 devices on the same DMA ring so we need a dummy device |
| 3799 | * for NAPI to work |
| 3800 | */ |
| 3801 | init_dummy_netdev(ð->dummy_dev); |
| 3802 | netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, |
| 3803 | MTK_NAPI_WEIGHT); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3804 | netif_napi_add(ð->dummy_dev, ð->rx_napi[0].napi, mtk_napi_rx, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3805 | MTK_NAPI_WEIGHT); |
| 3806 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3807 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 3808 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) |
| 3809 | netif_napi_add(ð->dummy_dev, ð->rx_napi[i].napi, |
| 3810 | mtk_napi_rx, MTK_NAPI_WEIGHT); |
| 3811 | } |
| 3812 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3813 | mtketh_debugfs_init(eth); |
| 3814 | debug_proc_init(eth); |
| 3815 | |
| 3816 | platform_set_drvdata(pdev, eth); |
| 3817 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3818 | register_netdevice_notifier(&mtk_eth_netdevice_nb); |
developer | 793f7b4 | 2022-05-20 13:54:51 +0800 | [diff] [blame] | 3819 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3820 | timer_setup(ð->mtk_dma_monitor_timer, mtk_dma_monitor, 0); |
| 3821 | eth->mtk_dma_monitor_timer.expires = jiffies; |
| 3822 | add_timer(ð->mtk_dma_monitor_timer); |
developer | 793f7b4 | 2022-05-20 13:54:51 +0800 | [diff] [blame] | 3823 | #endif |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3824 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3825 | return 0; |
| 3826 | |
| 3827 | err_deinit_mdio: |
| 3828 | mtk_mdio_cleanup(eth); |
| 3829 | err_free_dev: |
| 3830 | mtk_free_dev(eth); |
| 3831 | err_deinit_hw: |
| 3832 | mtk_hw_deinit(eth); |
| 3833 | |
| 3834 | return err; |
| 3835 | } |
| 3836 | |
| 3837 | static int mtk_remove(struct platform_device *pdev) |
| 3838 | { |
| 3839 | struct mtk_eth *eth = platform_get_drvdata(pdev); |
| 3840 | struct mtk_mac *mac; |
| 3841 | int i; |
| 3842 | |
| 3843 | /* stop all devices to make sure that dma is properly shut down */ |
| 3844 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 3845 | if (!eth->netdev[i]) |
| 3846 | continue; |
| 3847 | mtk_stop(eth->netdev[i]); |
| 3848 | mac = netdev_priv(eth->netdev[i]); |
| 3849 | phylink_disconnect_phy(mac->phylink); |
| 3850 | } |
| 3851 | |
| 3852 | mtk_hw_deinit(eth); |
| 3853 | |
| 3854 | netif_napi_del(ð->tx_napi); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3855 | netif_napi_del(ð->rx_napi[0].napi); |
| 3856 | |
| 3857 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 3858 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) |
| 3859 | netif_napi_del(ð->rx_napi[i].napi); |
| 3860 | } |
| 3861 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3862 | mtk_cleanup(eth); |
| 3863 | mtk_mdio_cleanup(eth); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3864 | unregister_netdevice_notifier(&mtk_eth_netdevice_nb); |
| 3865 | del_timer_sync(ð->mtk_dma_monitor_timer); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3866 | |
| 3867 | return 0; |
| 3868 | } |
| 3869 | |
| 3870 | static const struct mtk_soc_data mt2701_data = { |
| 3871 | .caps = MT7623_CAPS | MTK_HWLRO, |
| 3872 | .hw_features = MTK_HW_FEATURES, |
| 3873 | .required_clks = MT7623_CLKS_BITMAP, |
| 3874 | .required_pctl = true, |
| 3875 | .has_sram = false, |
| 3876 | }; |
| 3877 | |
| 3878 | static const struct mtk_soc_data mt7621_data = { |
| 3879 | .caps = MT7621_CAPS, |
| 3880 | .hw_features = MTK_HW_FEATURES, |
| 3881 | .required_clks = MT7621_CLKS_BITMAP, |
| 3882 | .required_pctl = false, |
| 3883 | .has_sram = false, |
| 3884 | }; |
| 3885 | |
| 3886 | static const struct mtk_soc_data mt7622_data = { |
| 3887 | .ana_rgc3 = 0x2028, |
| 3888 | .caps = MT7622_CAPS | MTK_HWLRO, |
| 3889 | .hw_features = MTK_HW_FEATURES, |
| 3890 | .required_clks = MT7622_CLKS_BITMAP, |
| 3891 | .required_pctl = false, |
| 3892 | .has_sram = false, |
| 3893 | }; |
| 3894 | |
| 3895 | static const struct mtk_soc_data mt7623_data = { |
| 3896 | .caps = MT7623_CAPS | MTK_HWLRO, |
| 3897 | .hw_features = MTK_HW_FEATURES, |
| 3898 | .required_clks = MT7623_CLKS_BITMAP, |
| 3899 | .required_pctl = true, |
| 3900 | .has_sram = false, |
| 3901 | }; |
| 3902 | |
| 3903 | static const struct mtk_soc_data mt7629_data = { |
| 3904 | .ana_rgc3 = 0x128, |
| 3905 | .caps = MT7629_CAPS | MTK_HWLRO, |
| 3906 | .hw_features = MTK_HW_FEATURES, |
| 3907 | .required_clks = MT7629_CLKS_BITMAP, |
| 3908 | .required_pctl = false, |
| 3909 | .has_sram = false, |
| 3910 | }; |
| 3911 | |
| 3912 | static const struct mtk_soc_data mt7986_data = { |
| 3913 | .ana_rgc3 = 0x128, |
| 3914 | .caps = MT7986_CAPS, |
developer | cba5f4e | 2021-05-06 14:01:53 +0800 | [diff] [blame] | 3915 | .hw_features = MTK_HW_FEATURES, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3916 | .required_clks = MT7986_CLKS_BITMAP, |
| 3917 | .required_pctl = false, |
| 3918 | .has_sram = true, |
| 3919 | }; |
| 3920 | |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 3921 | static const struct mtk_soc_data mt7981_data = { |
| 3922 | .ana_rgc3 = 0x128, |
| 3923 | .caps = MT7981_CAPS, |
developer | 7377b0b | 2021-11-18 14:54:47 +0800 | [diff] [blame] | 3924 | .hw_features = MTK_HW_FEATURES, |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 3925 | .required_clks = MT7981_CLKS_BITMAP, |
| 3926 | .required_pctl = false, |
| 3927 | .has_sram = true, |
| 3928 | }; |
| 3929 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3930 | static const struct mtk_soc_data rt5350_data = { |
| 3931 | .caps = MT7628_CAPS, |
| 3932 | .hw_features = MTK_HW_FEATURES_MT7628, |
| 3933 | .required_clks = MT7628_CLKS_BITMAP, |
| 3934 | .required_pctl = false, |
| 3935 | .has_sram = false, |
| 3936 | }; |
| 3937 | |
| 3938 | const struct of_device_id of_mtk_match[] = { |
| 3939 | { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, |
| 3940 | { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, |
| 3941 | { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, |
| 3942 | { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, |
| 3943 | { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, |
| 3944 | { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 3945 | { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data}, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3946 | { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, |
| 3947 | {}, |
| 3948 | }; |
| 3949 | MODULE_DEVICE_TABLE(of, of_mtk_match); |
| 3950 | |
| 3951 | static struct platform_driver mtk_driver = { |
| 3952 | .probe = mtk_probe, |
| 3953 | .remove = mtk_remove, |
| 3954 | .driver = { |
| 3955 | .name = "mtk_soc_eth", |
| 3956 | .of_match_table = of_mtk_match, |
| 3957 | }, |
| 3958 | }; |
| 3959 | |
| 3960 | module_platform_driver(mtk_driver); |
| 3961 | |
| 3962 | MODULE_LICENSE("GPL"); |
| 3963 | MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); |
| 3964 | MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); |