blob: 4772db383722354b38ec679206df5dcdf6049517 [file] [log] [blame]
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +09001#
2# I2C subsystem configuration
3#
4
5menu "I2C support"
6
Masahiro Yamadacd5cf8e2015-01-13 12:44:35 +09007config DM_I2C
8 bool "Enable Driver Model for I2C drivers"
9 depends on DM
10 help
Przemyslaw Marczake5fa1212015-03-31 18:57:17 +020011 Enable driver model for I2C. The I2C uclass interface: probe, read,
12 write and speed, is implemented with the bus drivers operations,
13 which provide methods for bus setting and data transfer. Each chip
14 device (bus child) info is kept as parent platdata. The interface
15 is defined in include/i2c.h. When i2c bus driver supports the i2c
16 uclass, but the device drivers not, then DM_I2C_COMPAT config can
17 be used as compatibility layer.
Masahiro Yamada96a42ed2015-01-13 12:44:36 +090018
Simon Glasse200ee22015-02-13 12:20:48 -070019config DM_I2C_COMPAT
20 bool "Enable I2C compatibility layer"
21 depends on DM
22 help
23 Enable old-style I2C functions for compatibility with existing code.
24 This option can be enabled as a temporary measure to avoid needing
25 to convert all code for a board in a single commit. It should not
26 be enabled for any board in an official release.
27
Simon Glass9ad07af2015-08-03 08:19:23 -060028config I2C_CROS_EC_TUNNEL
29 tristate "Chrome OS EC tunnel I2C bus"
30 depends on CROS_EC
31 help
32 This provides an I2C bus that will tunnel i2c commands through to
33 the other side of the Chrome OS EC to the I2C bus connected there.
34 This will work whatever the interface used to talk to the EC (SPI,
35 I2C or LPC). Some Chromebooks use this when the hardware design
36 does not allow direct access to the main PMIC from the AP.
37
Simon Glasseb2cc512015-08-03 08:19:24 -060038config I2C_CROS_EC_LDO
39 bool "Provide access to LDOs on the Chrome OS EC"
40 depends on CROS_EC
41 ---help---
42 On many Chromebooks the main PMIC is inaccessible to the AP. This is
43 often dealt with by using an I2C pass-through interface provided by
44 the EC. On some unfortunate models (e.g. Spring) the pass-through
45 is not available, and an LDO message is available instead. This
46 option enables a driver which provides very basic access to those
47 regulators, via the EC. We implement this as an I2C bus which
48 emulates just the TPS65090 messages we know about. This is done to
49 avoid duplicating the logic in the TPS65090 regulator driver for
50 enabling/disabling an LDO.
Simon Glass9ad07af2015-08-03 08:19:23 -060051
Lukasz Majewski0a556272017-03-21 12:08:25 +010052config I2C_SET_DEFAULT_BUS_NUM
53 bool "Set default I2C bus number"
54 depends on DM_I2C
55 help
56 Set default number of I2C bus to be accessed. This option provides
57 behaviour similar to old (i.e. pre DM) I2C bus driver.
58
59config I2C_DEFAULT_BUS_NUMBER
60 hex "I2C default bus number"
61 depends on I2C_SET_DEFAULT_BUS_NUM
62 default 0x0
63 help
64 Number of default I2C bus to use
65
Przemyslaw Marczakd3aa7e12015-03-31 18:57:18 +020066config DM_I2C_GPIO
67 bool "Enable Driver Model for software emulated I2C bus driver"
68 depends on DM_I2C && DM_GPIO
69 help
70 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
71 configuration is given by the device tree. Kernel-style device tree
72 bindings are supported.
73 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
74
Songjun Wu26d88282016-06-20 13:22:38 +080075config SYS_I2C_AT91
76 bool "Atmel I2C driver"
77 depends on DM_I2C && ARCH_AT91
78 help
79 Add support for the Atmel I2C driver. A serious problem is that there
80 is no documented way to issue repeated START conditions for more than
81 two messages, as needed to support combined I2C messages. Use the
82 i2c-gpio driver unless your system can cope with this limitation.
83 Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
84
mario.six@gdsys.cc349686c2016-04-25 08:31:09 +020085config SYS_I2C_FSL
86 bool "Freescale I2C bus driver"
87 depends on DM_I2C
88 help
89 Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
90 MPC85xx processors.
91
Moritz Fischer0075dac2015-12-28 09:47:11 -080092config SYS_I2C_CADENCE
93 tristate "Cadence I2C Controller"
94 depends on DM_I2C && (ARCH_ZYNQ || ARM64)
95 help
96 Say yes here to select Cadence I2C Host Controller. This controller is
97 e.g. used by Xilinx Zynq.
98
Adam Forddecc8952018-08-10 05:05:22 -050099config SYS_I2C_DAVINCI
100 bool "Davinci I2C Controller"
101 depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
102 help
103 Say yes here to add support for Davinci and Keystone I2C controller
104
Stefan Roeseb71955f2016-04-28 09:47:17 +0200105config SYS_I2C_DW
106 bool "Designware I2C Controller"
107 default n
108 help
109 Say yes here to select the Designware I2C Host Controller. This
110 controller is used in various SoCs, e.g. the ST SPEAr, Altera
111 SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
112
Stefan Roese38fe7dc2016-04-28 09:47:19 +0200113config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
114 bool "DW I2C Enable Status Register not supported"
115 depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
116 TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
117 default y
118 help
119 Some versions of the Designware I2C controller do not support the
120 enable status register. This config option can be enabled in such
121 cases.
122
maxims@google.com7f613312017-04-17 12:00:30 -0700123config SYS_I2C_ASPEED
124 bool "Aspeed I2C Controller"
125 depends on DM_I2C && ARCH_ASPEED
126 help
127 Say yes here to select Aspeed I2C Host Controller. The driver
128 supports AST2500 and AST2400 controllers, but is very limited.
129 Only single master mode is supported and only byte-by-byte
130 synchronous reads and writes are supported, no Pool Buffers or DMA.
131
Simon Glass5e66fdc2016-01-17 16:11:44 -0700132config SYS_I2C_INTEL
133 bool "Intel I2C/SMBUS driver"
134 depends on DM_I2C
135 help
136 Add support for the Intel SMBUS driver. So far this driver is just
137 a stub which perhaps some basic init. There is no implementation of
138 the I2C API meaning that any I2C operations will immediately fail
139 for now.
140
Peng Fand684adb2017-02-24 09:54:18 +0800141config SYS_I2C_IMX_LPI2C
142 bool "NXP i.MX LPI2C driver"
Peng Fand684adb2017-02-24 09:54:18 +0800143 help
144 Add support for the NXP i.MX LPI2C driver.
145
Beniamino Galvanid5b199c2017-10-29 10:09:00 +0100146config SYS_I2C_MESON
147 bool "Amlogic Meson I2C driver"
148 depends on DM_I2C && ARCH_MESON
149 help
Beniamino Galvani83b153d2017-11-26 17:40:54 +0100150 Add support for the I2C controller available in Amlogic Meson
151 SoCs. The controller supports programmable bus speed including
152 standard (100kbits/s) and fast (400kbit/s) speed and allows the
153 software to define a flexible format of the bit streams. It has an
154 internal buffer holding up to 8 bytes for transfers and supports
155 both 7-bit and 10-bit addresses.
Beniamino Galvanid5b199c2017-10-29 10:09:00 +0100156
Jagan Teki0aedd7f2016-12-06 00:00:57 +0100157config SYS_I2C_MXC
Sriram Dash7122a0c2018-02-06 11:26:30 +0530158 bool "NXP MXC I2C driver"
Jagan Teki0aedd7f2016-12-06 00:00:57 +0100159 help
Chris Packham94d0d3d2019-01-13 22:13:25 +1300160 Add support for the NXP I2C driver. This supports up to four bus
161 channels and operating on standard mode up to 100 kbits/s and fast
162 mode up to 400 kbits/s.
Jagan Teki0aedd7f2016-12-06 00:00:57 +0100163
Trent Piepho92ebcba2019-05-08 23:30:06 +0000164# These settings are not used with DM_I2C, however SPL doesn't use
165# DM_I2C even if DM_I2C is enabled, and so might use these settings even
166# when main u-boot does not!
167if SYS_I2C_MXC && (!DM_I2C || SPL)
Sriram Dash7122a0c2018-02-06 11:26:30 +0530168config SYS_I2C_MXC_I2C1
169 bool "NXP MXC I2C1"
170 help
171 Add support for NXP MXC I2C Controller 1.
172 Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
173
174config SYS_I2C_MXC_I2C2
175 bool "NXP MXC I2C2"
176 help
177 Add support for NXP MXC I2C Controller 2.
178 Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
179
180config SYS_I2C_MXC_I2C3
181 bool "NXP MXC I2C3"
182 help
183 Add support for NXP MXC I2C Controller 3.
184 Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
185
186config SYS_I2C_MXC_I2C4
187 bool "NXP MXC I2C4"
188 help
189 Add support for NXP MXC I2C Controller 4.
190 Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
Sriram Dasha64aa192018-02-06 11:26:31 +0530191
192config SYS_I2C_MXC_I2C5
193 bool "NXP MXC I2C5"
194 help
195 Add support for NXP MXC I2C Controller 5.
196 Required for SoCs which have I2C MXC controller 5 eg LX2160A
197
198config SYS_I2C_MXC_I2C6
199 bool "NXP MXC I2C6"
200 help
201 Add support for NXP MXC I2C Controller 6.
202 Required for SoCs which have I2C MXC controller 6 eg LX2160A
203
204config SYS_I2C_MXC_I2C7
205 bool "NXP MXC I2C7"
206 help
207 Add support for NXP MXC I2C Controller 7.
208 Required for SoCs which have I2C MXC controller 7 eg LX2160A
209
210config SYS_I2C_MXC_I2C8
211 bool "NXP MXC I2C8"
212 help
213 Add support for NXP MXC I2C Controller 8.
214 Required for SoCs which have I2C MXC controller 8 eg LX2160A
Sriram Dash7122a0c2018-02-06 11:26:30 +0530215endif
216
217if SYS_I2C_MXC_I2C1
218config SYS_MXC_I2C1_SPEED
219 int "I2C Channel 1 speed"
220 default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
221 default 100000
222 help
223 MXC I2C Channel 1 speed
224
225config SYS_MXC_I2C1_SLAVE
226 int "I2C1 Slave"
227 default 0
228 help
229 MXC I2C1 Slave
230endif
231
232if SYS_I2C_MXC_I2C2
233config SYS_MXC_I2C2_SPEED
234 int "I2C Channel 2 speed"
235 default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
236 default 100000
237 help
238 MXC I2C Channel 2 speed
239
240config SYS_MXC_I2C2_SLAVE
241 int "I2C2 Slave"
242 default 0
243 help
244 MXC I2C2 Slave
245endif
246
247if SYS_I2C_MXC_I2C3
248config SYS_MXC_I2C3_SPEED
249 int "I2C Channel 3 speed"
250 default 100000
251 help
252 MXC I2C Channel 3 speed
253
254config SYS_MXC_I2C3_SLAVE
255 int "I2C3 Slave"
256 default 0
257 help
258 MXC I2C3 Slave
259endif
260
261if SYS_I2C_MXC_I2C4
262config SYS_MXC_I2C4_SPEED
263 int "I2C Channel 4 speed"
264 default 100000
265 help
266 MXC I2C Channel 4 speed
267
268config SYS_MXC_I2C4_SLAVE
269 int "I2C4 Slave"
270 default 0
271 help
272 MXC I2C4 Slave
273endif
274
Sriram Dasha64aa192018-02-06 11:26:31 +0530275if SYS_I2C_MXC_I2C5
276config SYS_MXC_I2C5_SPEED
277 int "I2C Channel 5 speed"
278 default 100000
279 help
280 MXC I2C Channel 5 speed
281
282config SYS_MXC_I2C5_SLAVE
283 int "I2C5 Slave"
284 default 0
285 help
286 MXC I2C5 Slave
287endif
288
289if SYS_I2C_MXC_I2C6
290config SYS_MXC_I2C6_SPEED
291 int "I2C Channel 6 speed"
292 default 100000
293 help
294 MXC I2C Channel 6 speed
295
296config SYS_MXC_I2C6_SLAVE
297 int "I2C6 Slave"
298 default 0
299 help
300 MXC I2C6 Slave
301endif
302
303if SYS_I2C_MXC_I2C7
304config SYS_MXC_I2C7_SPEED
305 int "I2C Channel 7 speed"
306 default 100000
307 help
308 MXC I2C Channel 7 speed
309
310config SYS_MXC_I2C7_SLAVE
311 int "I2C7 Slave"
312 default 0
313 help
314 MXC I2C7 Slave
315endif
316
317if SYS_I2C_MXC_I2C8
318config SYS_MXC_I2C8_SPEED
319 int "I2C Channel 8 speed"
320 default 100000
321 help
322 MXC I2C Channel 8 speed
323
324config SYS_MXC_I2C8_SLAVE
325 int "I2C8 Slave"
326 default 0
327 help
328 MXC I2C8 Slave
329endif
330
Adam Ford85901162017-08-07 13:11:34 -0500331config SYS_I2C_OMAP24XX
332 bool "TI OMAP2+ I2C driver"
Vignesh R64d4f552019-06-04 18:08:11 -0500333 depends on ARCH_OMAP2PLUS || ARCH_K3
Adam Ford85901162017-08-07 13:11:34 -0500334 help
335 Add support for the OMAP2+ I2C driver.
336
Adam Forded3b0822018-01-24 15:21:21 -0600337if SYS_I2C_OMAP24XX
338config SYS_OMAP24_I2C_SLAVE
339 int "I2C Slave addr channel 0"
340 default 1
341 help
342 OMAP24xx I2C Slave address channel 0
343
344config SYS_OMAP24_I2C_SPEED
345 int "I2C Slave channel 0 speed"
346 default 100000
347 help
348 OMAP24xx Slave speed channel 0
349endif
350
Marek Vasut27165962018-04-21 18:57:28 +0200351config SYS_I2C_RCAR_I2C
352 bool "Renesas RCar I2C driver"
353 depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
354 help
355 Support for Renesas RCar I2C controller.
356
Marek Vasut125d8df2017-11-28 08:02:27 +0100357config SYS_I2C_RCAR_IIC
358 bool "Renesas RCar Gen3 IIC driver"
Marek Vasut4bc57a32018-02-17 02:17:40 +0100359 depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
Marek Vasut125d8df2017-11-28 08:02:27 +0100360 help
361 Support for Renesas RCar Gen3 IIC controller.
362
Simon Glass3595f952015-08-30 16:55:39 -0600363config SYS_I2C_ROCKCHIP
364 bool "Rockchip I2C driver"
365 depends on DM_I2C
366 help
367 Add support for the Rockchip I2C driver. This is used with various
368 Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
Chris Packham94d0d3d2019-01-13 22:13:25 +1300369 have several I2C ports and all are provided, controlled by the
Simon Glass3595f952015-08-30 16:55:39 -0600370 device tree.
371
Simon Glass39bc3be2015-03-06 13:19:04 -0700372config SYS_I2C_SANDBOX
373 bool "Sandbox I2C driver"
374 depends on SANDBOX && DM_I2C
375 help
376 Enable I2C support for sandbox. This is an emulation of a real I2C
377 bus. Devices can be attached to the bus using the device tree
Masahiro Yamada8d8371d2017-02-11 12:39:55 +0900378 which specifies the driver to use. See sandbox.dts as an example.
Simon Glass39bc3be2015-03-06 13:19:04 -0700379
Jaehoon Chungf7e6a032017-01-09 14:47:52 +0900380config SYS_I2C_S3C24X0
381 bool "Samsung I2C driver"
382 depends on ARCH_EXYNOS4 && DM_I2C
383 help
384 Support for Samsung I2C controller as Samsung SoCs.
Simon Glass39bc3be2015-03-06 13:19:04 -0700385
Patrice Chotardebf442d2017-08-09 14:45:27 +0200386config SYS_I2C_STM32F7
387 bool "STMicroelectronics STM32F7 I2C support"
Patrick Delaunay85b53972018-03-12 10:46:10 +0100388 depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
Patrice Chotardebf442d2017-08-09 14:45:27 +0200389 help
390 Enable this option to add support for STM32 I2C controller
391 introduced with STM32F7/H7 SoCs. This I2C controller supports :
392 _ Slave and master modes
393 _ Multimaster capability
394 _ Standard-mode (up to 100 kHz)
395 _ Fast-mode (up to 400 kHz)
396 _ Fast-mode Plus (up to 1 MHz)
397 _ 7-bit and 10-bit addressing mode
398 _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
399 _ All 7-bit addresses acknowledge mode
400 _ General call
401 _ Programmable setup and hold times
402 _ Easy to use event management
403 _ Optional clock stretching
404 _ Software reset
405
Peter Robinson12d37d82019-02-20 12:17:26 +0000406config SYS_I2C_TEGRA
407 bool "NVIDIA Tegra internal I2C controller"
408 depends on TEGRA
409 help
410 Support for NVIDIA I2C controller available in Tegra SoCs.
411
Masahiro Yamada96a42ed2015-01-13 12:44:36 +0900412config SYS_I2C_UNIPHIER
413 bool "UniPhier I2C driver"
414 depends on ARCH_UNIPHIER && DM_I2C
415 default y
416 help
Masahiro Yamada563ee4c2015-05-29 17:30:01 +0900417 Support for UniPhier I2C controller driver. This I2C controller
418 is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
Masahiro Yamada4e82e5e2015-01-13 12:44:37 +0900419
420config SYS_I2C_UNIPHIER_F
421 bool "UniPhier FIFO-builtin I2C driver"
422 depends on ARCH_UNIPHIER && DM_I2C
423 default y
424 help
Masahiro Yamada563ee4c2015-05-29 17:30:01 +0900425 Support for UniPhier FIFO-builtin I2C controller driver.
Masahiro Yamada4e82e5e2015-01-13 12:44:37 +0900426 This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
Simon Glass2a80c402015-08-03 08:19:21 -0600427
Heiko Schochera37c1962018-10-11 07:26:33 +0200428config SYS_I2C_VERSATILE
429 bool "Arm Ltd Versatile I2C bus driver"
430 depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || TARGET_VEXPRESS64_JUNO)
431 help
432 Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
433 controller is present in the development boards manufactured by Arm Ltd.
434
mario.six@gdsys.cc355a1272016-07-21 11:57:10 +0200435config SYS_I2C_MVTWSI
436 bool "Marvell I2C driver"
437 depends on DM_I2C
438 help
439 Support for Marvell I2C controllers as used on the orion5x and
440 kirkwood SoC families.
441
Stephen Warren67a83482016-08-08 11:28:27 -0600442config TEGRA186_BPMP_I2C
443 bool "Enable Tegra186 BPMP-based I2C driver"
444 depends on TEGRA186_BPMP
445 help
446 Support for Tegra I2C controllers managed by the BPMP (Boot and
447 Power Management Processor). On Tegra186, some I2C controllers are
448 directly controlled by the main CPU, whereas others are controlled
449 by the BPMP, and can only be accessed by the main CPU via IPC
450 requests to the BPMP. This driver covers the latter case.
451
Adam Fordfa1dd3d2017-08-11 06:39:34 -0500452config SYS_I2C_BUS_MAX
453 int "Max I2C busses"
454 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
455 default 2 if TI816X
456 default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
457 default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
458 default 5 if OMAP54XX
459 help
460 Define the maximum number of available I2C buses.
461
Marek Vasut9de0e2a2018-12-19 12:26:27 +0100462config SYS_I2C_XILINX_XIIC
463 bool "Xilinx AXI I2C driver"
464 depends on DM_I2C
465 help
466 Support for Xilinx AXI I2C controller.
467
Mario Six3bb409c2018-01-15 11:08:11 +0100468config SYS_I2C_IHS
469 bool "gdsys IHS I2C driver"
470 depends on DM_I2C
471 help
472 Support for gdsys IHS I2C driver on FPGA bus.
473
Simon Glass2a80c402015-08-03 08:19:21 -0600474source "drivers/i2c/muxes/Kconfig"
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +0900475
476endmenu