Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Configuration for Versatile Express. Parts were derived from other ARM |
| 4 | * configurations. |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 7 | #ifndef __VEXPRESS_AEMV8_H |
| 8 | #define __VEXPRESS_AEMV8_H |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 9 | |
Peter Hoyes | 16fff30 | 2021-11-11 09:26:01 +0000 | [diff] [blame] | 10 | #include <linux/stringify.h> |
| 11 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 12 | #define CONFIG_REMAKE_ELF |
| 13 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 14 | /* Link Definitions */ |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 15 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
| 16 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) |
| 17 | #else |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 18 | /* ATF loads u-boot here for BASE_FVP model */ |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 19 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 20 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 21 | |
Ryan Harkin | 642aa2c | 2015-10-09 17:18:01 +0100 | [diff] [blame] | 22 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 23 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 24 | /* CS register bases for the original memory map. */ |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 25 | #define V2M_BASE 0x80000000 |
| 26 | #define V2M_PA_BASE 0x00000000 |
| 27 | |
| 28 | #define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000) |
| 29 | #define V2M_PA_CS1 (V2M_PA_BASE + 0x14000000) |
| 30 | #define V2M_PA_CS2 (V2M_PA_BASE + 0x18000000) |
| 31 | #define V2M_PA_CS3 (V2M_PA_BASE + 0x1c000000) |
| 32 | #define V2M_PA_CS4 (V2M_PA_BASE + 0x0c000000) |
| 33 | #define V2M_PA_CS5 (V2M_PA_BASE + 0x10000000) |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 34 | |
| 35 | #define V2M_PERIPH_OFFSET(x) (x << 16) |
| 36 | #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) |
| 37 | #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) |
| 38 | #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) |
| 39 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 40 | /* Common peripherals relative to CS7. */ |
| 41 | #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) |
| 42 | #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) |
| 43 | #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) |
| 44 | #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) |
| 45 | |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 46 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
| 47 | #define V2M_UART0 0x7ff80000 |
| 48 | #define V2M_UART1 0x7ff70000 |
| 49 | #else /* Not Juno */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 50 | #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) |
| 51 | #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) |
| 52 | #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) |
| 53 | #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 54 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 55 | |
| 56 | #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) |
| 57 | |
| 58 | #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) |
| 59 | #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) |
| 60 | |
| 61 | #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) |
| 62 | #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) |
| 63 | |
| 64 | #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) |
| 65 | |
| 66 | #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) |
| 67 | |
| 68 | /* System register offsets. */ |
| 69 | #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) |
| 70 | #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) |
| 71 | #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) |
| 72 | |
| 73 | /* Generic Timer Definitions */ |
Tom Rini | 3a6d453 | 2021-09-03 10:40:28 -0400 | [diff] [blame] | 74 | #define COUNTER_FREQUENCY 24000000 /* 24MHz */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 75 | |
| 76 | /* Generic Interrupt Controller Definitions */ |
David Feng | 79bbde0 | 2014-03-14 14:26:27 +0800 | [diff] [blame] | 77 | #ifdef CONFIG_GICV3 |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 78 | #define GICD_BASE (V2M_PA_BASE + 0x2f000000) |
| 79 | #define GICR_BASE (V2M_PA_BASE + 0x2f100000) |
David Feng | 79bbde0 | 2014-03-14 14:26:27 +0800 | [diff] [blame] | 80 | #else |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 81 | |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 82 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 83 | #define GICD_BASE (0x2C010000) |
| 84 | #define GICC_BASE (0x2C02f000) |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 85 | #else |
| 86 | #define GICD_BASE (V2M_PA_BASE + 0x2f000000) |
| 87 | #define GICC_BASE (V2M_PA_BASE + 0x2c000000) |
David Feng | 79bbde0 | 2014-03-14 14:26:27 +0800 | [diff] [blame] | 88 | #endif |
Linus Walleij | a90caa3 | 2015-03-23 11:06:14 +0100 | [diff] [blame] | 89 | #endif /* !CONFIG_GICV3 */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 90 | |
Peter Hoyes | 8194cda | 2021-11-11 09:26:03 +0000 | [diff] [blame] | 91 | #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && !defined(CONFIG_DM_ETH) |
| 92 | /* The Vexpress64 BASE_FVP simulator uses SMSC91C111 */ |
Bhupesh Sharma | e997f35 | 2014-01-16 09:47:40 -0600 | [diff] [blame] | 93 | #define CONFIG_SMC91111 1 |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 94 | #define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000) |
Linus Walleij | 48b4755 | 2015-02-17 11:35:25 +0100 | [diff] [blame] | 95 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 96 | |
| 97 | /* PL011 Serial Configuration */ |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 98 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
Andre Przywara | d345718 | 2020-04-27 19:18:00 +0100 | [diff] [blame] | 99 | #define CONFIG_PL011_CLOCK 7372800 |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 100 | #else |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 101 | #define CONFIG_PL011_CLOCK 24000000 |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 102 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 103 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 104 | /* BOOTP options */ |
| 105 | #define CONFIG_BOOTP_BOOTFILESIZE |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 106 | |
| 107 | /* Miscellaneous configurable options */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 108 | |
| 109 | /* Physical Memory Map */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 110 | #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ |
Linus Walleij | 0a38bfe | 2015-05-11 10:03:57 +0200 | [diff] [blame] | 111 | /* Top 16MB reserved for secure world use */ |
| 112 | #define DRAM_SEC_SIZE 0x01000000 |
| 113 | #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE |
| 114 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 115 | |
Ryan Harkin | 98d2fff | 2015-11-18 10:39:07 +0000 | [diff] [blame] | 116 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
Ryan Harkin | 98d2fff | 2015-11-18 10:39:07 +0000 | [diff] [blame] | 117 | #define PHYS_SDRAM_2 (0x880000000) |
| 118 | #define PHYS_SDRAM_2_SIZE 0x180000000 |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 119 | #elif CONFIG_NR_DRAM_BANKS == 2 |
Diego Sueiro | 7a02a1b | 2021-02-15 07:27:57 +0000 | [diff] [blame] | 120 | #define PHYS_SDRAM_2 (0x880000000) |
| 121 | #define PHYS_SDRAM_2_SIZE 0x80000000 |
Ryan Harkin | 98d2fff | 2015-11-18 10:39:07 +0000 | [diff] [blame] | 122 | #endif |
| 123 | |
Linus Walleij | 0a38bfe | 2015-05-11 10:03:57 +0200 | [diff] [blame] | 124 | /* Enable memtest */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 125 | |
| 126 | /* Initial environment variables */ |
Linus Walleij | c39566a | 2015-04-05 01:48:32 +0200 | [diff] [blame] | 127 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
Andre Przywara | be03531 | 2021-07-12 00:25:15 +0100 | [diff] [blame] | 128 | /* Copy the kernel and FDT to DRAM memory and boot */ |
| 129 | #define BOOTENV_DEV_AFS(devtypeu, devtypel, instance) \ |
| 130 | "bootcmd_afs=" \ |
| 131 | "afs load ${kernel_name} ${kernel_addr_r} ;"\ |
| 132 | "if test $? -eq 1; then "\ |
| 133 | " echo Loading ${kernel_alt_name} instead of ${kernel_name}; "\ |
| 134 | " afs load ${kernel_alt_name} ${kernel_addr_r};"\ |
| 135 | "fi ; "\ |
| 136 | "afs load ${fdtfile} ${fdt_addr_r} ;"\ |
| 137 | "if test $? -eq 1; then "\ |
| 138 | " echo Loading ${fdt_alt_name} instead of ${fdtfile}; "\ |
| 139 | " afs load ${fdt_alt_name} ${fdt_addr_r}; "\ |
| 140 | "fi ; "\ |
| 141 | "fdt addr ${fdt_addr_r}; fdt resize; " \ |
| 142 | "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\ |
| 143 | "then "\ |
| 144 | " setenv ramdisk_param ${ramdisk_addr_r}; "\ |
| 145 | "else "\ |
| 146 | " setenv ramdisk_param -; "\ |
| 147 | "fi ; " \ |
| 148 | "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0" |
| 149 | #define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs " |
| 150 | |
| 151 | #define BOOT_TARGET_DEVICES(func) \ |
| 152 | func(USB, usb, 0) \ |
| 153 | func(SATA, sata, 0) \ |
| 154 | func(SATA, sata, 1) \ |
| 155 | func(PXE, pxe, na) \ |
| 156 | func(DHCP, dhcp, na) \ |
| 157 | func(AFS, afs, na) |
| 158 | |
| 159 | #include <config_distro_bootcmd.h> |
| 160 | |
Linus Walleij | c39566a | 2015-04-05 01:48:32 +0200 | [diff] [blame] | 161 | /* |
| 162 | * Defines where the kernel and FDT exist in NOR flash and where it will |
| 163 | * be copied into DRAM |
| 164 | */ |
| 165 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Ryan Harkin | 66fe7ee | 2015-10-09 17:18:07 +0100 | [diff] [blame] | 166 | "kernel_name=norkern\0" \ |
| 167 | "kernel_alt_name=Image\0" \ |
Andre Przywara | 11e56c4 | 2020-04-27 19:17:58 +0100 | [diff] [blame] | 168 | "kernel_addr_r=0x80080000\0" \ |
| 169 | "ramdisk_name=ramdisk.img\0" \ |
| 170 | "ramdisk_addr_r=0x88000000\0" \ |
Alexander Graf | af68480 | 2016-03-04 01:10:11 +0100 | [diff] [blame] | 171 | "fdtfile=board.dtb\0" \ |
Ryan Harkin | 66fe7ee | 2015-10-09 17:18:07 +0100 | [diff] [blame] | 172 | "fdt_alt_name=juno\0" \ |
Andre Przywara | 11e56c4 | 2020-04-27 19:17:58 +0100 | [diff] [blame] | 173 | "fdt_addr_r=0x80000000\0" \ |
Andre Przywara | be03531 | 2021-07-12 00:25:15 +0100 | [diff] [blame] | 174 | BOOTENV |
Linus Walleij | c39566a | 2015-04-05 01:48:32 +0200 | [diff] [blame] | 175 | |
| 176 | #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP |
Peter Hoyes | 16fff30 | 2021-11-11 09:26:01 +0000 | [diff] [blame] | 177 | |
| 178 | #define VEXPRESS_KERNEL_ADDR 0x80080000 |
| 179 | #define VEXPRESS_FDT_ADDR 0x8fc00000 |
| 180 | #define VEXPRESS_BOOT_ADDR 0x8fd00000 |
| 181 | #define VEXPRESS_RAMDISK_ADDR 0x8fe00000 |
| 182 | |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 183 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Linus Walleij | 4d30c9d | 2015-05-27 09:45:39 +0200 | [diff] [blame] | 184 | "kernel_name=Image\0" \ |
Peter Hoyes | 16fff30 | 2021-11-11 09:26:01 +0000 | [diff] [blame] | 185 | "kernel_addr_r=" __stringify(VEXPRESS_KERNEL_ADDR) "\0" \ |
| 186 | "ramdisk_name=ramdisk.img\0" \ |
| 187 | "ramdisk_addr_r=" __stringify(VEXPRESS_RAMDISK_ADDR) "\0" \ |
| 188 | "fdtfile=devtree.dtb\0" \ |
| 189 | "fdt_addr_r=" __stringify(VEXPRESS_FDT_ADDR) "\0" \ |
| 190 | "boot_name=boot.img\0" \ |
| 191 | "boot_addr_r=" __stringify(VEXPRESS_BOOT_ADDR) "\0" |
| 192 | |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 193 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 194 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 195 | /* Monitor Command Prompt */ |
| 196 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 197 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ |
| 198 | |
Ryan Harkin | ad5b2a2 | 2015-11-18 10:39:09 +0000 | [diff] [blame] | 199 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
| 200 | #define CONFIG_SYS_FLASH_BASE 0x08000000 |
| 201 | /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ |
| 202 | #define CONFIG_SYS_MAX_FLASH_SECT 259 |
| 203 | /* Store environment at top of flash in the same location as blank.img */ |
| 204 | /* in the Juno firmware. */ |
Linus Walleij | 6ba4b6a | 2015-02-19 17:19:37 +0100 | [diff] [blame] | 205 | #else |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 206 | #define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000) |
Ryan Harkin | ad5b2a2 | 2015-11-18 10:39:09 +0000 | [diff] [blame] | 207 | /* 256 x 256KiB sectors */ |
| 208 | #define CONFIG_SYS_MAX_FLASH_SECT 256 |
| 209 | /* Store environment at top of flash */ |
Ryan Harkin | ad5b2a2 | 2015-11-18 10:39:09 +0000 | [diff] [blame] | 210 | #endif |
| 211 | |
Ryan Harkin | b1a4a67 | 2015-05-08 18:07:52 +0100 | [diff] [blame] | 212 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT |
Ryan Harkin | ad5b2a2 | 2015-11-18 10:39:09 +0000 | [diff] [blame] | 213 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
Linus Walleij | 6ba4b6a | 2015-02-19 17:19:37 +0100 | [diff] [blame] | 214 | |
Andre Przywara | e3e8121 | 2020-04-27 19:18:03 +0100 | [diff] [blame] | 215 | #ifdef CONFIG_USB_EHCI_HCD |
| 216 | #define CONFIG_USB_OHCI_NEW |
| 217 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 |
| 218 | #endif |
| 219 | |
Linus Walleij | 6ba4b6a | 2015-02-19 17:19:37 +0100 | [diff] [blame] | 220 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ |
Ryan Harkin | ad5b2a2 | 2015-11-18 10:39:09 +0000 | [diff] [blame] | 221 | #define FLASH_MAX_SECTOR_SIZE 0x00040000 |
Linus Walleij | 6ba4b6a | 2015-02-19 17:19:37 +0100 | [diff] [blame] | 222 | |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 223 | #endif /* __VEXPRESS_AEMV8_H */ |