blob: 13515dd7ecf87977d829ed5251e78fa0ce524fce [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070040 pci0 = &pci0;
41 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070042 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020043 remoteproc0 = &rproc_1;
44 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060045 rtc0 = &rtc_0;
46 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060047 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020048 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070049 testbus3 = "/some-bus";
50 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070051 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070052 testfdt3 = "/b-test";
53 testfdt5 = "/some-bus/c-test@5";
54 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070055 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020056 fdt-dummy0 = "/translation-test@8000/dev@0,0";
57 fdt-dummy1 = "/translation-test@8000/dev@1,100";
58 fdt-dummy2 = "/translation-test@8000/dev@2,200";
59 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060060 usb0 = &usb_0;
61 usb1 = &usb_1;
62 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020063 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020064 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060065 };
66
Philippe Reynes462d1632022-03-28 22:56:53 +020067 binman {
68 };
69
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020070 config {
Simon Glass0034d962021-08-07 07:24:01 -060071 testing-bool;
72 testing-int = <123>;
73 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020074 environment {
75 from_fdt = "yes";
76 fdt_env_path = "";
77 };
78 };
79
Simon Glassb255efc2022-04-24 23:31:24 -060080 bootstd {
81 compatible = "u-boot,boot-std";
82
83 filename-prefixes = "/", "/boot/";
84 bootdev-order = "mmc2", "mmc1";
85
86 syslinux {
87 compatible = "u-boot,distro-syslinux";
88 };
89
90 efi {
91 compatible = "u-boot,distro-efi";
92 };
93 };
94
Nandor Han6521e5d2021-06-10 16:56:44 +030095 reboot-mode0 {
96 compatible = "reboot-mode-gpio";
97 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
98 u-boot,env-variable = "bootstatus";
99 mode-test = <0x01>;
100 mode-download = <0x03>;
101 };
102
Nandor Han7e4067a2021-06-10 16:56:45 +0300103 reboot_mode1: reboot-mode@14 {
104 compatible = "reboot-mode-rtc";
105 rtc = <&rtc_0>;
106 reg = <0x30 4>;
107 u-boot,env-variable = "bootstatus";
108 big-endian;
109 mode-test = <0x21969147>;
110 mode-download = <0x51939147>;
111 };
112
Simon Glassed96cde2018-12-10 10:37:33 -0700113 audio: audio-codec {
114 compatible = "sandbox,audio-codec";
115 #sound-dai-cells = <1>;
116 };
117
Philippe Reynes1ee26482020-07-24 18:19:51 +0200118 buttons {
119 compatible = "gpio-keys";
120
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200121 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200122 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200123 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200124 };
125
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200126 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200127 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200128 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200129 };
130 };
131
Marek Szyprowskiad398592021-02-18 11:33:18 +0100132 buttons2 {
133 compatible = "adc-keys";
134 io-channels = <&adc 3>;
135 keyup-threshold-microvolt = <3000000>;
136
137 button-up {
138 label = "button3";
139 linux,code = <KEY_F3>;
140 press-threshold-microvolt = <1500000>;
141 };
142
143 button-down {
144 label = "button4";
145 linux,code = <KEY_F4>;
146 press-threshold-microvolt = <1000000>;
147 };
148
149 button-enter {
150 label = "button5";
151 linux,code = <KEY_F5>;
152 press-threshold-microvolt = <500000>;
153 };
154 };
155
Simon Glassc953aaf2018-12-10 10:37:34 -0700156 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600157 reg = <0 0>;
158 compatible = "google,cros-ec-sandbox";
159
160 /*
161 * This describes the flash memory within the EC. Note
162 * that the STM32L flash erases to 0, not 0xff.
163 */
164 flash {
165 image-pos = <0x08000000>;
166 size = <0x20000>;
167 erase-value = <0>;
168
169 /* Information for sandbox */
170 ro {
171 image-pos = <0>;
172 size = <0xf000>;
173 };
174 wp-ro {
175 image-pos = <0xf000>;
176 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700177 used = <0x884>;
178 compress = "lz4";
179 uncomp-size = <0xcf8>;
180 hash {
181 algo = "sha256";
182 value = [00 01 02 03 04 05 06 07
183 08 09 0a 0b 0c 0d 0e 0f
184 10 11 12 13 14 15 16 17
185 18 19 1a 1b 1c 1d 1e 1f];
186 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600187 };
188 rw {
189 image-pos = <0x10000>;
190 size = <0x10000>;
191 };
192 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300193
194 cros_ec_pwm: cros-ec-pwm {
195 compatible = "google,cros-ec-pwm";
196 #pwm-cells = <1>;
197 };
198
Simon Glass699c9ca2018-10-01 12:22:08 -0600199 };
200
Yannick Fertré9712c822019-10-07 15:29:05 +0200201 dsi_host: dsi_host {
202 compatible = "sandbox,dsi-host";
203 };
204
Simon Glassb2c1cac2014-02-26 15:59:21 -0700205 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600206 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700207 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600208 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700209 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600210 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100211 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
212 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700213 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100214 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
215 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
216 <&gpio_b 7 GPIO_IN 3 2 1>,
217 <&gpio_b 8 GPIO_OUT 3 2 1>,
218 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100219 test3-gpios =
220 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
221 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
222 <&gpio_c 2 GPIO_OUT>,
223 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
224 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200225 <&gpio_c 5 GPIO_IN>,
226 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
227 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530228 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
229 test5-gpios = <&gpio_a 19>;
230
Simon Glass73025392021-10-23 17:26:04 -0600231 bool-value;
Simon Glass6df01f92018-12-10 10:37:37 -0700232 int-value = <1234>;
233 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200234 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200235 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600236 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700237 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600238 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200239 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530240
241 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
242 <&muxcontroller0 2>, <&muxcontroller0 3>,
243 <&muxcontroller1>;
244 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
245 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100246 display-timings {
247 timing0: 240x320 {
248 clock-frequency = <6500000>;
249 hactive = <240>;
250 vactive = <320>;
251 hfront-porch = <6>;
252 hback-porch = <7>;
253 hsync-len = <1>;
254 vback-porch = <5>;
255 vfront-porch = <8>;
256 vsync-len = <2>;
257 hsync-active = <1>;
258 vsync-active = <0>;
259 de-active = <1>;
260 pixelclk-active = <1>;
261 interlaced;
262 doublescan;
263 doubleclk;
264 };
265 timing1: 480x800 {
266 clock-frequency = <9000000>;
267 hactive = <480>;
268 vactive = <800>;
269 hfront-porch = <10>;
270 hback-porch = <59>;
271 hsync-len = <12>;
272 vback-porch = <15>;
273 vfront-porch = <17>;
274 vsync-len = <16>;
275 hsync-active = <0>;
276 vsync-active = <1>;
277 de-active = <0>;
278 pixelclk-active = <0>;
279 };
280 timing2: 800x480 {
281 clock-frequency = <33500000>;
282 hactive = <800>;
283 vactive = <480>;
284 hback-porch = <89>;
285 hfront-porch = <164>;
286 vback-porch = <23>;
287 vfront-porch = <10>;
288 hsync-len = <11>;
289 vsync-len = <13>;
290 };
291 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700292 };
293
294 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600295 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700296 compatible = "not,compatible";
297 };
298
299 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600300 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700301 };
302
Simon Glass5620cf82018-10-01 12:22:40 -0600303 backlight: backlight {
304 compatible = "pwm-backlight";
305 enable-gpios = <&gpio_a 1>;
306 power-supply = <&ldo_1>;
307 pwms = <&pwm 0 1000>;
308 default-brightness-level = <5>;
309 brightness-levels = <0 16 32 64 128 170 202 234 255>;
310 };
311
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200312 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200313 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200314 bind-test-child1 {
315 compatible = "sandbox,phy";
316 #phy-cells = <1>;
317 };
318
319 bind-test-child2 {
320 compatible = "simple-bus";
321 };
322 };
323
Simon Glassb2c1cac2014-02-26 15:59:21 -0700324 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600325 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700326 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600327 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700328 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530329
330 mux-controls = <&muxcontroller0 0>;
331 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700332 };
333
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200334 phy_provider0: gen_phy@0 {
335 compatible = "sandbox,phy";
336 #phy-cells = <1>;
337 };
338
339 phy_provider1: gen_phy@1 {
340 compatible = "sandbox,phy";
341 #phy-cells = <0>;
342 broken;
343 };
344
developer71092972020-05-02 11:35:12 +0200345 phy_provider2: gen_phy@2 {
346 compatible = "sandbox,phy";
347 #phy-cells = <0>;
348 };
349
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200350 gen_phy_user: gen_phy_user {
351 compatible = "simple-bus";
352 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
353 phy-names = "phy1", "phy2", "phy3";
354 };
355
developer71092972020-05-02 11:35:12 +0200356 gen_phy_user1: gen_phy_user1 {
357 compatible = "simple-bus";
358 phys = <&phy_provider0 0>, <&phy_provider2>;
359 phy-names = "phy1", "phy2";
360 };
361
Simon Glassb2c1cac2014-02-26 15:59:21 -0700362 some-bus {
363 #address-cells = <1>;
364 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600365 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600366 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600367 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700368 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600369 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700370 compatible = "denx,u-boot-fdt-test";
371 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600372 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700373 ping-add = <5>;
374 };
Simon Glass40717422014-07-23 06:55:18 -0600375 c-test@0 {
376 compatible = "denx,u-boot-fdt-test";
377 reg = <0>;
378 ping-expect = <6>;
379 ping-add = <6>;
380 };
381 c-test@1 {
382 compatible = "denx,u-boot-fdt-test";
383 reg = <1>;
384 ping-expect = <7>;
385 ping-add = <7>;
386 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700387 };
388
389 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600390 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600391 ping-expect = <6>;
392 ping-add = <6>;
393 compatible = "google,another-fdt-test";
394 };
395
396 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600397 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600398 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700399 ping-add = <6>;
400 compatible = "google,another-fdt-test";
401 };
402
Simon Glass0ccb0972015-01-25 08:27:05 -0700403 f-test {
404 compatible = "denx,u-boot-fdt-test";
405 };
406
407 g-test {
408 compatible = "denx,u-boot-fdt-test";
409 };
410
Bin Mengd9d24782018-10-10 22:07:01 -0700411 h-test {
412 compatible = "denx,u-boot-fdt-test1";
413 };
414
developercf8bc132020-05-02 11:35:10 +0200415 i-test {
416 compatible = "mediatek,u-boot-fdt-test";
417 #address-cells = <1>;
418 #size-cells = <0>;
419
420 subnode@0 {
421 reg = <0>;
422 };
423
424 subnode@1 {
425 reg = <1>;
426 };
427
428 subnode@2 {
429 reg = <2>;
430 };
431 };
432
Simon Glass204675c2019-12-29 21:19:25 -0700433 devres-test {
434 compatible = "denx,u-boot-devres-test";
435 };
436
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530437 another-test {
438 reg = <0 2>;
439 compatible = "denx,u-boot-fdt-test";
440 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
441 test5-gpios = <&gpio_a 19>;
442 };
443
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100444 mmio-bus@0 {
445 #address-cells = <1>;
446 #size-cells = <1>;
447 compatible = "denx,u-boot-test-bus";
448 dma-ranges = <0x10000000 0x00000000 0x00040000>;
449
450 subnode@0 {
451 compatible = "denx,u-boot-fdt-test";
452 };
453 };
454
455 mmio-bus@1 {
456 #address-cells = <1>;
457 #size-cells = <1>;
458 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100459
460 subnode@0 {
461 compatible = "denx,u-boot-fdt-test";
462 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100463 };
464
Simon Glass3c601b12020-07-07 13:12:06 -0600465 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600466 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600467 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600468 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600469 child {
470 compatible = "denx,u-boot-acpi-test";
471 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600472 };
473
Simon Glass3c601b12020-07-07 13:12:06 -0600474 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600475 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600476 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600477 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600478 };
479
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200480 clocks {
481 clk_fixed: clk-fixed {
482 compatible = "fixed-clock";
483 #clock-cells = <0>;
484 clock-frequency = <1234>;
485 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000486
487 clk_fixed_factor: clk-fixed-factor {
488 compatible = "fixed-factor-clock";
489 #clock-cells = <0>;
490 clock-div = <3>;
491 clock-mult = <2>;
492 clocks = <&clk_fixed>;
493 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200494
495 osc {
496 compatible = "fixed-clock";
497 #clock-cells = <0>;
498 clock-frequency = <20000000>;
499 };
Stephen Warrena9622432016-06-17 09:44:00 -0600500 };
501
502 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600503 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600504 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200505 assigned-clocks = <&clk_sandbox 3>;
506 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600507 };
508
509 clk-test {
510 compatible = "sandbox,clk-test";
511 clocks = <&clk_fixed>,
512 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200513 <&clk_sandbox 0>,
514 <&clk_sandbox 3>,
515 <&clk_sandbox 2>;
516 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600517 };
518
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200519 ccf: clk-ccf {
520 compatible = "sandbox,clk-ccf";
521 };
522
Simon Glass507ab962021-12-04 08:56:31 -0700523 efi-media {
524 compatible = "sandbox,efi-media";
525 };
526
Simon Glass5b968632015-05-22 15:42:15 -0600527 eth@10002000 {
528 compatible = "sandbox,eth";
529 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600530 };
531
532 eth_5: eth@10003000 {
533 compatible = "sandbox,eth";
534 reg = <0x10003000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400535 mac-address = [ 02 00 11 22 33 46 ];
Simon Glass5b968632015-05-22 15:42:15 -0600536 };
537
Bin Meng04a11cb2015-08-27 22:25:53 -0700538 eth_3: sbe5 {
539 compatible = "sandbox,eth";
540 reg = <0x10005000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400541 mac-address = [ 02 00 11 22 33 45 ];
Bin Meng04a11cb2015-08-27 22:25:53 -0700542 };
543
Simon Glass5b968632015-05-22 15:42:15 -0600544 eth@10004000 {
545 compatible = "sandbox,eth";
546 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600547 };
548
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200549 phy_eth0: phy-test-eth {
550 compatible = "sandbox,eth";
551 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400552 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200553 phy-handle = <&ethphy1>;
Marek BehĂșnbc194772022-04-07 00:33:01 +0200554 phy-mode = "2500base-x";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200555 };
556
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800557 dsa_eth0: dsa-test-eth {
558 compatible = "sandbox,eth";
559 reg = <0x10006000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400560 mac-address = [ 02 00 11 22 33 48 ];
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800561 };
562
563 dsa-test {
564 compatible = "sandbox,dsa";
565
566 ports {
567 #address-cells = <1>;
568 #size-cells = <0>;
569 swp_0: port@0 {
570 reg = <0>;
571 label = "lan0";
572 phy-mode = "rgmii-rxid";
573
574 fixed-link {
575 speed = <100>;
576 full-duplex;
577 };
578 };
579
580 swp_1: port@1 {
581 reg = <1>;
582 label = "lan1";
583 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800584 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800585 };
586
587 port@2 {
588 reg = <2>;
589 ethernet = <&dsa_eth0>;
590
591 fixed-link {
592 speed = <1000>;
593 full-duplex;
594 };
595 };
596 };
597 };
598
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700599 firmware {
600 sandbox_firmware: sandbox-firmware {
601 compatible = "sandbox,firmware";
602 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200603
Etienne Carriere09665cb2022-02-21 09:22:39 +0100604 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200605 compatible = "sandbox,scmi-agent";
606 #address-cells = <1>;
607 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200608
Etienne Carriere09665cb2022-02-21 09:22:39 +0100609 protocol@10 {
610 reg = <0x10>;
611 };
612
613 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200614 reg = <0x14>;
615 #clock-cells = <1>;
616 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200617
Etienne Carriere09665cb2022-02-21 09:22:39 +0100618 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200619 reg = <0x16>;
620 #reset-cells = <1>;
621 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100622
623 protocol@17 {
624 reg = <0x17>;
625
626 regulators {
627 #address-cells = <1>;
628 #size-cells = <0>;
629
Etienne Carriere09665cb2022-02-21 09:22:39 +0100630 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100631 reg = <0>;
632 regulator-name = "sandbox-voltd0";
633 regulator-min-microvolt = <1100000>;
634 regulator-max-microvolt = <3300000>;
635 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100636 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100637 reg = <0x1>;
638 regulator-name = "sandbox-voltd1";
639 regulator-min-microvolt = <1800000>;
640 };
641 };
642 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200643 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700644 };
645
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100646 pinctrl-gpio {
647 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700648
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100649 gpio_a: base-gpios {
650 compatible = "sandbox,gpio";
651 gpio-controller;
652 #gpio-cells = <1>;
653 gpio-bank-name = "a";
654 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200655 hog_input_active_low {
656 gpio-hog;
657 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200658 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200659 };
660 hog_input_active_high {
661 gpio-hog;
662 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200663 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200664 };
665 hog_output_low {
666 gpio-hog;
667 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200668 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200669 };
670 hog_output_high {
671 gpio-hog;
672 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200673 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200674 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100675 };
676
677 gpio_b: extra-gpios {
678 compatible = "sandbox,gpio";
679 gpio-controller;
680 #gpio-cells = <5>;
681 gpio-bank-name = "b";
682 sandbox,gpio-count = <10>;
683 };
Simon Glass25348a42014-10-13 23:42:11 -0600684
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100685 gpio_c: pinmux-gpios {
686 compatible = "sandbox,gpio";
687 gpio-controller;
688 #gpio-cells = <2>;
689 gpio-bank-name = "c";
690 sandbox,gpio-count = <10>;
691 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100692 };
693
Simon Glass7df766e2014-12-10 08:55:55 -0700694 i2c@0 {
695 #address-cells = <1>;
696 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600697 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700698 compatible = "sandbox,i2c";
699 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200700 pinctrl-names = "default";
701 pinctrl-0 = <&pinmux_i2c0_pins>;
702
Simon Glass7df766e2014-12-10 08:55:55 -0700703 eeprom@2c {
704 reg = <0x2c>;
705 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700706 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200707 partitions {
708 compatible = "fixed-partitions";
709 #address-cells = <1>;
710 #size-cells = <1>;
711 bootcount_i2c: bootcount@10 {
712 reg = <10 2>;
713 };
714 };
Simon Glass7df766e2014-12-10 08:55:55 -0700715 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200716
Simon Glass336b2952015-05-22 15:42:17 -0600717 rtc_0: rtc@43 {
718 reg = <0x43>;
719 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700720 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600721 };
722
723 rtc_1: rtc@61 {
724 reg = <0x61>;
725 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700726 sandbox,emul = <&emul1>;
727 };
728
729 i2c_emul: emul {
730 reg = <0xff>;
731 compatible = "sandbox,i2c-emul-parent";
732 emul_eeprom: emul-eeprom {
733 compatible = "sandbox,i2c-eeprom";
734 sandbox,filename = "i2c.bin";
735 sandbox,size = <256>;
736 };
737 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700738 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700739 };
740 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700741 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600742 };
743 };
744
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200745 sandbox_pmic: sandbox_pmic {
746 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700747 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200748 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200749
750 mc34708: pmic@41 {
751 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700752 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200753 };
Simon Glass7df766e2014-12-10 08:55:55 -0700754 };
755
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100756 bootcount@0 {
757 compatible = "u-boot,bootcount-rtc";
758 rtc = <&rtc_1>;
759 offset = <0x13>;
760 };
761
Michal Simek4f18f922020-05-28 11:48:55 +0200762 bootcount {
763 compatible = "u-boot,bootcount-i2c-eeprom";
764 i2c-eeprom = <&bootcount_i2c>;
765 };
766
Nandor Han88895812021-06-10 15:40:38 +0300767 bootcount_4@0 {
768 compatible = "u-boot,bootcount-syscon";
769 syscon = <&syscon0>;
770 reg = <0x0 0x04>, <0x0 0x04>;
771 reg-names = "syscon_reg", "offset";
772 };
773
774 bootcount_2@0 {
775 compatible = "u-boot,bootcount-syscon";
776 syscon = <&syscon0>;
777 reg = <0x0 0x04>, <0x0 0x02> ;
778 reg-names = "syscon_reg", "offset";
779 };
780
Marek Szyprowskiad398592021-02-18 11:33:18 +0100781 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100782 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100783 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100784 vdd-supply = <&buck2>;
785 vss-microvolts = <0>;
786 };
787
Mark Kettenis67748ee2021-10-23 16:58:02 +0200788 iommu: iommu@0 {
789 compatible = "sandbox,iommu";
790 #iommu-cells = <0>;
791 };
792
Simon Glass515dcff2020-02-06 09:55:00 -0700793 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700794 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700795 interrupt-controller;
796 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700797 };
798
Simon Glass90b6fef2016-01-18 19:52:26 -0700799 lcd {
800 u-boot,dm-pre-reloc;
801 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200802 pinctrl-names = "default";
803 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700804 xres = <1366>;
805 yres = <768>;
806 };
807
Simon Glassd783eb32015-07-06 12:54:34 -0600808 leds {
809 compatible = "gpio-leds";
810
811 iracibble {
812 gpios = <&gpio_a 1 0>;
813 label = "sandbox:red";
814 };
815
816 martinet {
817 gpios = <&gpio_a 2 0>;
818 label = "sandbox:green";
819 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200820
821 default_on {
822 gpios = <&gpio_a 5 0>;
823 label = "sandbox:default_on";
824 default-state = "on";
825 };
826
827 default_off {
828 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400829 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200830 default-state = "off";
831 };
Simon Glassd783eb32015-07-06 12:54:34 -0600832 };
833
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200834 gpio-wdt {
835 gpios = <&gpio_a 7 0>;
836 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200837 hw_margin_ms = <100>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200838 always-running;
839 };
840
Stephen Warren62f2c902016-05-16 17:41:37 -0600841 mbox: mbox {
842 compatible = "sandbox,mbox";
843 #mbox-cells = <1>;
844 };
845
846 mbox-test {
847 compatible = "sandbox,mbox-test";
848 mboxes = <&mbox 100>, <&mbox 1>;
849 mbox-names = "other", "test";
850 };
851
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900852 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200853 #address-cells = <1>;
854 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400855 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200856 cpu1: cpu@1 {
857 device_type = "cpu";
858 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400859 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900860 compatible = "sandbox,cpu_sandbox";
861 u-boot,dm-pre-reloc;
862 };
Mario Sixdea5df72018-08-06 10:23:44 +0200863
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200864 cpu2: cpu@2 {
865 device_type = "cpu";
866 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900867 compatible = "sandbox,cpu_sandbox";
868 u-boot,dm-pre-reloc;
869 };
Mario Sixdea5df72018-08-06 10:23:44 +0200870
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200871 cpu3: cpu@3 {
872 device_type = "cpu";
873 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900874 compatible = "sandbox,cpu_sandbox";
875 u-boot,dm-pre-reloc;
876 };
Mario Sixdea5df72018-08-06 10:23:44 +0200877 };
878
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500879 chipid: chipid {
880 compatible = "sandbox,soc";
881 };
882
Simon Glassc953aaf2018-12-10 10:37:34 -0700883 i2s: i2s {
884 compatible = "sandbox,i2s";
885 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700886 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700887 };
888
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200889 nop-test_0 {
890 compatible = "sandbox,nop_sandbox1";
891 nop-test_1 {
892 compatible = "sandbox,nop_sandbox2";
893 bind = "True";
894 };
895 nop-test_2 {
896 compatible = "sandbox,nop_sandbox2";
897 bind = "False";
898 };
899 };
900
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200901 misc-test {
902 compatible = "sandbox,misc_sandbox";
903 };
904
Simon Glasse4fef742017-04-23 20:02:07 -0600905 mmc2 {
906 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -0600907 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -0600908 };
909
Simon Glassb255efc2022-04-24 23:31:24 -0600910 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -0600911 mmc1 {
912 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -0600913 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -0600914 };
915
Simon Glassb255efc2022-04-24 23:31:24 -0600916 /* This is used for the fastboot tests */
Simon Glasse4fef742017-04-23 20:02:07 -0600917 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600918 compatible = "sandbox,mmc";
919 };
920
Simon Glass53a68b32019-02-16 20:24:50 -0700921 pch {
922 compatible = "sandbox,pch";
923 };
924
Tom Rini4a3ca482020-02-11 12:41:23 -0500925 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700926 compatible = "sandbox,pci";
927 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500928 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700929 #address-cells = <3>;
930 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600931 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700932 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700933 pci@0,0 {
934 compatible = "pci-generic";
935 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600936 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700937 };
Alex Margineanf1274432019-06-07 11:24:24 +0300938 pci@1,0 {
939 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600940 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
941 reg = <0x02000814 0 0 0 0
942 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600943 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300944 };
Simon Glass937bb472019-12-06 21:41:57 -0700945 p2sb-pci@2,0 {
946 compatible = "sandbox,p2sb";
947 reg = <0x02001010 0 0 0 0>;
948 sandbox,emul = <&p2sb_emul>;
949
950 adder {
951 intel,p2sb-port-id = <3>;
952 compatible = "sandbox,adder";
953 };
954 };
Simon Glass8c501022019-12-06 21:41:54 -0700955 pci@1e,0 {
956 compatible = "sandbox,pmc";
957 reg = <0xf000 0 0 0 0>;
958 sandbox,emul = <&pmc_emul1e>;
959 acpi-base = <0x400>;
960 gpe0-dwx-mask = <0xf>;
961 gpe0-dwx-shift-base = <4>;
962 gpe0-dw = <6 7 9>;
963 gpe0-sts = <0x20>;
964 gpe0-en = <0x30>;
965 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700966 pci@1f,0 {
967 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600968 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
969 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600970 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700971 };
972 };
973
Simon Glassb98ba4c2019-09-25 08:56:10 -0600974 pci-emul0 {
975 compatible = "sandbox,pci-emul-parent";
976 swap_case_emul0_0: emul0@0,0 {
977 compatible = "sandbox,swap-case";
978 };
979 swap_case_emul0_1: emul0@1,0 {
980 compatible = "sandbox,swap-case";
981 use-ea;
982 };
983 swap_case_emul0_1f: emul0@1f,0 {
984 compatible = "sandbox,swap-case";
985 };
Simon Glass937bb472019-12-06 21:41:57 -0700986 p2sb_emul: emul@2,0 {
987 compatible = "sandbox,p2sb-emul";
988 };
Simon Glass8c501022019-12-06 21:41:54 -0700989 pmc_emul1e: emul@1e,0 {
990 compatible = "sandbox,pmc-emul";
991 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600992 };
993
Tom Rini4a3ca482020-02-11 12:41:23 -0500994 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700995 compatible = "sandbox,pci";
996 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500997 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700998 #address-cells = <3>;
999 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001000 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001001 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001002 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001003 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001004 0x0c 0x00 0x1234 0x5678
1005 0x10 0x00 0x1234 0x5678>;
1006 pci@10,0 {
1007 reg = <0x8000 0 0 0 0>;
1008 };
Bin Meng408e5902018-08-03 01:14:41 -07001009 };
1010
Tom Rini4a3ca482020-02-11 12:41:23 -05001011 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001012 compatible = "sandbox,pci";
1013 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001014 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001015 #address-cells = <3>;
1016 #size-cells = <2>;
1017 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1018 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1019 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1020 pci@1f,0 {
1021 compatible = "pci-generic";
1022 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001023 sandbox,emul = <&swap_case_emul2_1f>;
1024 };
1025 };
1026
1027 pci-emul2 {
1028 compatible = "sandbox,pci-emul-parent";
1029 swap_case_emul2_1f: emul2@1f,0 {
1030 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001031 };
1032 };
1033
Ramon Friedc64f19b2019-04-27 11:15:23 +03001034 pci_ep: pci_ep {
1035 compatible = "sandbox,pci_ep";
1036 };
1037
Simon Glass9c433fe2017-04-23 20:10:44 -06001038 probing {
1039 compatible = "simple-bus";
1040 test1 {
1041 compatible = "denx,u-boot-probe-test";
1042 };
1043
1044 test2 {
1045 compatible = "denx,u-boot-probe-test";
1046 };
1047
1048 test3 {
1049 compatible = "denx,u-boot-probe-test";
1050 };
1051
1052 test4 {
1053 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001054 first-syscon = <&syscon0>;
1055 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001056 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001057 };
1058 };
1059
Stephen Warren92c67fa2016-07-13 13:45:31 -06001060 pwrdom: power-domain {
1061 compatible = "sandbox,power-domain";
1062 #power-domain-cells = <1>;
1063 };
1064
1065 power-domain-test {
1066 compatible = "sandbox,power-domain-test";
1067 power-domains = <&pwrdom 2>;
1068 };
1069
Simon Glass5620cf82018-10-01 12:22:40 -06001070 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001071 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001072 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001073 pinctrl-names = "default";
1074 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001075 };
1076
1077 pwm2 {
1078 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001079 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001080 };
1081
Simon Glass3d355e62015-07-06 12:54:31 -06001082 ram {
1083 compatible = "sandbox,ram";
1084 };
1085
Simon Glassd860f222015-07-06 12:54:29 -06001086 reset@0 {
1087 compatible = "sandbox,warm-reset";
1088 };
1089
1090 reset@1 {
1091 compatible = "sandbox,reset";
1092 };
1093
Stephen Warren6488e642016-06-17 09:43:59 -06001094 resetc: reset-ctl {
1095 compatible = "sandbox,reset-ctl";
1096 #reset-cells = <1>;
1097 };
1098
1099 reset-ctl-test {
1100 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001101 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1102 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001103 };
1104
Sughosh Ganu23e37512019-12-28 23:58:31 +05301105 rng {
1106 compatible = "sandbox,sandbox-rng";
1107 };
1108
Nishanth Menonedf85812015-09-17 15:42:41 -05001109 rproc_1: rproc@1 {
1110 compatible = "sandbox,test-processor";
1111 remoteproc-name = "remoteproc-test-dev1";
1112 };
1113
1114 rproc_2: rproc@2 {
1115 compatible = "sandbox,test-processor";
1116 internal-memory-mapped;
1117 remoteproc-name = "remoteproc-test-dev2";
1118 };
1119
Simon Glass5620cf82018-10-01 12:22:40 -06001120 panel {
1121 compatible = "simple-panel";
1122 backlight = <&backlight 0 100>;
1123 };
1124
Ramon Fried26ed32e2018-07-02 02:57:59 +03001125 smem@0 {
1126 compatible = "sandbox,smem";
1127 };
1128
Simon Glass76072ac2018-12-10 10:37:36 -07001129 sound {
1130 compatible = "sandbox,sound";
1131 cpu {
1132 sound-dai = <&i2s 0>;
1133 };
1134
1135 codec {
1136 sound-dai = <&audio 0>;
1137 };
1138 };
1139
Simon Glass25348a42014-10-13 23:42:11 -06001140 spi@0 {
1141 #address-cells = <1>;
1142 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001143 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001144 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001145 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001146 pinctrl-names = "default";
1147 pinctrl-0 = <&pinmux_spi0_pins>;
1148
Simon Glass25348a42014-10-13 23:42:11 -06001149 spi.bin@0 {
1150 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001151 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001152 spi-max-frequency = <40000000>;
1153 sandbox,filename = "spi.bin";
1154 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001155 spi.bin@1 {
1156 reg = <1>;
1157 compatible = "spansion,m25p16", "jedec,spi-nor";
1158 spi-max-frequency = <50000000>;
1159 sandbox,filename = "spi.bin";
1160 spi-cpol;
1161 spi-cpha;
1162 };
Simon Glass25348a42014-10-13 23:42:11 -06001163 };
1164
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001165 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001166 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001167 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001168 };
1169
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001170 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001171 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001172 reg = <0x20 5
1173 0x28 6
1174 0x30 7
1175 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001176 };
1177
Patrick Delaunayee010432019-03-07 09:57:13 +01001178 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001179 compatible = "simple-mfd", "syscon";
1180 reg = <0x40 5
1181 0x48 6
1182 0x50 7
1183 0x58 8>;
1184 };
1185
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301186 syscon3: syscon@3 {
1187 compatible = "simple-mfd", "syscon";
1188 reg = <0x000100 0x10>;
1189
1190 muxcontroller0: a-mux-controller {
1191 compatible = "mmio-mux";
1192 #mux-control-cells = <1>;
1193
1194 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1195 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1196 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1197 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1198 u-boot,mux-autoprobe;
1199 };
1200 };
1201
1202 muxcontroller1: emul-mux-controller {
1203 compatible = "mux-emul";
1204 #mux-control-cells = <0>;
1205 u-boot,mux-autoprobe;
1206 idle-state = <0xabcd>;
1207 };
1208
Simon Glass791a17f2020-12-16 21:20:27 -07001209 testfdtm0 {
1210 compatible = "denx,u-boot-fdtm-test";
1211 };
1212
1213 testfdtm1: testfdtm1 {
1214 compatible = "denx,u-boot-fdtm-test";
1215 };
1216
1217 testfdtm2 {
1218 compatible = "denx,u-boot-fdtm-test";
1219 };
1220
Sean Anderson79d3bba2020-09-28 10:52:23 -04001221 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001222 compatible = "sandbox,timer";
1223 clock-frequency = <1000000>;
1224 };
1225
Sean Anderson79d3bba2020-09-28 10:52:23 -04001226 timer@1 {
1227 compatible = "sandbox,timer";
1228 sandbox,timebase-frequency-fallback;
1229 };
1230
Miquel Raynal80938c12018-05-15 11:57:27 +02001231 tpm2 {
1232 compatible = "sandbox,tpm2";
1233 };
1234
Simon Glass5b968632015-05-22 15:42:15 -06001235 uart0: serial {
1236 compatible = "sandbox,serial";
1237 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001238 pinctrl-names = "default";
1239 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001240 };
1241
Simon Glass31680482015-03-25 12:23:05 -06001242 usb_0: usb@0 {
1243 compatible = "sandbox,usb";
1244 status = "disabled";
1245 hub {
1246 compatible = "sandbox,usb-hub";
1247 #address-cells = <1>;
1248 #size-cells = <0>;
1249 flash-stick {
1250 reg = <0>;
1251 compatible = "sandbox,usb-flash";
1252 };
1253 };
1254 };
1255
1256 usb_1: usb@1 {
1257 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001258 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001259 hub {
1260 compatible = "usb-hub";
1261 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001262 #address-cells = <1>;
1263 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001264 hub-emul {
1265 compatible = "sandbox,usb-hub";
1266 #address-cells = <1>;
1267 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001268 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001269 reg = <0>;
1270 compatible = "sandbox,usb-flash";
1271 sandbox,filepath = "testflash.bin";
1272 };
1273
Simon Glass4700fe52015-11-08 23:48:01 -07001274 flash-stick@1 {
1275 reg = <1>;
1276 compatible = "sandbox,usb-flash";
1277 sandbox,filepath = "testflash1.bin";
1278 };
1279
1280 flash-stick@2 {
1281 reg = <2>;
1282 compatible = "sandbox,usb-flash";
1283 sandbox,filepath = "testflash2.bin";
1284 };
1285
Simon Glassc0ccc722015-11-08 23:48:08 -07001286 keyb@3 {
1287 reg = <3>;
1288 compatible = "sandbox,usb-keyb";
1289 };
1290
Simon Glass31680482015-03-25 12:23:05 -06001291 };
Michael Walle7c961322020-06-02 01:47:07 +02001292
1293 usbstor@1 {
1294 reg = <1>;
1295 };
1296 usbstor@3 {
1297 reg = <3>;
1298 };
Simon Glass31680482015-03-25 12:23:05 -06001299 };
1300 };
1301
1302 usb_2: usb@2 {
1303 compatible = "sandbox,usb";
1304 status = "disabled";
1305 };
1306
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001307 spmi: spmi@0 {
1308 compatible = "sandbox,spmi";
1309 #address-cells = <0x1>;
1310 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001311 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001312 pm8916@0 {
1313 compatible = "qcom,spmi-pmic";
1314 reg = <0x0 0x1>;
1315 #address-cells = <0x1>;
1316 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001317 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001318
1319 spmi_gpios: gpios@c000 {
1320 compatible = "qcom,pm8916-gpio";
1321 reg = <0xc000 0x400>;
1322 gpio-controller;
1323 gpio-count = <4>;
1324 #gpio-cells = <2>;
1325 gpio-bank-name="spmi";
1326 };
1327 };
1328 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001329
1330 wdt0: wdt@0 {
1331 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001332 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001333 };
Rob Clarka471b672018-01-10 11:33:30 +01001334
Mario Six95922152018-08-09 14:51:19 +02001335 axi: axi@0 {
1336 compatible = "sandbox,axi";
1337 #address-cells = <0x1>;
1338 #size-cells = <0x1>;
1339 store@0 {
1340 compatible = "sandbox,sandbox_store";
1341 reg = <0x0 0x400>;
1342 };
1343 };
1344
Rob Clarka471b672018-01-10 11:33:30 +01001345 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001346 #address-cells = <1>;
1347 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001348 setting = "sunrise ohoka";
1349 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001350 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001351 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001352 chosen-test {
1353 compatible = "denx,u-boot-fdt-test";
1354 reg = <9 1>;
1355 };
1356 };
Mario Six35616ef2018-03-12 14:53:33 +01001357
1358 translation-test@8000 {
1359 compatible = "simple-bus";
1360 reg = <0x8000 0x4000>;
1361
1362 #address-cells = <0x2>;
1363 #size-cells = <0x1>;
1364
1365 ranges = <0 0x0 0x8000 0x1000
1366 1 0x100 0x9000 0x1000
1367 2 0x200 0xA000 0x1000
1368 3 0x300 0xB000 0x1000
1369 >;
1370
Fabien Dessenne22236e02019-05-31 15:11:30 +02001371 dma-ranges = <0 0x000 0x10000000 0x1000
1372 1 0x100 0x20000000 0x1000
1373 >;
1374
Mario Six35616ef2018-03-12 14:53:33 +01001375 dev@0,0 {
1376 compatible = "denx,u-boot-fdt-dummy";
1377 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojasa3181152018-12-03 19:37:09 +01001378 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001379 };
1380
1381 dev@1,100 {
1382 compatible = "denx,u-boot-fdt-dummy";
1383 reg = <1 0x100 0x1000>;
1384
1385 };
1386
1387 dev@2,200 {
1388 compatible = "denx,u-boot-fdt-dummy";
1389 reg = <2 0x200 0x1000>;
1390 };
1391
1392
1393 noxlatebus@3,300 {
1394 compatible = "simple-bus";
1395 reg = <3 0x300 0x1000>;
1396
1397 #address-cells = <0x1>;
1398 #size-cells = <0x0>;
1399
1400 dev@42 {
1401 compatible = "denx,u-boot-fdt-dummy";
1402 reg = <0x42>;
1403 };
1404 };
1405 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001406
1407 osd {
1408 compatible = "sandbox,sandbox_osd";
1409 };
Tom Rinib93eea72018-09-30 18:16:51 -04001410
Jens Wiklander86afaa62018-09-25 16:40:16 +02001411 sandbox_tee {
1412 compatible = "sandbox,tee";
1413 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001414
1415 sandbox_virtio1 {
1416 compatible = "sandbox,virtio1";
1417 };
1418
1419 sandbox_virtio2 {
1420 compatible = "sandbox,virtio2";
1421 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001422
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001423 sandbox_scmi {
1424 compatible = "sandbox,scmi-devices";
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001425 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001426 resets = <&reset_scmi 3>;
1427 regul0-supply = <&regul0_scmi>;
1428 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001429 };
1430
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001431 pinctrl {
1432 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001433
Sean Anderson3438e3b2020-09-14 11:01:57 -04001434 pinctrl-names = "default", "alternate";
1435 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1436 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001437
Sean Anderson3438e3b2020-09-14 11:01:57 -04001438 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001439 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001440 pins = "P5";
1441 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001442 bias-pull-up;
1443 input-disable;
1444 };
1445 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001446 pins = "P6";
1447 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001448 output-high;
1449 drive-open-drain;
1450 };
1451 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001452 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001453 bias-pull-down;
1454 input-enable;
1455 };
1456 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001457 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001458 bias-disable;
1459 };
1460 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001461
1462 pinctrl_i2c: i2c {
1463 groups {
1464 groups = "I2C_UART";
1465 function = "I2C";
1466 };
1467
1468 pins {
1469 pins = "P0", "P1";
1470 drive-open-drain;
1471 };
1472 };
1473
1474 pinctrl_i2s: i2s {
1475 groups = "SPI_I2S";
1476 function = "I2S";
1477 };
1478
1479 pinctrl_spi: spi {
1480 groups = "SPI_I2S";
1481 function = "SPI";
1482
1483 cs {
1484 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1485 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1486 };
1487 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001488 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001489
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001490 pinctrl-single-no-width {
1491 compatible = "pinctrl-single";
1492 reg = <0x0000 0x238>;
1493 #pinctrl-cells = <1>;
1494 pinctrl-single,function-mask = <0x7f>;
1495 };
1496
1497 pinctrl-single-pins {
1498 compatible = "pinctrl-single";
1499 reg = <0x0000 0x238>;
1500 #pinctrl-cells = <1>;
1501 pinctrl-single,register-width = <32>;
1502 pinctrl-single,function-mask = <0x7f>;
1503
1504 pinmux_pwm_pins: pinmux_pwm_pins {
1505 pinctrl-single,pins = < 0x48 0x06 >;
1506 };
1507
1508 pinmux_spi0_pins: pinmux_spi0_pins {
1509 pinctrl-single,pins = <
1510 0x190 0x0c
1511 0x194 0x0c
1512 0x198 0x23
1513 0x19c 0x0c
1514 >;
1515 };
1516
1517 pinmux_uart0_pins: pinmux_uart0_pins {
1518 pinctrl-single,pins = <
1519 0x70 0x30
1520 0x74 0x00
1521 >;
1522 };
1523 };
1524
1525 pinctrl-single-bits {
1526 compatible = "pinctrl-single";
1527 reg = <0x0000 0x50>;
1528 #pinctrl-cells = <2>;
1529 pinctrl-single,bit-per-mux;
1530 pinctrl-single,register-width = <32>;
1531 pinctrl-single,function-mask = <0xf>;
1532
1533 pinmux_i2c0_pins: pinmux_i2c0_pins {
1534 pinctrl-single,bits = <
1535 0x10 0x00002200 0x0000ff00
1536 >;
1537 };
1538
1539 pinmux_lcd_pins: pinmux_lcd_pins {
1540 pinctrl-single,bits = <
1541 0x40 0x22222200 0xffffff00
1542 0x44 0x22222222 0xffffffff
1543 0x48 0x00000022 0x000000ff
1544 0x48 0x02000000 0x0f000000
1545 0x4c 0x02000022 0x0f0000ff
1546 >;
1547 };
1548 };
1549
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001550 hwspinlock@0 {
1551 compatible = "sandbox,hwspinlock";
1552 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001553
1554 dma: dma {
1555 compatible = "sandbox,dma";
1556 #dma-cells = <1>;
1557
1558 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1559 dma-names = "m2m", "tx0", "rx0";
1560 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001561
Alex Marginean0649be52019-07-12 10:13:53 +03001562 /*
1563 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1564 * end of the test. If parent mdio is removed first, clean-up of the
1565 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1566 * active at the end of the test. That it turn doesn't allow the mdio
1567 * class to be destroyed, triggering an error.
1568 */
1569 mdio-mux-test {
1570 compatible = "sandbox,mdio-mux";
1571 #address-cells = <1>;
1572 #size-cells = <0>;
1573 mdio-parent-bus = <&mdio>;
1574
1575 mdio-ch-test@0 {
1576 reg = <0>;
1577 };
1578 mdio-ch-test@1 {
1579 reg = <1>;
1580 };
1581 };
1582
1583 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001584 compatible = "sandbox,mdio";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +02001585 #address-cells = <1>;
1586 #size-cells = <0>;
1587
1588 ethphy1: ethernet-phy@1 {
1589 reg = <1>;
1590 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001591 };
Sean Andersonb7860542020-06-24 06:41:12 -04001592
1593 pm-bus-test {
1594 compatible = "simple-pm-bus";
1595 clocks = <&clk_sandbox 4>;
1596 power-domains = <&pwrdom 1>;
1597 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001598
1599 resetc2: syscon-reset {
1600 compatible = "syscon-reset";
1601 #reset-cells = <1>;
1602 regmap = <&syscon0>;
1603 offset = <1>;
1604 mask = <0x27FFFFFF>;
1605 assert-high = <0>;
1606 };
1607
1608 syscon-reset-test {
1609 compatible = "sandbox,misc_sandbox";
1610 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1611 reset-names = "valid", "no_mask", "out_of_range";
1612 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301613
Simon Glass458b66a2020-11-05 06:32:05 -07001614 sysinfo {
1615 compatible = "sandbox,sysinfo-sandbox";
1616 };
1617
Sean Anderson1c830672021-04-20 10:50:58 -04001618 sysinfo-gpio {
1619 compatible = "gpio-sysinfo";
1620 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1621 revisions = <19>, <5>;
1622 names = "rev_a", "foo";
1623 };
1624
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301625 some_regmapped-bus {
1626 #address-cells = <0x1>;
1627 #size-cells = <0x1>;
1628
1629 ranges = <0x0 0x0 0x10>;
1630 compatible = "simple-bus";
1631
1632 regmap-test_0 {
1633 reg = <0 0x10>;
1634 compatible = "sandbox,regmap_test";
1635 };
1636 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001637};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001638
1639#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001640#include "cros-ec-keyboard.dtsi"