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git01.mediatek.com / filogic / uboot / df41fc634d9e2e7899dc1023a7390708e6d8b886 / . / arch / m68k / cpu / mcf5445x / start.S
blob: f0264671d386f63cc04c2f4a139bf0dff87f00ba [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]2/*
3 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
4 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
5 *
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]6 * Copyright 2010-2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]8 */
9
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]10#include <asm-offsets.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]11#include <config.h>
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]12#include <asm/cache.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]13
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]14#define _START _start
15#define _FAULT _fault
16
17#define SAVE_ALL \
18 move.w #0x2700,%sr; /* disable intrs */ \
19 subl #60,%sp; /* space for 15 regs */ \
20 moveml %d0-%d7/%a0-%a6,%sp@;
21
22#define RESTORE_ALL \
23 moveml %sp@,%d0-%d7/%a0-%a6; \
24 addl #60,%sp; /* space for 15 regs */ \
25 rte;
26
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]27#if defined(CONFIG_SERIAL_BOOT)
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]28#define ASM_DRAMINIT (asm_dram_init - CONFIG_TEXT_BASE + \
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]29 CFG_SYS_INIT_RAM_ADDR)
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]30#define ASM_DRAMINIT_N (asm_dram_init - CONFIG_TEXT_BASE)
31#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_TEXT_BASE + \
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]32 CFG_SYS_INIT_RAM_ADDR)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]33#endif
34
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]35.text
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]36
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]37/*
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]38 * Vector table. This is used for initial platform startup.
39 * These vectors are to catch any un-intended traps.
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]40 */
41_vectors:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]42#if defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]43
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]44INITSP: .long 0 /* Initial SP */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]45#ifdef CONFIG_CF_SBF
Wolfgang Denk62fb2b42021-09-27 17:42:39 +0200[diff] [blame]46INITPC: .long ASM_DRAMINIT /* Initial PC */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]47#endif
48#ifdef CONFIG_SYS_NAND_BOOT
Wolfgang Denk62fb2b42021-09-27 17:42:39 +0200[diff] [blame]49INITPC: .long ASM_DRAMINIT_N /* Initial PC */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]50#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]51
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]52#else
53
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]54INITSP: .long 0 /* Initial SP */
Wolfgang Denk62fb2b42021-09-27 17:42:39 +0200[diff] [blame]55INITPC: .long _START /* Initial PC */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]56
57#endif
58
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]59vector02_0F:
60.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
61.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]62
63/* Reserved */
64vector10_17:
65.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
66
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]67vector18_1F:
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]69
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]70#if !defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]71
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]72/* TRAP #0 - #15 */
73vector20_2F:
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76
77/* Reserved */
78vector30_3F:
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81
82vector64_127:
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91
92vector128_191:
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101
102vector192_255:
103.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
104.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
105.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
106.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
109.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
110.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]111#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]112
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]113#if defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]114 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
115asm_sbf_img_hdr:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]116 .long 0x00000000 /* checksum, not yet implemented */
117 .long 0x00040000 /* image length */
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]118 .long CONFIG_TEXT_BASE /* image to be relocated at */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]119
120asm_dram_init:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]121 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]122
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]123#ifdef CONFIG_SYS_NAND_BOOT
124 /* for assembly stack */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]125 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]126 movec %d0, %RAMBAR1
127
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]128 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]129 clr.l %sp@-
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]130#endif
131
132#ifdef CONFIG_CF_SBF
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]133 move.l #CFG_SYS_INIT_RAM_ADDR, %d0
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]134 movec %d0, %VBR
135
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]136 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]137 movec %d0, %RAMBAR1
138
139 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]140 move.l #0, %d0
141 move.l #(ICACHE_STATUS), %a1 /* icache */
142 move.l #(DCACHE_STATUS), %a2 /* dcache */
143 move.l %d0, (%a1)
144 move.l %d0, (%a2)
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]145
146 /* invalidate and disable cache */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]147 move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]148 movec %d0, %CACR /* Invalidate cache */
149 move.l #0, %d0
150 movec %d0, %ACR0
151 movec %d0, %ACR1
152 movec %d0, %ACR2
153 movec %d0, %ACR3
154
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]155 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]156 clr.l %sp@-
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]157
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]158#ifdef CFG_SYS_CS0_BASE
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]159 /* Must disable global address */
160 move.l #0xFC008000, %a1
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]161 move.l #(CFG_SYS_CS0_BASE), (%a1)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]162 move.l #0xFC008008, %a1
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]163 move.l #(CFG_SYS_CS0_CTRL), (%a1)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]164 move.l #0xFC008004, %a1
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]165 move.l #(CFG_SYS_CS0_MASK), (%a1)
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]166#endif
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]167#endif /* CONFIG_CF_SBF */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]168
169#ifdef CONFIG_MCF5441x
170 /* TC: enable all peripherals,
171 in the future only enable certain peripherals */
172 move.l #0xFC04002D, %a1
173
174#if defined(CONFIG_CF_SBF)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]175 move.b #23, (%a1) /* dspi */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]176#endif
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]177#endif /* CONFIG_MCF5441x */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]178
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]179 /* mandatory board level ddr-sdram init,
180 * for both 5441x and 5445x
181 */
182 bsr sbf_dram_init
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]183
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]184#ifdef CONFIG_CF_SBF
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]185 /*
186 * DSPI Initialization
187 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
188 * a1 - dspi status
189 * a2 - dtfr
190 * a3 - drfr
191 * a4 - Dst addr
192 */
193 /* Enable pins for DSPI mode - chip-selects are enabled later */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]194asm_dspi_init:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]195#ifdef CONFIG_MCF5441x
196 move.l #0xEC09404E, %a1
197 move.l #0xEC09404F, %a2
198 move.b #0xFF, (%a1)
199 move.b #0x80, (%a2)
200#endif
201
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]202 /* Configure DSPI module */
203 move.l #0xFC05C000, %a0
204 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
205
206 move.l #0xFC05C00C, %a0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]207#ifdef CONFIG_MCF5441x
208 move.l #0x3E000016, (%a0)
209#endif
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]210
211 move.l #0xFC05C034, %a2 /* dtfr */
212 move.l #0xFC05C03B, %a3 /* drfr */
213
214 move.l #(ASM_SBF_IMG_HDR + 4), %a1
215 move.l (%a1)+, %d5
216 move.l (%a1), %a4
217
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]218 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_SBFHDR_DATA_OFFSET), %a0
219 move.l #(CFG_SYS_SBFHDR_SIZE), %d4
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]220
221 move.l #0xFC05C02C, %a1 /* dspi status */
222
223 /* Issue commands and address */
224 move.l #0x8002000B, %d2 /* Fast Read Cmd */
225 jsr asm_dspi_wr_status
226 jsr asm_dspi_rd_status
227
228 move.l #0x80020000, %d2 /* Address byte 2 */
229 jsr asm_dspi_wr_status
230 jsr asm_dspi_rd_status
231
232 move.l #0x80020000, %d2 /* Address byte 1 */
233 jsr asm_dspi_wr_status
234 jsr asm_dspi_rd_status
235
236 move.l #0x80020000, %d2 /* Address byte 0 */
237 jsr asm_dspi_wr_status
238 jsr asm_dspi_rd_status
239
240 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
241 jsr asm_dspi_wr_status
242 jsr asm_dspi_rd_status
243
244 /* Transfer serial boot header to sram */
245asm_dspi_rd_loop1:
246 move.l #0x80020000, %d2
247 jsr asm_dspi_wr_status
248 jsr asm_dspi_rd_status
249
250 move.b %d1, (%a0) /* read, copy to dst */
251
252 add.l #1, %a0 /* inc dst by 1 */
253 sub.l #1, %d4 /* dec cnt by 1 */
254 bne asm_dspi_rd_loop1
255
256 /* Transfer u-boot from serial flash to memory */
257asm_dspi_rd_loop2:
258 move.l #0x80020000, %d2
259 jsr asm_dspi_wr_status
260 jsr asm_dspi_rd_status
261
262 move.b %d1, (%a4) /* read, copy to dst */
263
264 add.l #1, %a4 /* inc dst by 1 */
265 sub.l #1, %d5 /* dec cnt by 1 */
266 bne asm_dspi_rd_loop2
267
268 move.l #0x00020000, %d2 /* Terminate */
269 jsr asm_dspi_wr_status
270 jsr asm_dspi_rd_status
271
272 /* jump to memory and execute */
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]273 move.l #(CONFIG_TEXT_BASE + 0x400), %a0
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]274 jmp (%a0)
275
276asm_dspi_wr_status:
277 move.l (%a1), %d0 /* status */
278 and.l #0x0000F000, %d0
279 cmp.l #0x00003000, %d0
280 bgt asm_dspi_wr_status
281
282 move.l %d2, (%a2)
283 rts
284
285asm_dspi_rd_status:
286 move.l (%a1), %d0 /* status */
287 and.l #0x000000F0, %d0
288 lsr.l #4, %d0
289 cmp.l #0, %d0
290 beq asm_dspi_rd_status
291
292 move.b (%a3), %d1
293 rts
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]294#endif /* CONFIG_CF_SBF */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]295
296#ifdef CONFIG_SYS_NAND_BOOT
297 /* copy 4 boot pages to dram as soon as possible */
298 /* each page is 996 bytes (1056 total with 60 ECC bytes */
299 move.l #0x00000000, %a1 /* src */
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]300 move.l #CONFIG_TEXT_BASE, %a2 /* dst */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]301 move.l #0x3E0, %d0 /* sz in long */
302
303asm_boot_nand_copy:
304 move.l (%a1)+, (%a2)+
305 subq.l #1, %d0
306 bne asm_boot_nand_copy
307
308 /* jump to memory and execute */
309 move.l #(asm_nand_init), %a0
310 jmp (%a0)
311
312asm_nand_init:
313 /* exit nand boot-mode */
314 move.l #0xFC0FFF30, %a1
315 or.l #0x00000040, %d1
316 move.l %d1, (%a1)
317
318 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]319 move.l #0, %d0
320 move.l #(CACR_STATUS), %a1 /* CACR */
321 move.l #(ICACHE_STATUS), %a2 /* icache */
322 move.l #(DCACHE_STATUS), %a3 /* dcache */
323 move.l %d0, (%a1)
324 move.l %d0, (%a2)
325 move.l %d0, (%a3)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]326
327 /* invalidate and disable cache */
328 move.l #0x01004100, %d0 /* Invalidate cache cmd */
329 movec %d0, %CACR /* Invalidate cache */
330 move.l #0, %d0
331 movec %d0, %ACR0
332 movec %d0, %ACR1
333 movec %d0, %ACR2
334 movec %d0, %ACR3
335
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]336#ifdef CFG_SYS_CS0_BASE
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]337 /* Must disable global address */
338 move.l #0xFC008000, %a1
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]339 move.l #(CFG_SYS_CS0_BASE), (%a1)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]340 move.l #0xFC008008, %a1
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]341 move.l #(CFG_SYS_CS0_CTRL), (%a1)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]342 move.l #0xFC008004, %a1
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]343 move.l #(CFG_SYS_CS0_MASK), (%a1)
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]344#endif
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]345
346 /* NAND port configuration */
347 move.l #0xEC094048, %a1
348 move.b #0xFD, (%a1)+
349 move.b #0x5F, (%a1)+
350 move.b #0x04, (%a1)+
351
352 /* reset nand */
353 move.l #0xFC0FFF38, %a1 /* isr */
354 move.l #0x000e0000, (%a1)
355 move.l #0xFC0FFF08, %a2
356 move.l #0x00000000, (%a2)+ /* car */
357 move.l #0x11000000, (%a2)+ /* rar */
358 move.l #0x00000000, (%a2)+ /* rpt */
359 move.l #0x00000000, (%a2)+ /* rai */
360 move.l #0xFC0FFF2c, %a2 /* cfg */
361 move.l #0x00000000, (%a2)+ /* secsz */
362 move.l #0x000e0681, (%a2)+
363 move.l #0xFC0FFF04, %a2 /* cmd2 */
364 move.l #0xFF404001, (%a2)
365 move.l #0x000e0000, (%a1)
366
367 move.l #0x2000, %d1
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]368 bsr asm_delay
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]369
370 /* setup nand */
371 move.l #0xFC0FFF00, %a1
372 move.l #0x30700000, (%a1)+ /* cmd1 */
373 move.l #0x007EF000, (%a1)+ /* cmd2 */
374
375 move.l #0xFC0FFF2C, %a1
376 move.l #0x00000841, (%a1)+ /* secsz */
377 move.l #0x000e0681, (%a1)+ /* cfg */
378
379 move.l #100, %d4 /* 100 pages ~200KB */
380 move.l #4, %d2 /* start at 4 */
381 move.l #0xFC0FFF04, %a0 /* cmd2 */
382 move.l #0xFC0FFF0C, %a1 /* rar */
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]383 move.l #(CONFIG_TEXT_BASE + 0xF80), %a2
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]384
385asm_nand_read:
386 move.l #0x11000000, %d0 /* rar */
387 or.l %d2, %d0
388 move.l %d0, (%a1)
389 add.l #1, %d2
390
391 move.l (%a0), %d0 /* cmd2 */
392 or.l #1, %d0
393 move.l %d0, (%a0)
394
395 move.l #0x200, %d1
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]396 bsr asm_delay
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]397
398asm_nand_chk_status:
399 move.l #0xFC0FFF38, %a4 /* isr */
400 move.l (%a4), %d0
401 and.l #0x40000000, %d0
402 tst.l %d0
403 beq asm_nand_chk_status
404
405 move.l #0xFC0FFF38, %a4 /* isr */
406 move.l (%a4), %d0
407 or.l #0x000E0000, %d0
408 move.l %d0, (%a4)
409
410 move.l #0x200, %d3
411 move.l #0xFC0FC000, %a3 /* buf 1 */
412asm_nand_copy:
413 move.l (%a3)+, (%a2)+
414 subq.l #1, %d3
415 bgt asm_nand_copy
416
417 subq.l #1, %d4
418 bgt asm_nand_read
419
420 /* jump to memory and execute */
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]421 move.l #(CONFIG_TEXT_BASE + 0x400), %a0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]422 jmp (%a0)
423
424#endif /* CONFIG_SYS_NAND_BOOT */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]425
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]426.globl asm_delay
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]427asm_delay:
428 nop
429 subq.l #1, %d1
430 bne asm_delay
431 rts
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]432#endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]433
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]434.text
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]435 . = 0x400
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]436.globl _start
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]437_start:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]438#if !defined(CONFIG_SERIAL_BOOT)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]439 nop
440 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]441 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]442
443 /* Set vector base register at the beginning of the Flash */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]444 move.l #CFG_SYS_FLASH_BASE, %d0
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]445 movec %d0, %VBR
446
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]447 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew0573a7a2007-11-07 18:00:54 -0600[diff] [blame]448 movec %d0, %RAMBAR1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]449
450 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]451 move.l #0, %d0
452 move.l #(ICACHE_STATUS), %a1 /* icache */
453 move.l #(DCACHE_STATUS), %a2 /* dcache */
454 move.l %d0, (%a1)
455 move.l %d0, (%a2)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]456
457 /* invalidate and disable cache */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]458 move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]459 movec %d0, %CACR /* Invalidate cache */
460 move.l #0, %d0
461 movec %d0, %ACR0
462 movec %d0, %ACR1
463 movec %d0, %ACR2
464 movec %d0, %ACR3
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]465#else
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]466 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]467 movec %d0, %RAMBAR1
468#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]469
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]470 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]471 move.l #__got_start, %a5
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]472
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]473 /* setup stack initially on top of internal static ram */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]474 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]475
476 /*
477 * if configured, malloc_f arena will be reserved first,
478 * then (and always) gd struct space will be reserved
479 */
480 move.l %sp, -(%sp)
481 move.l #board_init_f_alloc_reserve, %a1
482 jsr (%a1)
483
484 /* update stack and frame-pointers */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]485 move.l %d0, %sp
486 move.l %sp, %fp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]487
488 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]489 move.l %d0, -(%sp)
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]490 move.l #board_init_f_init_reserve, %a1
491 jsr (%a1)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]492
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]493 /* run low-level CPU init code (from flash) */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]494 move.l #cpu_init_f, %a1
495 jsr (%a1)
496
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]497 /* run low-level board init code (from flash) */
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]498 clr.l %sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]499 move.l #board_init_f, %a1
500 jsr (%a1)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]501
502 /* board_init_f() does not return */
503
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]504/******************************************************************************/
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]505
506/*
Simon Glass284f71b2019-12-28 10:44:45 -0700[diff] [blame]507 * void relocate_code(addr_sp, gd, addr_moni)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]508 *
509 * This "function" does not return, instead it continues in RAM
510 * after relocating the monitor code.
511 *
512 * r3 = dest
513 * r4 = src
514 * r5 = length in bytes
515 * r6 = cachelinesize
516 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]517.globl relocate_code
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]518relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]519 link.w %a6,#0
520 move.l 8(%a6), %sp /* set new stack pointer */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]521
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]522 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
523 move.l 16(%a6), %a0 /* Save copy of Destination Address */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]524
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]525 move.l #CONFIG_SYS_MONITOR_BASE, %a1
526 move.l #__init_end, %a2
527 move.l %a0, %a3
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]528
529 /* copy the code to RAM */
5301:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]531 move.l (%a1)+, (%a3)+
532 cmp.l %a1,%a2
533 bgt.s 1b
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]534
Marek Vasut549651f2023-08-27 00:25:36 +0200[diff] [blame]535#define R_68K_32 1
536#define R_68K_RELATIVE 22
537
538 move.l #(__rel_dyn_start), %a1
539 move.l #(__rel_dyn_end), %a2
540
541fixloop:
542 move.l (%a1)+, %d1 /* Elf32_Rela r_offset */
543 move.l (%a1)+, %d2 /* Elf32_Rela r_info */
544 move.l (%a1)+, %d3 /* Elf32_Rela r_addend */
545
546 andi.l #0xff, %d2
547 cmp.l #R_68K_32, %d2
548 beq.s fixup
549 cmp.l #R_68K_RELATIVE, %d2
550 beq.s fixup
551
552 bra fixnext
553
554fixup:
555 /* relative fix: store addend plus offset at dest location */
556 move.l %a0, %a3
557 add.l %d1, %a3
558 sub.l #CONFIG_SYS_MONITOR_BASE, %a3
559 move.l (%a3), %d4
560 add.l %a0, %d4
561 sub.l #CONFIG_SYS_MONITOR_BASE, %d4
562 move.l %d4, (%a3)
563
564fixnext:
565 cmp.l %a1, %a2
566 bge.s fixloop
567
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]568/*
569 * We are done. Do not return, instead branch to second part of board
570 * initialization, now running from RAM.
571 */
572 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]573 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]574 jmp (%a1)
575
576in_ram:
577
578clear_bss:
579 /*
580 * Now clear BSS segment
581 */
Marek Vasut549651f2023-08-27 00:25:36 +0200[diff] [blame]582 move.l #(_sbss), %a1
583 move.l #(_ebss), %d1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]5846:
585 clr.l (%a1)+
586 cmp.l %a1,%d1
587 bgt.s 6b
588
589 /*
590 * fix got table in RAM
591 */
Marek Vasut549651f2023-08-27 00:25:36 +0200[diff] [blame]592 move.l #(__got_start), %a5 /* fix got pointer register a5 */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]593
594 /* calculate relative jump to board_init_r in ram */
Marek Vasut549651f2023-08-27 00:25:36 +0200[diff] [blame]595 move.l #(board_init_r), %a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]596
597 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]598 move.l %a0,-(%sp) /* dest_addr */
599 move.l %d0,-(%sp) /* gd */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]600 jsr (%a1)
601
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]602/******************************************************************************/
603
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]604/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]605.globl _fault
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]606_fault:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]607 bra _fault
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]608
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]609.globl _exc_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]610_exc_handler:
611 SAVE_ALL
612 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]613 bsr exc_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]614 addql #4,%sp
615 RESTORE_ALL
616
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]617.globl _int_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]618_int_handler:
619 SAVE_ALL
620 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]621 bsr int_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]622 addql #4,%sp
623 RESTORE_ALL
624
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]625/******************************************************************************/
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]626
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]627.align 4