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git01.mediatek.com / filogic / uboot / 89ae64c595ffb189bdee34d821ec39139f5ab956 / . / arch / m68k / cpu / mcf5445x / start.S
blob: 41d9088b6afcdc4d10e74d7948eaa77ff5454c03 [file] [log] [blame]
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]5 * Copyright 2010-2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]9 */
10
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]11#include <common.h>
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]12#include <asm-offsets.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]13#include <config.h>
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]14#include <timestamp.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]15#include "version.h"
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]16#include <asm/cache.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]17
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]18#define _START _start
19#define _FAULT _fault
20
21#define SAVE_ALL \
22 move.w #0x2700,%sr; /* disable intrs */ \
23 subl #60,%sp; /* space for 15 regs */ \
24 moveml %d0-%d7/%a0-%a6,%sp@;
25
26#define RESTORE_ALL \
27 moveml %sp@,%d0-%d7/%a0-%a6; \
28 addl #60,%sp; /* space for 15 regs */ \
29 rte;
30
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]31#if defined(CONFIG_SERIAL_BOOT)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]32#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + \
33 CONFIG_SYS_INIT_RAM_ADDR)
Masahiro Yamada03390c62015-12-11 12:22:25 +0900[diff] [blame]34#define ASM_DRAMINIT_N (asm_dram_init - CONFIG_SYS_TEXT_BASE)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]35#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
36 CONFIG_SYS_INIT_RAM_ADDR)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]37#endif
38
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]39.text
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]40
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]41/*
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]42 * Vector table. This is used for initial platform startup.
43 * These vectors are to catch any un-intended traps.
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]44 */
45_vectors:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]46#if defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]47
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]48INITSP: .long 0 /* Initial SP */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]49#ifdef CONFIG_CF_SBF
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]50INITPC: .long ASM_DRAMINIT /* Initial PC */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]51#endif
52#ifdef CONFIG_SYS_NAND_BOOT
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]53INITPC: .long ASM_DRAMINIT_N /* Initial PC */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]54#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]55
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]56#else
57
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]58INITSP: .long 0 /* Initial SP */
59INITPC: .long _START /* Initial PC */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]60
61#endif
62
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]63vector02_0F:
64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
65.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]66
67/* Reserved */
68vector10_17:
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]71vector18_1F:
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]73
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]74#if !defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]75
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]76/* TRAP #0 - #15 */
77vector20_2F:
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80
81/* Reserved */
82vector30_3F:
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85
86vector64_127:
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95
96vector128_191:
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
103.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
104.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
105
106vector192_255:
107.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
109.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
110.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
111.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
113.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
114.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]115#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]116
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]117#if defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]118 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
119asm_sbf_img_hdr:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]120 .long 0x00000000 /* checksum, not yet implemented */
121 .long 0x00040000 /* image length */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200[diff] [blame]122 .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]123
124asm_dram_init:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]125 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]126
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]127#ifdef CONFIG_SYS_NAND_BOOT
128 /* for assembly stack */
129 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
130 movec %d0, %RAMBAR1
131
132 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]133 clr.l %sp@-
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]134#endif
135
136#ifdef CONFIG_CF_SBF
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]137 move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
138 movec %d0, %VBR
139
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]140 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]141 movec %d0, %RAMBAR1
142
143 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]144 move.l #0, %d0
145 move.l #(ICACHE_STATUS), %a1 /* icache */
146 move.l #(DCACHE_STATUS), %a2 /* dcache */
147 move.l %d0, (%a1)
148 move.l %d0, (%a2)
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]149
150 /* invalidate and disable cache */
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]151 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]152 movec %d0, %CACR /* Invalidate cache */
153 move.l #0, %d0
154 movec %d0, %ACR0
155 movec %d0, %ACR1
156 movec %d0, %ACR2
157 movec %d0, %ACR3
158
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]159 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]160 clr.l %sp@-
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]161
162 /* Must disable global address */
163 move.l #0xFC008000, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]164 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]165 move.l #0xFC008008, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]166 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]167 move.l #0xFC008004, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]168 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]169#endif /* CONFIG_CF_SBF */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]170
171#ifdef CONFIG_MCF5441x
172 /* TC: enable all peripherals,
173 in the future only enable certain peripherals */
174 move.l #0xFC04002D, %a1
175
176#if defined(CONFIG_CF_SBF)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]177 move.b #23, (%a1) /* dspi */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]178#endif
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame^]179#endif /* CONFIG_MCF5441x */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]180
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame^]181 /* mandatory board level ddr-sdram init,
182 * for both 5441x and 5445x
183 */
184 bsr sbf_dram_init
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]185
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]186#ifdef CONFIG_CF_SBF
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]187 /*
188 * DSPI Initialization
189 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
190 * a1 - dspi status
191 * a2 - dtfr
192 * a3 - drfr
193 * a4 - Dst addr
194 */
195 /* Enable pins for DSPI mode - chip-selects are enabled later */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]196asm_dspi_init:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]197#ifdef CONFIG_MCF5441x
198 move.l #0xEC09404E, %a1
199 move.l #0xEC09404F, %a2
200 move.b #0xFF, (%a1)
201 move.b #0x80, (%a2)
202#endif
203
204#ifdef CONFIG_MCF5445x
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]205 move.l #0xFC0A4063, %a0
206 move.b #0x7F, (%a0)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]207#endif
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]208 /* Configure DSPI module */
209 move.l #0xFC05C000, %a0
210 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
211
212 move.l #0xFC05C00C, %a0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]213#ifdef CONFIG_MCF5441x
214 move.l #0x3E000016, (%a0)
215#endif
216#ifdef CONFIG_MCF5445x
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]217 move.l #0x3E000011, (%a0)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]218#endif
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]219
220 move.l #0xFC05C034, %a2 /* dtfr */
221 move.l #0xFC05C03B, %a3 /* drfr */
222
223 move.l #(ASM_SBF_IMG_HDR + 4), %a1
224 move.l (%a1)+, %d5
225 move.l (%a1), %a4
226
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]227 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
228 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]229
230 move.l #0xFC05C02C, %a1 /* dspi status */
231
232 /* Issue commands and address */
233 move.l #0x8002000B, %d2 /* Fast Read Cmd */
234 jsr asm_dspi_wr_status
235 jsr asm_dspi_rd_status
236
237 move.l #0x80020000, %d2 /* Address byte 2 */
238 jsr asm_dspi_wr_status
239 jsr asm_dspi_rd_status
240
241 move.l #0x80020000, %d2 /* Address byte 1 */
242 jsr asm_dspi_wr_status
243 jsr asm_dspi_rd_status
244
245 move.l #0x80020000, %d2 /* Address byte 0 */
246 jsr asm_dspi_wr_status
247 jsr asm_dspi_rd_status
248
249 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
250 jsr asm_dspi_wr_status
251 jsr asm_dspi_rd_status
252
253 /* Transfer serial boot header to sram */
254asm_dspi_rd_loop1:
255 move.l #0x80020000, %d2
256 jsr asm_dspi_wr_status
257 jsr asm_dspi_rd_status
258
259 move.b %d1, (%a0) /* read, copy to dst */
260
261 add.l #1, %a0 /* inc dst by 1 */
262 sub.l #1, %d4 /* dec cnt by 1 */
263 bne asm_dspi_rd_loop1
264
265 /* Transfer u-boot from serial flash to memory */
266asm_dspi_rd_loop2:
267 move.l #0x80020000, %d2
268 jsr asm_dspi_wr_status
269 jsr asm_dspi_rd_status
270
271 move.b %d1, (%a4) /* read, copy to dst */
272
273 add.l #1, %a4 /* inc dst by 1 */
274 sub.l #1, %d5 /* dec cnt by 1 */
275 bne asm_dspi_rd_loop2
276
277 move.l #0x00020000, %d2 /* Terminate */
278 jsr asm_dspi_wr_status
279 jsr asm_dspi_rd_status
280
281 /* jump to memory and execute */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200[diff] [blame]282 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]283 jmp (%a0)
284
285asm_dspi_wr_status:
286 move.l (%a1), %d0 /* status */
287 and.l #0x0000F000, %d0
288 cmp.l #0x00003000, %d0
289 bgt asm_dspi_wr_status
290
291 move.l %d2, (%a2)
292 rts
293
294asm_dspi_rd_status:
295 move.l (%a1), %d0 /* status */
296 and.l #0x000000F0, %d0
297 lsr.l #4, %d0
298 cmp.l #0, %d0
299 beq asm_dspi_rd_status
300
301 move.b (%a3), %d1
302 rts
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]303#endif /* CONFIG_CF_SBF */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]304
305#ifdef CONFIG_SYS_NAND_BOOT
306 /* copy 4 boot pages to dram as soon as possible */
307 /* each page is 996 bytes (1056 total with 60 ECC bytes */
308 move.l #0x00000000, %a1 /* src */
Masahiro Yamada03390c62015-12-11 12:22:25 +0900[diff] [blame]309 move.l #CONFIG_SYS_TEXT_BASE, %a2 /* dst */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]310 move.l #0x3E0, %d0 /* sz in long */
311
312asm_boot_nand_copy:
313 move.l (%a1)+, (%a2)+
314 subq.l #1, %d0
315 bne asm_boot_nand_copy
316
317 /* jump to memory and execute */
318 move.l #(asm_nand_init), %a0
319 jmp (%a0)
320
321asm_nand_init:
322 /* exit nand boot-mode */
323 move.l #0xFC0FFF30, %a1
324 or.l #0x00000040, %d1
325 move.l %d1, (%a1)
326
327 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]328 move.l #0, %d0
329 move.l #(CACR_STATUS), %a1 /* CACR */
330 move.l #(ICACHE_STATUS), %a2 /* icache */
331 move.l #(DCACHE_STATUS), %a3 /* dcache */
332 move.l %d0, (%a1)
333 move.l %d0, (%a2)
334 move.l %d0, (%a3)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]335
336 /* invalidate and disable cache */
337 move.l #0x01004100, %d0 /* Invalidate cache cmd */
338 movec %d0, %CACR /* Invalidate cache */
339 move.l #0, %d0
340 movec %d0, %ACR0
341 movec %d0, %ACR1
342 movec %d0, %ACR2
343 movec %d0, %ACR3
344
345 /* Must disable global address */
346 move.l #0xFC008000, %a1
347 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
348 move.l #0xFC008008, %a1
349 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
350 move.l #0xFC008004, %a1
351 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
352
353 /* NAND port configuration */
354 move.l #0xEC094048, %a1
355 move.b #0xFD, (%a1)+
356 move.b #0x5F, (%a1)+
357 move.b #0x04, (%a1)+
358
359 /* reset nand */
360 move.l #0xFC0FFF38, %a1 /* isr */
361 move.l #0x000e0000, (%a1)
362 move.l #0xFC0FFF08, %a2
363 move.l #0x00000000, (%a2)+ /* car */
364 move.l #0x11000000, (%a2)+ /* rar */
365 move.l #0x00000000, (%a2)+ /* rpt */
366 move.l #0x00000000, (%a2)+ /* rai */
367 move.l #0xFC0FFF2c, %a2 /* cfg */
368 move.l #0x00000000, (%a2)+ /* secsz */
369 move.l #0x000e0681, (%a2)+
370 move.l #0xFC0FFF04, %a2 /* cmd2 */
371 move.l #0xFF404001, (%a2)
372 move.l #0x000e0000, (%a1)
373
374 move.l #0x2000, %d1
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame^]375 bsr asm_delay
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]376
377 /* setup nand */
378 move.l #0xFC0FFF00, %a1
379 move.l #0x30700000, (%a1)+ /* cmd1 */
380 move.l #0x007EF000, (%a1)+ /* cmd2 */
381
382 move.l #0xFC0FFF2C, %a1
383 move.l #0x00000841, (%a1)+ /* secsz */
384 move.l #0x000e0681, (%a1)+ /* cfg */
385
386 move.l #100, %d4 /* 100 pages ~200KB */
387 move.l #4, %d2 /* start at 4 */
388 move.l #0xFC0FFF04, %a0 /* cmd2 */
389 move.l #0xFC0FFF0C, %a1 /* rar */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]390 move.l #(CONFIG_SYS_TEXT_BASE + 0xF80), %a2
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]391
392asm_nand_read:
393 move.l #0x11000000, %d0 /* rar */
394 or.l %d2, %d0
395 move.l %d0, (%a1)
396 add.l #1, %d2
397
398 move.l (%a0), %d0 /* cmd2 */
399 or.l #1, %d0
400 move.l %d0, (%a0)
401
402 move.l #0x200, %d1
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame^]403 bsr asm_delay
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]404
405asm_nand_chk_status:
406 move.l #0xFC0FFF38, %a4 /* isr */
407 move.l (%a4), %d0
408 and.l #0x40000000, %d0
409 tst.l %d0
410 beq asm_nand_chk_status
411
412 move.l #0xFC0FFF38, %a4 /* isr */
413 move.l (%a4), %d0
414 or.l #0x000E0000, %d0
415 move.l %d0, (%a4)
416
417 move.l #0x200, %d3
418 move.l #0xFC0FC000, %a3 /* buf 1 */
419asm_nand_copy:
420 move.l (%a3)+, (%a2)+
421 subq.l #1, %d3
422 bgt asm_nand_copy
423
424 subq.l #1, %d4
425 bgt asm_nand_read
426
427 /* jump to memory and execute */
Masahiro Yamada03390c62015-12-11 12:22:25 +0900[diff] [blame]428 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]429 jmp (%a0)
430
431#endif /* CONFIG_SYS_NAND_BOOT */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]432
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame^]433.globl asm_delay
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]434asm_delay:
435 nop
436 subq.l #1, %d1
437 bne asm_delay
438 rts
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]439#endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]440
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]441.text
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]442 . = 0x400
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]443.globl _start
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]444_start:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]445#if !defined(CONFIG_SERIAL_BOOT)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]446 nop
447 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]448 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]449
450 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]451 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]452 movec %d0, %VBR
453
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]454 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew0573a7a2007-11-07 18:00:54 -0600[diff] [blame]455 movec %d0, %RAMBAR1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]456
457 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]458 move.l #0, %d0
459 move.l #(ICACHE_STATUS), %a1 /* icache */
460 move.l #(DCACHE_STATUS), %a2 /* dcache */
461 move.l %d0, (%a1)
462 move.l %d0, (%a2)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]463
464 /* invalidate and disable cache */
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]465 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]466 movec %d0, %CACR /* Invalidate cache */
467 move.l #0, %d0
468 movec %d0, %ACR0
469 movec %d0, %ACR1
470 movec %d0, %ACR2
471 movec %d0, %ACR3
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]472#else
473 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
474 movec %d0, %RAMBAR1
475#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]476
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]477 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]478 move.l #__got_start, %a5
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]479
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]480 /* setup stack initially on top of internal static ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]481 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]482
483 /*
484 * if configured, malloc_f arena will be reserved first,
485 * then (and always) gd struct space will be reserved
486 */
487 move.l %sp, -(%sp)
488 move.l #board_init_f_alloc_reserve, %a1
489 jsr (%a1)
490
491 /* update stack and frame-pointers */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]492 move.l %d0, %sp
493 move.l %sp, %fp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]494
495 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]496 move.l %d0, -(%sp)
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]497 move.l #board_init_f_init_reserve, %a1
498 jsr (%a1)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]499
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]500 /* run low-level CPU init code (from flash) */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]501 move.l #cpu_init_f, %a1
502 jsr (%a1)
503
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]504 /* run low-level board init code (from flash) */
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]505 clr.l %sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]506 move.l #board_init_f, %a1
507 jsr (%a1)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]508
509 /* board_init_f() does not return */
510
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]511/******************************************************************************/
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]512
513/*
514 * void relocate_code (addr_sp, gd, addr_moni)
515 *
516 * This "function" does not return, instead it continues in RAM
517 * after relocating the monitor code.
518 *
519 * r3 = dest
520 * r4 = src
521 * r5 = length in bytes
522 * r6 = cachelinesize
523 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]524.globl relocate_code
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]525relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]526 link.w %a6,#0
527 move.l 8(%a6), %sp /* set new stack pointer */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]528
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]529 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
530 move.l 16(%a6), %a0 /* Save copy of Destination Address */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]531
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]532 move.l #CONFIG_SYS_MONITOR_BASE, %a1
533 move.l #__init_end, %a2
534 move.l %a0, %a3
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]535
536 /* copy the code to RAM */
5371:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]538 move.l (%a1)+, (%a3)+
539 cmp.l %a1,%a2
540 bgt.s 1b
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]541
542/*
543 * We are done. Do not return, instead branch to second part of board
544 * initialization, now running from RAM.
545 */
546 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]547 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]548 jmp (%a1)
549
550in_ram:
551
552clear_bss:
553 /*
554 * Now clear BSS segment
555 */
556 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]557 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]558 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]559 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]5606:
561 clr.l (%a1)+
562 cmp.l %a1,%d1
563 bgt.s 6b
564
565 /*
566 * fix got table in RAM
567 */
568 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]569 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]570 move.l %a1,%a5 /* fix got pointer register a5 */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]571
572 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]573 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]574
5757:
576 move.l (%a1),%d1
577 sub.l #_start,%d1
578 add.l %a0,%d1
579 move.l %d1,(%a1)+
580 cmp.l %a2, %a1
581 bne 7b
582
583 /* calculate relative jump to board_init_r in ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]584 move.l %a0, %a1
585 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]586
587 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]588 move.l %a0,-(%sp) /* dest_addr */
589 move.l %d0,-(%sp) /* gd */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]590 jsr (%a1)
591
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]592/******************************************************************************/
593
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]594/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]595.globl _fault
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]596_fault:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]597 bra _fault
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]598
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]599.globl _exc_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]600_exc_handler:
601 SAVE_ALL
602 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]603 bsr exc_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]604 addql #4,%sp
605 RESTORE_ALL
606
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]607.globl _int_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]608_int_handler:
609 SAVE_ALL
610 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]611 bsr int_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]612 addql #4,%sp
613 RESTORE_ALL
614
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]615/******************************************************************************/
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]616
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]617.globl version_string
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]618version_string:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]619.ascii U_BOOT_VERSION_STRING, "\0"
620.align 4