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git01.mediatek.com / filogic / uboot / 23cf8fd6cb91bd46face2ec858d1fd8c340794d1 / . / cpu / mcf5445x / start.S
blob: 2a6019bbfc7a84bd2c5b9c7e705b3d8c3077780c [file] [log] [blame]
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25#include "version.h"
26
27#ifndef CONFIG_IDENT_STRING
28#define CONFIG_IDENT_STRING ""
29#endif
30
31/* last three long word reserved for cache status */
32#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
33#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
34#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
35
36#define _START _start
37#define _FAULT _fault
38
39#define SAVE_ALL \
40 move.w #0x2700,%sr; /* disable intrs */ \
41 subl #60,%sp; /* space for 15 regs */ \
42 moveml %d0-%d7/%a0-%a6,%sp@;
43
44#define RESTORE_ALL \
45 moveml %sp@,%d0-%d7/%a0-%a6; \
46 addl #60,%sp; /* space for 15 regs */ \
47 rte;
48
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame^]49#if defined(CONFIG_CF_SBF)
50#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CFG_INIT_RAM_ADDR)
51#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CFG_INIT_RAM_ADDR)
52#endif
53
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]54.text
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame^]55
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]56/*
57 * Vector table. This is used for initial platform startup.
58 * These vectors are to catch any un-intended traps.
59 */
60_vectors:
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame^]61#if defined(CONFIG_CF_SBF)
62
63INITSP: .long 0 /* Initial SP */
64INITPC: .long ASM_DRAMINIT /* Initial PC */
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]65
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame^]66#else
67
68INITSP: .long 0 /* Initial SP */
69INITPC: .long _START /* Initial PC */
70
71#endif
72
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]73vector02: .long _FAULT /* Access Error */
74vector03: .long _FAULT /* Address Error */
75vector04: .long _FAULT /* Illegal Instruction */
76vector05: .long _FAULT /* Reserved */
77vector06: .long _FAULT /* Reserved */
78vector07: .long _FAULT /* Reserved */
79vector08: .long _FAULT /* Privilege Violation */
80vector09: .long _FAULT /* Trace */
81vector0A: .long _FAULT /* Unimplemented A-Line */
82vector0B: .long _FAULT /* Unimplemented F-Line */
83vector0C: .long _FAULT /* Debug Interrupt */
84vector0D: .long _FAULT /* Reserved */
85vector0E: .long _FAULT /* Format Error */
86vector0F: .long _FAULT /* Unitialized Int. */
87
88/* Reserved */
89vector10_17:
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91
92vector18: .long _FAULT /* Spurious Interrupt */
93vector19: .long _FAULT /* Autovector Level 1 */
94vector1A: .long _FAULT /* Autovector Level 2 */
95vector1B: .long _FAULT /* Autovector Level 3 */
96vector1C: .long _FAULT /* Autovector Level 4 */
97vector1D: .long _FAULT /* Autovector Level 5 */
98vector1E: .long _FAULT /* Autovector Level 6 */
99vector1F: .long _FAULT /* Autovector Level 7 */
100
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame^]101#if !defined(CONFIG_CF_SBF)
102
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]103/* TRAP #0 - #15 */
104vector20_2F:
105.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
106.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107
108/* Reserved */
109vector30_3F:
110.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
111.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112
113vector64_127:
114.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
115.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
116.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
117.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
118.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
119.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
120.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
121.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
122
123vector128_191:
124.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
125.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
126.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
127.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
128.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
129.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
130.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
131.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
132
133vector192_255:
134.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
135.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
136.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
137.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
138.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
139.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
140.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
141.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame^]142#endif
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]143
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame^]144#if defined(CONFIG_CF_SBF)
145 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
146asm_sbf_img_hdr:
147 .long 0x00000000 /* checksum, not yet implemented */
148 .long 0x00030000 /* image length */
149 .long TEXT_BASE /* image to be relocated at */
150
151asm_dram_init:
152 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
153 movec %d0, %RAMBAR1 /* init Rambar */
154 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
155 clr.l %sp@-
156
157 /* Must disable global address */
158 move.l #0xFC008000, %a1
159 move.l #(CFG_CS0_BASE), (%a1)
160 move.l #0xFC008008, %a1
161 move.l #(CFG_CS0_CTRL), (%a1)
162 move.l #0xFC008004, %a1
163 move.l #(CFG_CS0_MASK), (%a1)
164
165 /*
166 * Dram Initialization
167 * a1, a2, and d0
168 */
169 /* mscr sdram */
170 move.l #0xFC0A4074, %a1
171 move.b #(CFG_SDRAM_DRV_STRENGTH), (%a1)
172 nop
173
174 /* SDRAM Chip 0 and 1 */
175 move.l #0xFC0B8110, %a1
176 move.l #0xFC0B8114, %a2
177
178 /* calculate the size */
179 move.l #0x13, %d1
180 move.l #(CFG_SDRAM_SIZE), %d2
181#ifdef CFG_SDRAM_BASE1
182 lsr.l #1, %d2
183#endif
184
185dramsz_loop:
186 lsr.l #1, %d2
187 add.l #1, %d1
188 cmp.l #1, %d2
189 bne dramsz_loop
190
191 /* SDRAM Chip 0 and 1 */
192 move.l #(CFG_SDRAM_BASE), (%a1)
193 or.l %d1, (%a1)
194#ifdef CFG_SDRAM_BASE1
195 move.l #(CFG_SDRAM_BASE1), (%a2)
196 or.l %d1, (%a2)
197#endif
198 nop
199
200 /* dram cfg1 and cfg2 */
201 move.l #0xFC0B8008, %a1
202 move.l #(CFG_SDRAM_CFG1), (%a1)
203 nop
204 move.l #0xFC0B800C, %a2
205 move.l #(CFG_SDRAM_CFG2), (%a2)
206 nop
207
208 move.l #0xFC0B8000, %a1 /* Mode */
209 move.l #0xFC0B8004, %a2 /* Ctrl */
210
211#ifdef CONFIG_M54455EVB
212 /* Issue PALL */
213 move.l #(CFG_SDRAM_CTRL + 2), (%a2)
214 nop
215
216 /* Issue LEMR */
217 move.l #(CFG_SDRAM_EMOD + 0x408), (%a1)
218 nop
219 move.l #(CFG_SDRAM_MODE + 0x300), (%a1)
220 nop
221
222 move.l #1000, %d0
223wait1000:
224 nop
225 subq.l #1, %d0
226 bne wait1000
227#endif
228
229 /* Issue PALL */
230 move.l #(CFG_SDRAM_CTRL + 2), (%a2)
231 nop
232
233 /* Perform two refresh cycles */
234 move.l #(CFG_SDRAM_CTRL + 4), %d0
235 nop
236 move.l %d0, (%a2)
237 move.l %d0, (%a2)
238 nop
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]239
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame^]240#ifdef CONFIG_M54455EVB
241 move.l #(CFG_SDRAM_MODE + 0x200), (%a1)
242 nop
243#elif defined(CONFIG_M54451EVB)
244 /* Issue LEMR */
245 move.l #(CFG_SDRAM_MODE), (%a2)
246 nop
247 move.l #(CFG_SDRAM_EMOD), (%a2)
248 nop
249#endif
250
251 move.l #500, %d0
252wait500:
253 nop
254 subq.l #1, %d0
255 bne wait500
256
257 move.l #(CFG_SDRAM_CTRL), %d0
258 and.l #0x7FFFFFFF, %d0
259#ifdef CONFIG_M54455EVB
260 or.l #0x10000c00, %d0
261#elif defined(CONFIG_M54451EVB)
262 or.l #0x10000000, %d0
263#endif
264 move.l %d0, (%a2)
265 nop
266
267 /*
268 * DSPI Initialization
269 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
270 * a1 - dspi status
271 * a2 - dtfr
272 * a3 - drfr
273 * a4 - Dst addr
274 */
275 /* Enable pins for DSPI mode - chip-selects are enabled later */
276 move.l #0xFC0A4063, %a0
277 move.b #0x7F, (%a0)
278
279 /* Configure DSPI module */
280 move.l #0xFC05C000, %a0
281 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
282
283 move.l #0xFC05C00C, %a0
284 move.l #0x3E000011, (%a0)
285
286 move.l #0xFC05C034, %a2 /* dtfr */
287 move.l #0xFC05C03B, %a3 /* drfr */
288
289 move.l #(ASM_SBF_IMG_HDR + 4), %a1
290 move.l (%a1)+, %d5
291 move.l (%a1), %a4
292
293 move.l #(CFG_INIT_RAM_ADDR + CFG_SBFHDR_DATA_OFFSET), %a0
294 move.l #(CFG_SBFHDR_SIZE), %d4
295
296 move.l #0xFC05C02C, %a1 /* dspi status */
297
298 /* Issue commands and address */
299 move.l #0x8002000B, %d2 /* Fast Read Cmd */
300 jsr asm_dspi_wr_status
301 jsr asm_dspi_rd_status
302
303 move.l #0x80020000, %d2 /* Address byte 2 */
304 jsr asm_dspi_wr_status
305 jsr asm_dspi_rd_status
306
307 move.l #0x80020000, %d2 /* Address byte 1 */
308 jsr asm_dspi_wr_status
309 jsr asm_dspi_rd_status
310
311 move.l #0x80020000, %d2 /* Address byte 0 */
312 jsr asm_dspi_wr_status
313 jsr asm_dspi_rd_status
314
315 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
316 jsr asm_dspi_wr_status
317 jsr asm_dspi_rd_status
318
319 /* Transfer serial boot header to sram */
320asm_dspi_rd_loop1:
321 move.l #0x80020000, %d2
322 jsr asm_dspi_wr_status
323 jsr asm_dspi_rd_status
324
325 move.b %d1, (%a0) /* read, copy to dst */
326
327 add.l #1, %a0 /* inc dst by 1 */
328 sub.l #1, %d4 /* dec cnt by 1 */
329 bne asm_dspi_rd_loop1
330
331 /* Transfer u-boot from serial flash to memory */
332asm_dspi_rd_loop2:
333 move.l #0x80020000, %d2
334 jsr asm_dspi_wr_status
335 jsr asm_dspi_rd_status
336
337 move.b %d1, (%a4) /* read, copy to dst */
338
339 add.l #1, %a4 /* inc dst by 1 */
340 sub.l #1, %d5 /* dec cnt by 1 */
341 bne asm_dspi_rd_loop2
342
343 move.l #0x00020000, %d2 /* Terminate */
344 jsr asm_dspi_wr_status
345 jsr asm_dspi_rd_status
346
347 /* jump to memory and execute */
348 move.l #(TEXT_BASE + 0x400), %a0
349 jmp (%a0)
350
351asm_dspi_wr_status:
352 move.l (%a1), %d0 /* status */
353 and.l #0x0000F000, %d0
354 cmp.l #0x00003000, %d0
355 bgt asm_dspi_wr_status
356
357 move.l %d2, (%a2)
358 rts
359
360asm_dspi_rd_status:
361 move.l (%a1), %d0 /* status */
362 and.l #0x000000F0, %d0
363 lsr.l #4, %d0
364 cmp.l #0, %d0
365 beq asm_dspi_rd_status
366
367 move.b (%a3), %d1
368 rts
369#endif /* CONFIG_CF_SBF */
370
371 .text
372 . = 0x400
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]373 .globl _start
374_start:
375 nop
376 nop
377 move.w #0x2700,%sr /* Mask off Interrupt */
378
379 /* Set vector base register at the beginning of the Flash */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame^]380#if defined(CONFIG_CF_SBF)
381 move.l #TEXT_BASE, %d0
382 movec %d0, %VBR
383#else
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]384 move.l #CFG_FLASH_BASE, %d0
385 movec %d0, %VBR
386
387 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
TsiChungLiew0573a7a2007-11-07 18:00:54 -0600[diff] [blame]388 movec %d0, %RAMBAR1
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame^]389#endif
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]390
391 /* initialize general use internal ram */
392 move.l #0, %d0
393 move.l #(CACR_STATUS), %a1 /* CACR */
394 move.l #(ICACHE_STATUS), %a2 /* icache */
395 move.l #(DCACHE_STATUS), %a3 /* dcache */
396 move.l %d0, (%a1)
397 move.l %d0, (%a2)
398 move.l %d0, (%a3)
399
400 /* invalidate and disable cache */
401 move.l #0x01004100, %d0 /* Invalidate cache cmd */
402 movec %d0, %CACR /* Invalidate cache */
403 move.l #0, %d0
404 movec %d0, %ACR0
405 movec %d0, %ACR1
406 movec %d0, %ACR2
407 movec %d0, %ACR3
408
409 /* set stackpointer to end of internal ram to get some stackspace for
410 the first c-code */
411 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
412 clr.l %sp@-
413
414 move.l #__got_start, %a5 /* put relocation table address to a5 */
415
416 bsr cpu_init_f /* run low-level CPU init code (from flash) */
417 bsr board_init_f /* run low-level board init code (from flash) */
418
419 /* board_init_f() does not return */
420
421/*------------------------------------------------------------------------------*/
422
423/*
424 * void relocate_code (addr_sp, gd, addr_moni)
425 *
426 * This "function" does not return, instead it continues in RAM
427 * after relocating the monitor code.
428 *
429 * r3 = dest
430 * r4 = src
431 * r5 = length in bytes
432 * r6 = cachelinesize
433 */
434 .globl relocate_code
435relocate_code:
436 link.w %a6,#0
437 move.l 8(%a6), %sp /* set new stack pointer */
438
439 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
440 move.l 16(%a6), %a0 /* Save copy of Destination Address */
441
442 move.l #CFG_MONITOR_BASE, %a1
443 move.l #__init_end, %a2
444 move.l %a0, %a3
445
446 /* copy the code to RAM */
4471:
448 move.l (%a1)+, (%a3)+
449 cmp.l %a1,%a2
450 bgt.s 1b
451
452/*
453 * We are done. Do not return, instead branch to second part of board
454 * initialization, now running from RAM.
455 */
456 move.l %a0, %a1
457 add.l #(in_ram - CFG_MONITOR_BASE), %a1
458 jmp (%a1)
459
460in_ram:
461
462clear_bss:
463 /*
464 * Now clear BSS segment
465 */
466 move.l %a0, %a1
467 add.l #(_sbss - CFG_MONITOR_BASE),%a1
468 move.l %a0, %d1
469 add.l #(_ebss - CFG_MONITOR_BASE),%d1
4706:
471 clr.l (%a1)+
472 cmp.l %a1,%d1
473 bgt.s 6b
474
475 /*
476 * fix got table in RAM
477 */
478 move.l %a0, %a1
479 add.l #(__got_start - CFG_MONITOR_BASE),%a1
480 move.l %a1,%a5 /* * fix got pointer register a5 */
481
482 move.l %a0, %a2
483 add.l #(__got_end - CFG_MONITOR_BASE),%a2
484
4857:
486 move.l (%a1),%d1
487 sub.l #_start,%d1
488 add.l %a0,%d1
489 move.l %d1,(%a1)+
490 cmp.l %a2, %a1
491 bne 7b
492
493 /* calculate relative jump to board_init_r in ram */
494 move.l %a0, %a1
495 add.l #(board_init_r - CFG_MONITOR_BASE), %a1
496
497 /* set parameters for board_init_r */
498 move.l %a0,-(%sp) /* dest_addr */
499 move.l %d0,-(%sp) /* gd */
500 jsr (%a1)
501
502/*------------------------------------------------------------------------------*/
503/* exception code */
504 .globl _fault
505_fault:
TsiChung Liew160e11e2008-06-18 19:12:13 -0500[diff] [blame]506 bra _fault
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]507 .globl _exc_handler
508
509_exc_handler:
510 SAVE_ALL
511 movel %sp,%sp@-
512 bsr exc_handler
513 addql #4,%sp
514 RESTORE_ALL
515
516 .globl _int_handler
517_int_handler:
518 SAVE_ALL
519 movel %sp,%sp@-
520 bsr int_handler
521 addql #4,%sp
522 RESTORE_ALL
523
524/*------------------------------------------------------------------------------*/
525/* cache functions */
526 .globl icache_enable
527icache_enable:
528 move.l #(CACR_STATUS), %a1 /* read CACR Status */
529 move.l (%a1), %d1
530
531 move.l #0x00040100, %d0 /* Invalidate icache */
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]532 movec %d0, %CACR
533
TsiChungLiew3b790502008-01-14 17:11:47 -0600[diff] [blame]534 move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]535 movec %d0, %ACR2
536
TsiChungLiew3b790502008-01-14 17:11:47 -0600[diff] [blame]537 move.l #0x04088020, %d0 /* Enable bcache and icache */
538 movec %d0, %CACR
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]539
540 move.l #(ICACHE_STATUS), %a1
541 moveq #1, %d0
542 move.l %d0, (%a1)
543 rts
544
545 .globl icache_disable
546icache_disable:
547 move.l #(CACR_STATUS), %a1 /* read CACR Status */
548 move.l (%a1), %d0
549
TsiChungLiew3b790502008-01-14 17:11:47 -0600[diff] [blame]550 move.l #0xFFF77BFF, %d0
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]551 or.l #0x00040100, %d0 /* Setup cache mask */
552 movec %d0, %CACR /* Invalidate icache */
553 clr.l %d0
554 movec %d0, %ACR2
555 movec %d0, %ACR3
556
557 move.l #(ICACHE_STATUS), %a1
558 moveq #0, %d0
559 move.l %d0, (%a1)
560 rts
561
562 .globl icache_status
563icache_status:
564 move.l #(ICACHE_STATUS), %a1
565 move.l (%a1), %d0
566 rts
567
568 .globl icache_invalid
569icache_invalid:
570 move.l #(CACR_STATUS), %a1 /* read CACR Status */
571 move.l (%a1), %d0
572
TsiChungLiew3b790502008-01-14 17:11:47 -0600[diff] [blame]573 move.l #0x00040100, %d0 /* Invalidate icache */
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]574 movec %d0, %CACR /* Enable and invalidate cache */
575 rts
576
577 .globl dcache_enable
578dcache_enable:
579 move.l #(CACR_STATUS), %a1 /* read CACR Status */
580 move.l (%a1), %d1
581
TsiChungLiew3b790502008-01-14 17:11:47 -0600[diff] [blame]582 move.l #0x01040100, %d0
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]583 movec %d0, %CACR /* Invalidate dcache */
584
TsiChungLiew3b790502008-01-14 17:11:47 -0600[diff] [blame]585 move.l #0x80088020, %d0 /* Enable bcache and icache */
586 movec %d0, %CACR
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]587
588 move.l #(DCACHE_STATUS), %a1
589 moveq #1, %d0
590 move.l %d0, (%a1)
591 rts
592
593 .globl dcache_disable
594dcache_disable:
595 move.l #(CACR_STATUS), %a1 /* read CACR Status */
596 move.l (%a1), %d0
597
598 and.l #0x7FFFFFFF, %d0
599 or.l #0x01000000, %d0 /* Setup cache mask */
600 movec %d0, %CACR /* Disable dcache */
601 clr.l %d0
602 movec %d0, %ACR0
603 movec %d0, %ACR1
604
605 move.l #(DCACHE_STATUS), %a1
606 moveq #0, %d0
607 move.l %d0, (%a1)
608 rts
609
610 .globl dcache_invalid
611dcache_invalid:
612 move.l #(CACR_STATUS), %a1 /* read CACR Status */
613 move.l (%a1), %d0
614
TsiChungLiew3b790502008-01-14 17:11:47 -0600[diff] [blame]615 move.l #0x81088020, %d0 /* Setup cache mask */
TsiChungLiewfc3ca3b2007-08-16 15:05:11 -0500[diff] [blame]616 movec %d0, %CACR /* Enable and invalidate cache */
617 rts
618
619 .globl dcache_status
620dcache_status:
621 move.l #(DCACHE_STATUS), %a1
622 move.l (%a1), %d0
623 rts
624
625/*------------------------------------------------------------------------------*/
626
627 .globl version_string
628version_string:
629 .ascii U_BOOT_VERSION
630 .ascii " (", __DATE__, " - ", __TIME__, ")"
631 .ascii CONFIG_IDENT_STRING, "\0"
TsiChung Liew9d636e92008-03-28 08:47:45 -0500[diff] [blame]632 .align 4