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git01.mediatek.com / filogic / uboot / 549651fe21d8a2ac3090af2451b104c1190bf899 / . / arch / m68k / cpu / mcf5445x / start.S
blob: 5c3bfff791836b6d7eedda2896101099138daacd [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]2/*
3 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
4 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
5 *
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]6 * Copyright 2010-2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]8 */
9
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]10#include <common.h>
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]11#include <asm-offsets.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]12#include <config.h>
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]13#include <asm/cache.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]14
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]15#define _START _start
16#define _FAULT _fault
17
18#define SAVE_ALL \
19 move.w #0x2700,%sr; /* disable intrs */ \
20 subl #60,%sp; /* space for 15 regs */ \
21 moveml %d0-%d7/%a0-%a6,%sp@;
22
23#define RESTORE_ALL \
24 moveml %sp@,%d0-%d7/%a0-%a6; \
25 addl #60,%sp; /* space for 15 regs */ \
26 rte;
27
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]28#if defined(CONFIG_SERIAL_BOOT)
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]29#define ASM_DRAMINIT (asm_dram_init - CONFIG_TEXT_BASE + \
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]30 CFG_SYS_INIT_RAM_ADDR)
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]31#define ASM_DRAMINIT_N (asm_dram_init - CONFIG_TEXT_BASE)
32#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_TEXT_BASE + \
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]33 CFG_SYS_INIT_RAM_ADDR)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]34#endif
35
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]36.text
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]37
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]38/*
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]39 * Vector table. This is used for initial platform startup.
40 * These vectors are to catch any un-intended traps.
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]41 */
42_vectors:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]43#if defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]44
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]45INITSP: .long 0 /* Initial SP */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]46#ifdef CONFIG_CF_SBF
Wolfgang Denk62fb2b42021-09-27 17:42:39 +0200[diff] [blame]47INITPC: .long ASM_DRAMINIT /* Initial PC */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]48#endif
49#ifdef CONFIG_SYS_NAND_BOOT
Wolfgang Denk62fb2b42021-09-27 17:42:39 +0200[diff] [blame]50INITPC: .long ASM_DRAMINIT_N /* Initial PC */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]51#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]52
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]53#else
54
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]55INITSP: .long 0 /* Initial SP */
Wolfgang Denk62fb2b42021-09-27 17:42:39 +0200[diff] [blame]56INITPC: .long _START /* Initial PC */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]57
58#endif
59
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]60vector02_0F:
61.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
62.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]63
64/* Reserved */
65vector10_17:
66.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
67
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]68vector18_1F:
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]70
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]71#if !defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]72
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]73/* TRAP #0 - #15 */
74vector20_2F:
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77
78/* Reserved */
79vector30_3F:
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82
83vector64_127:
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92
93vector128_191:
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102
103vector192_255:
104.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
105.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
106.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
109.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
110.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
111.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]112#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]113
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]114#if defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]115 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
116asm_sbf_img_hdr:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]117 .long 0x00000000 /* checksum, not yet implemented */
118 .long 0x00040000 /* image length */
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]119 .long CONFIG_TEXT_BASE /* image to be relocated at */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]120
121asm_dram_init:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]122 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]123
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]124#ifdef CONFIG_SYS_NAND_BOOT
125 /* for assembly stack */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]126 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]127 movec %d0, %RAMBAR1
128
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]129 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]130 clr.l %sp@-
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]131#endif
132
133#ifdef CONFIG_CF_SBF
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]134 move.l #CFG_SYS_INIT_RAM_ADDR, %d0
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]135 movec %d0, %VBR
136
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]137 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]138 movec %d0, %RAMBAR1
139
140 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]141 move.l #0, %d0
142 move.l #(ICACHE_STATUS), %a1 /* icache */
143 move.l #(DCACHE_STATUS), %a2 /* dcache */
144 move.l %d0, (%a1)
145 move.l %d0, (%a2)
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]146
147 /* invalidate and disable cache */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]148 move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]149 movec %d0, %CACR /* Invalidate cache */
150 move.l #0, %d0
151 movec %d0, %ACR0
152 movec %d0, %ACR1
153 movec %d0, %ACR2
154 movec %d0, %ACR3
155
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]156 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]157 clr.l %sp@-
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]158
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]159#ifdef CFG_SYS_CS0_BASE
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]160 /* Must disable global address */
161 move.l #0xFC008000, %a1
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]162 move.l #(CFG_SYS_CS0_BASE), (%a1)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]163 move.l #0xFC008008, %a1
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]164 move.l #(CFG_SYS_CS0_CTRL), (%a1)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]165 move.l #0xFC008004, %a1
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]166 move.l #(CFG_SYS_CS0_MASK), (%a1)
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]167#endif
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]168#endif /* CONFIG_CF_SBF */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]169
170#ifdef CONFIG_MCF5441x
171 /* TC: enable all peripherals,
172 in the future only enable certain peripherals */
173 move.l #0xFC04002D, %a1
174
175#if defined(CONFIG_CF_SBF)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]176 move.b #23, (%a1) /* dspi */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]177#endif
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]178#endif /* CONFIG_MCF5441x */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]179
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]180 /* mandatory board level ddr-sdram init,
181 * for both 5441x and 5445x
182 */
183 bsr sbf_dram_init
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]184
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]185#ifdef CONFIG_CF_SBF
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]186 /*
187 * DSPI Initialization
188 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
189 * a1 - dspi status
190 * a2 - dtfr
191 * a3 - drfr
192 * a4 - Dst addr
193 */
194 /* Enable pins for DSPI mode - chip-selects are enabled later */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]195asm_dspi_init:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]196#ifdef CONFIG_MCF5441x
197 move.l #0xEC09404E, %a1
198 move.l #0xEC09404F, %a2
199 move.b #0xFF, (%a1)
200 move.b #0x80, (%a2)
201#endif
202
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]203 /* Configure DSPI module */
204 move.l #0xFC05C000, %a0
205 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
206
207 move.l #0xFC05C00C, %a0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]208#ifdef CONFIG_MCF5441x
209 move.l #0x3E000016, (%a0)
210#endif
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]211
212 move.l #0xFC05C034, %a2 /* dtfr */
213 move.l #0xFC05C03B, %a3 /* drfr */
214
215 move.l #(ASM_SBF_IMG_HDR + 4), %a1
216 move.l (%a1)+, %d5
217 move.l (%a1), %a4
218
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]219 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_SBFHDR_DATA_OFFSET), %a0
220 move.l #(CFG_SYS_SBFHDR_SIZE), %d4
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]221
222 move.l #0xFC05C02C, %a1 /* dspi status */
223
224 /* Issue commands and address */
225 move.l #0x8002000B, %d2 /* Fast Read Cmd */
226 jsr asm_dspi_wr_status
227 jsr asm_dspi_rd_status
228
229 move.l #0x80020000, %d2 /* Address byte 2 */
230 jsr asm_dspi_wr_status
231 jsr asm_dspi_rd_status
232
233 move.l #0x80020000, %d2 /* Address byte 1 */
234 jsr asm_dspi_wr_status
235 jsr asm_dspi_rd_status
236
237 move.l #0x80020000, %d2 /* Address byte 0 */
238 jsr asm_dspi_wr_status
239 jsr asm_dspi_rd_status
240
241 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
242 jsr asm_dspi_wr_status
243 jsr asm_dspi_rd_status
244
245 /* Transfer serial boot header to sram */
246asm_dspi_rd_loop1:
247 move.l #0x80020000, %d2
248 jsr asm_dspi_wr_status
249 jsr asm_dspi_rd_status
250
251 move.b %d1, (%a0) /* read, copy to dst */
252
253 add.l #1, %a0 /* inc dst by 1 */
254 sub.l #1, %d4 /* dec cnt by 1 */
255 bne asm_dspi_rd_loop1
256
257 /* Transfer u-boot from serial flash to memory */
258asm_dspi_rd_loop2:
259 move.l #0x80020000, %d2
260 jsr asm_dspi_wr_status
261 jsr asm_dspi_rd_status
262
263 move.b %d1, (%a4) /* read, copy to dst */
264
265 add.l #1, %a4 /* inc dst by 1 */
266 sub.l #1, %d5 /* dec cnt by 1 */
267 bne asm_dspi_rd_loop2
268
269 move.l #0x00020000, %d2 /* Terminate */
270 jsr asm_dspi_wr_status
271 jsr asm_dspi_rd_status
272
273 /* jump to memory and execute */
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]274 move.l #(CONFIG_TEXT_BASE + 0x400), %a0
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]275 jmp (%a0)
276
277asm_dspi_wr_status:
278 move.l (%a1), %d0 /* status */
279 and.l #0x0000F000, %d0
280 cmp.l #0x00003000, %d0
281 bgt asm_dspi_wr_status
282
283 move.l %d2, (%a2)
284 rts
285
286asm_dspi_rd_status:
287 move.l (%a1), %d0 /* status */
288 and.l #0x000000F0, %d0
289 lsr.l #4, %d0
290 cmp.l #0, %d0
291 beq asm_dspi_rd_status
292
293 move.b (%a3), %d1
294 rts
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]295#endif /* CONFIG_CF_SBF */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]296
297#ifdef CONFIG_SYS_NAND_BOOT
298 /* copy 4 boot pages to dram as soon as possible */
299 /* each page is 996 bytes (1056 total with 60 ECC bytes */
300 move.l #0x00000000, %a1 /* src */
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]301 move.l #CONFIG_TEXT_BASE, %a2 /* dst */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]302 move.l #0x3E0, %d0 /* sz in long */
303
304asm_boot_nand_copy:
305 move.l (%a1)+, (%a2)+
306 subq.l #1, %d0
307 bne asm_boot_nand_copy
308
309 /* jump to memory and execute */
310 move.l #(asm_nand_init), %a0
311 jmp (%a0)
312
313asm_nand_init:
314 /* exit nand boot-mode */
315 move.l #0xFC0FFF30, %a1
316 or.l #0x00000040, %d1
317 move.l %d1, (%a1)
318
319 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]320 move.l #0, %d0
321 move.l #(CACR_STATUS), %a1 /* CACR */
322 move.l #(ICACHE_STATUS), %a2 /* icache */
323 move.l #(DCACHE_STATUS), %a3 /* dcache */
324 move.l %d0, (%a1)
325 move.l %d0, (%a2)
326 move.l %d0, (%a3)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]327
328 /* invalidate and disable cache */
329 move.l #0x01004100, %d0 /* Invalidate cache cmd */
330 movec %d0, %CACR /* Invalidate cache */
331 move.l #0, %d0
332 movec %d0, %ACR0
333 movec %d0, %ACR1
334 movec %d0, %ACR2
335 movec %d0, %ACR3
336
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]337#ifdef CFG_SYS_CS0_BASE
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]338 /* Must disable global address */
339 move.l #0xFC008000, %a1
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]340 move.l #(CFG_SYS_CS0_BASE), (%a1)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]341 move.l #0xFC008008, %a1
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]342 move.l #(CFG_SYS_CS0_CTRL), (%a1)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]343 move.l #0xFC008004, %a1
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]344 move.l #(CFG_SYS_CS0_MASK), (%a1)
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]345#endif
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]346
347 /* NAND port configuration */
348 move.l #0xEC094048, %a1
349 move.b #0xFD, (%a1)+
350 move.b #0x5F, (%a1)+
351 move.b #0x04, (%a1)+
352
353 /* reset nand */
354 move.l #0xFC0FFF38, %a1 /* isr */
355 move.l #0x000e0000, (%a1)
356 move.l #0xFC0FFF08, %a2
357 move.l #0x00000000, (%a2)+ /* car */
358 move.l #0x11000000, (%a2)+ /* rar */
359 move.l #0x00000000, (%a2)+ /* rpt */
360 move.l #0x00000000, (%a2)+ /* rai */
361 move.l #0xFC0FFF2c, %a2 /* cfg */
362 move.l #0x00000000, (%a2)+ /* secsz */
363 move.l #0x000e0681, (%a2)+
364 move.l #0xFC0FFF04, %a2 /* cmd2 */
365 move.l #0xFF404001, (%a2)
366 move.l #0x000e0000, (%a1)
367
368 move.l #0x2000, %d1
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]369 bsr asm_delay
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]370
371 /* setup nand */
372 move.l #0xFC0FFF00, %a1
373 move.l #0x30700000, (%a1)+ /* cmd1 */
374 move.l #0x007EF000, (%a1)+ /* cmd2 */
375
376 move.l #0xFC0FFF2C, %a1
377 move.l #0x00000841, (%a1)+ /* secsz */
378 move.l #0x000e0681, (%a1)+ /* cfg */
379
380 move.l #100, %d4 /* 100 pages ~200KB */
381 move.l #4, %d2 /* start at 4 */
382 move.l #0xFC0FFF04, %a0 /* cmd2 */
383 move.l #0xFC0FFF0C, %a1 /* rar */
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]384 move.l #(CONFIG_TEXT_BASE + 0xF80), %a2
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]385
386asm_nand_read:
387 move.l #0x11000000, %d0 /* rar */
388 or.l %d2, %d0
389 move.l %d0, (%a1)
390 add.l #1, %d2
391
392 move.l (%a0), %d0 /* cmd2 */
393 or.l #1, %d0
394 move.l %d0, (%a0)
395
396 move.l #0x200, %d1
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]397 bsr asm_delay
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]398
399asm_nand_chk_status:
400 move.l #0xFC0FFF38, %a4 /* isr */
401 move.l (%a4), %d0
402 and.l #0x40000000, %d0
403 tst.l %d0
404 beq asm_nand_chk_status
405
406 move.l #0xFC0FFF38, %a4 /* isr */
407 move.l (%a4), %d0
408 or.l #0x000E0000, %d0
409 move.l %d0, (%a4)
410
411 move.l #0x200, %d3
412 move.l #0xFC0FC000, %a3 /* buf 1 */
413asm_nand_copy:
414 move.l (%a3)+, (%a2)+
415 subq.l #1, %d3
416 bgt asm_nand_copy
417
418 subq.l #1, %d4
419 bgt asm_nand_read
420
421 /* jump to memory and execute */
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]422 move.l #(CONFIG_TEXT_BASE + 0x400), %a0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]423 jmp (%a0)
424
425#endif /* CONFIG_SYS_NAND_BOOT */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]426
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]427.globl asm_delay
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]428asm_delay:
429 nop
430 subq.l #1, %d1
431 bne asm_delay
432 rts
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]433#endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]434
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]435.text
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]436 . = 0x400
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]437.globl _start
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]438_start:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]439#if !defined(CONFIG_SERIAL_BOOT)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]440 nop
441 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]442 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]443
444 /* Set vector base register at the beginning of the Flash */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]445 move.l #CFG_SYS_FLASH_BASE, %d0
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]446 movec %d0, %VBR
447
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]448 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew0573a7a2007-11-07 18:00:54 -0600[diff] [blame]449 movec %d0, %RAMBAR1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]450
451 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]452 move.l #0, %d0
453 move.l #(ICACHE_STATUS), %a1 /* icache */
454 move.l #(DCACHE_STATUS), %a2 /* dcache */
455 move.l %d0, (%a1)
456 move.l %d0, (%a2)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]457
458 /* invalidate and disable cache */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]459 move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]460 movec %d0, %CACR /* Invalidate cache */
461 move.l #0, %d0
462 movec %d0, %ACR0
463 movec %d0, %ACR1
464 movec %d0, %ACR2
465 movec %d0, %ACR3
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]466#else
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]467 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]468 movec %d0, %RAMBAR1
469#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]470
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]471 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]472 move.l #__got_start, %a5
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]473
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]474 /* setup stack initially on top of internal static ram */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]475 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]476
477 /*
478 * if configured, malloc_f arena will be reserved first,
479 * then (and always) gd struct space will be reserved
480 */
481 move.l %sp, -(%sp)
482 move.l #board_init_f_alloc_reserve, %a1
483 jsr (%a1)
484
485 /* update stack and frame-pointers */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]486 move.l %d0, %sp
487 move.l %sp, %fp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]488
489 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]490 move.l %d0, -(%sp)
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]491 move.l #board_init_f_init_reserve, %a1
492 jsr (%a1)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]493
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]494 /* run low-level CPU init code (from flash) */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]495 move.l #cpu_init_f, %a1
496 jsr (%a1)
497
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]498 /* run low-level board init code (from flash) */
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]499 clr.l %sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]500 move.l #board_init_f, %a1
501 jsr (%a1)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]502
503 /* board_init_f() does not return */
504
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]505/******************************************************************************/
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]506
507/*
Simon Glass284f71b2019-12-28 10:44:45 -0700[diff] [blame]508 * void relocate_code(addr_sp, gd, addr_moni)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]509 *
510 * This "function" does not return, instead it continues in RAM
511 * after relocating the monitor code.
512 *
513 * r3 = dest
514 * r4 = src
515 * r5 = length in bytes
516 * r6 = cachelinesize
517 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]518.globl relocate_code
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]519relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]520 link.w %a6,#0
521 move.l 8(%a6), %sp /* set new stack pointer */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]522
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]523 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
524 move.l 16(%a6), %a0 /* Save copy of Destination Address */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]525
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]526 move.l #CONFIG_SYS_MONITOR_BASE, %a1
527 move.l #__init_end, %a2
528 move.l %a0, %a3
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]529
530 /* copy the code to RAM */
5311:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]532 move.l (%a1)+, (%a3)+
533 cmp.l %a1,%a2
534 bgt.s 1b
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]535
Marek Vasut549651f2023-08-27 00:25:36 +0200[diff] [blame^]536#define R_68K_32 1
537#define R_68K_RELATIVE 22
538
539 move.l #(__rel_dyn_start), %a1
540 move.l #(__rel_dyn_end), %a2
541
542fixloop:
543 move.l (%a1)+, %d1 /* Elf32_Rela r_offset */
544 move.l (%a1)+, %d2 /* Elf32_Rela r_info */
545 move.l (%a1)+, %d3 /* Elf32_Rela r_addend */
546
547 andi.l #0xff, %d2
548 cmp.l #R_68K_32, %d2
549 beq.s fixup
550 cmp.l #R_68K_RELATIVE, %d2
551 beq.s fixup
552
553 bra fixnext
554
555fixup:
556 /* relative fix: store addend plus offset at dest location */
557 move.l %a0, %a3
558 add.l %d1, %a3
559 sub.l #CONFIG_SYS_MONITOR_BASE, %a3
560 move.l (%a3), %d4
561 add.l %a0, %d4
562 sub.l #CONFIG_SYS_MONITOR_BASE, %d4
563 move.l %d4, (%a3)
564
565fixnext:
566 cmp.l %a1, %a2
567 bge.s fixloop
568
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]569/*
570 * We are done. Do not return, instead branch to second part of board
571 * initialization, now running from RAM.
572 */
573 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]574 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]575 jmp (%a1)
576
577in_ram:
578
579clear_bss:
580 /*
581 * Now clear BSS segment
582 */
Marek Vasut549651f2023-08-27 00:25:36 +0200[diff] [blame^]583 move.l #(_sbss), %a1
584 move.l #(_ebss), %d1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]5856:
586 clr.l (%a1)+
587 cmp.l %a1,%d1
588 bgt.s 6b
589
590 /*
591 * fix got table in RAM
592 */
Marek Vasut549651f2023-08-27 00:25:36 +0200[diff] [blame^]593 move.l #(__got_start), %a5 /* fix got pointer register a5 */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]594
595 /* calculate relative jump to board_init_r in ram */
Marek Vasut549651f2023-08-27 00:25:36 +0200[diff] [blame^]596 move.l #(board_init_r), %a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]597
598 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]599 move.l %a0,-(%sp) /* dest_addr */
600 move.l %d0,-(%sp) /* gd */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]601 jsr (%a1)
602
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]603/******************************************************************************/
604
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]605/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]606.globl _fault
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]607_fault:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]608 bra _fault
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]609
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]610.globl _exc_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]611_exc_handler:
612 SAVE_ALL
613 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]614 bsr exc_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]615 addql #4,%sp
616 RESTORE_ALL
617
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]618.globl _int_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]619_int_handler:
620 SAVE_ALL
621 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]622 bsr int_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]623 addql #4,%sp
624 RESTORE_ALL
625
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]626/******************************************************************************/
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]627
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]628.align 4