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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk9c53f402003-10-15 23:53:47 +00002/*
Dipen Dudhat5d51bf92011-01-19 12:46:27 +05303 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
wdenk9c53f402003-10-15 23:53:47 +00004 * (C) Copyright 2002, 2003 Motorola Inc.
5 * Xianghua Xiao (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk9c53f402003-10-15 23:53:47 +00009 */
10
Andy Flemingfecff2b2008-08-31 16:33:26 -050011#include <config.h>
Simon Glass970b61e2019-11-14 12:57:09 -070012#include <cpu_func.h>
Tom Rinif7246c22021-08-21 13:50:17 -040013#include <clock_legacy.h>
Simon Glass1ab16922022-07-31 12:28:48 -060014#include <display_options.h>
Simon Glass97589732020-05-10 11:40:02 -060015#include <init.h>
Simon Glass8f3f7612019-11-14 12:57:42 -070016#include <irq_func.h>
Simon Glass0f2af882020-05-10 11:40:05 -060017#include <log.h>
Simon Glassa9dc0682019-12-28 10:44:59 -070018#include <time.h>
Simon Glassf5c208d2019-11-14 12:57:20 -070019#include <vsprintf.h>
wdenk9c53f402003-10-15 23:53:47 +000020#include <watchdog.h>
21#include <command.h>
Andy Fleming6843a6e2008-10-30 16:51:33 -050022#include <fsl_esdhc.h>
wdenk9c53f402003-10-15 23:53:47 +000023#include <asm/cache.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060024#include <asm/global_data.h>
Sergei Poselenovddc1a472008-06-06 15:42:40 +020025#include <asm/io.h>
Becky Bruceee888da2010-06-17 11:37:25 -050026#include <asm/mmu.h>
York Sun37562f62013-10-22 12:39:02 -070027#include <fsl_ifc.h>
Becky Bruceee888da2010-06-17 11:37:25 -050028#include <asm/fsl_law.h>
Becky Bruce5e35d8a2010-12-17 17:17:56 -060029#include <asm/fsl_lbc.h>
York Sunc41b7442010-09-28 15:20:33 -070030#include <post.h>
31#include <asm/processor.h>
York Sunf0626592013-09-30 09:22:09 -070032#include <fsl_ddr_sdram.h>
Christophe Leroy31f6e932017-07-13 15:09:54 +020033#include <asm/ppc.h>
Simon Glassdbd79542020-05-10 11:40:11 -060034#include <linux/delay.h>
wdenk9c53f402003-10-15 23:53:47 +000035
James Yang957b1912008-02-08 16:44:53 -060036DECLARE_GLOBAL_DATA_PTR;
37
Ira W. Snydera85994c2011-11-21 13:20:32 -080038/*
39 * Default board reset function
40 */
41static void
42__board_reset(void)
43{
44 /* Do nothing */
45}
Pali Rohár779f6522022-08-01 15:31:46 +020046void board_reset_prepare(void) __attribute__((weak, alias("__board_reset")));
Ira W. Snydera85994c2011-11-21 13:20:32 -080047void board_reset(void) __attribute__((weak, alias("__board_reset")));
Pali Rohárc13f4fb2022-08-01 15:31:45 +020048void board_reset_last(void) __attribute__((weak, alias("__board_reset")));
Ira W. Snydera85994c2011-11-21 13:20:32 -080049
wdenk9c53f402003-10-15 23:53:47 +000050int checkcpu (void)
51{
wdenka445ddf2004-06-09 00:34:46 +000052 sys_info_t sysinfo;
wdenka445ddf2004-06-09 00:34:46 +000053 uint pvr, svr;
54 uint ver;
55 uint major, minor;
Kumar Gala8ddf00c2008-06-10 16:53:46 -050056 struct cpu_type *cpu;
Wolfgang Denk20591042008-10-19 02:35:49 +020057 char buf1[32], buf2[32];
Tom Rinif7246c22021-08-21 13:50:17 -040058#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
59 defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
York Sunc87e81e2013-06-25 11:37:43 -070060 ccsr_gur_t __iomem *gur =
Tom Rinid5c3bf22022-10-28 20:27:12 -040061 (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
York Sunc87e81e2013-06-25 11:37:43 -070062#endif
York Sun3b5179f2012-10-08 07:44:31 +000063
64 /*
65 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
66 * mode. Previous platform use ddr ratio to do the same. This
67 * information is only for display here.
68 */
Kumar Galadccd9e32009-03-19 02:46:19 -050069#ifdef CONFIG_FSL_CORENET
York Sun383f6f62012-10-08 07:44:16 +000070#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
York Sun3b5179f2012-10-08 07:44:31 +000071 u32 ddr_sync = 0; /* only async mode is supported */
York Sun383f6f62012-10-08 07:44:16 +000072#else
York Sun3b5179f2012-10-08 07:44:31 +000073 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
Srikanth Srinivasanf58c2a42010-02-10 17:32:43 +080074 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
York Sun383f6f62012-10-08 07:44:16 +000075#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
York Sun3b5179f2012-10-08 07:44:31 +000076#else /* CONFIG_FSL_CORENET */
Tom Rinif7246c22021-08-21 13:50:17 -040077#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
York Sun3b5179f2012-10-08 07:44:31 +000078 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
79 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
Kumar Gala54b68102008-05-29 01:21:24 -050080#else
81 u32 ddr_ratio = 0;
Tom Rinif7246c22021-08-21 13:50:17 -040082#endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */
York Sun3b5179f2012-10-08 07:44:31 +000083#endif /* CONFIG_FSL_CORENET */
84
Timur Tabi47289422011-08-05 16:15:24 -050085 unsigned int i, core, nr_cores = cpu_numcores();
86 u32 mask = cpu_mask();
wdenk9c53f402003-10-15 23:53:47 +000087
Shaveta Leekhadbf0bc82015-01-19 12:46:54 +053088#ifdef CONFIG_HETROGENOUS_CLUSTERS
89 unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
90 u32 dsp_mask = cpu_dsp_mask();
91#endif
92
wdenka445ddf2004-06-09 00:34:46 +000093 svr = get_svr();
wdenka445ddf2004-06-09 00:34:46 +000094 major = SVR_MAJ(svr);
95 minor = SVR_MIN(svr);
96
Shengzhou Liu26ed2d02014-04-25 16:31:22 +080097#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
98 if (SVR_SOC_VER(svr) == SVR_T4080) {
99 ccsr_rcpm_t *rcpm =
Tom Rini376b88a2022-10-28 20:27:13 -0400100 (void __iomem *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
Shengzhou Liu26ed2d02014-04-25 16:31:22 +0800101
102 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
103 FSL_CORENET_DEVDISR2_DTSEC1_9);
104 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
105 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
106
107 /* It needs SW to disable core4~7 as HW design sake on T4080 */
108 for (i = 4; i < 8; i++)
109 cpu_disable(i);
110
111 /* request core4~7 into PH20 state, prior to entering PCL10
112 * state, all cores in cluster should be placed in PH20 state.
113 */
114 setbits_be32(&rcpm->pcph20setr, 0xf0);
115
116 /* put the 2nd cluster into PCL10 state */
117 setbits_be32(&rcpm->clpcl10setr, 1 << 1);
118 }
119#endif
120
Poonam Aggrwal4baef822009-07-31 12:08:14 +0530121 if (cpu_numcores() > 1) {
Poonam Aggrwal36a68432009-09-03 19:42:40 +0530122#ifndef CONFIG_MP
123 puts("Unicore software on multiprocessor system!!\n"
124 "To enable mutlticore build define CONFIG_MP\n");
125#endif
Tom Rinid5c3bf22022-10-28 20:27:12 -0400126 volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
Poonam Aggrwal4baef822009-07-31 12:08:14 +0530127 printf("CPU%d: ", pic->whoami);
128 } else {
129 puts("CPU: ");
130 }
Andy Flemingf5740972008-02-06 01:19:40 -0600131
Simon Glassa8b57392012-12-13 20:48:48 +0000132 cpu = gd->arch.cpu;
Andy Flemingf5740972008-02-06 01:19:40 -0600133
Poonam Aggrwalda6e1ca2009-09-02 13:35:21 +0530134 puts(cpu->name);
135 if (IS_E_PROCESSOR(svr))
136 puts("E");
Andy Flemingf5740972008-02-06 01:19:40 -0600137
wdenka445ddf2004-06-09 00:34:46 +0000138 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
wdenk9c53f402003-10-15 23:53:47 +0000139
wdenk3f3262b2005-03-15 22:56:53 +0000140 pvr = get_pvr();
141 ver = PVR_VER(pvr);
142 major = PVR_MAJ(pvr);
143 minor = PVR_MIN(pvr);
144
145 printf("Core: ");
Kumar Galae222ed32011-07-25 09:28:39 -0500146 switch(ver) {
147 case PVR_VER_E500_V1:
Pali Rohár62923c62022-04-03 00:05:10 +0200148 puts("e500v1");
149 break;
Kumar Galae222ed32011-07-25 09:28:39 -0500150 case PVR_VER_E500_V2:
Pali Rohár62923c62022-04-03 00:05:10 +0200151 puts("e500v2");
Kumar Galae222ed32011-07-25 09:28:39 -0500152 break;
153 case PVR_VER_E500MC:
Fabio Estevamf4c557c2013-04-21 13:11:02 -0300154 puts("e500mc");
Kumar Galae222ed32011-07-25 09:28:39 -0500155 break;
156 case PVR_VER_E5500:
Fabio Estevamf4c557c2013-04-21 13:11:02 -0300157 puts("e5500");
Kumar Galae222ed32011-07-25 09:28:39 -0500158 break;
Kumar Galac1abf4a2012-08-17 08:20:23 +0000159 case PVR_VER_E6500:
Fabio Estevamf4c557c2013-04-21 13:11:02 -0300160 puts("e6500");
Kumar Galac1abf4a2012-08-17 08:20:23 +0000161 break;
Kumar Galae222ed32011-07-25 09:28:39 -0500162 default:
Kumar Galabd2985c2009-10-21 13:23:54 -0500163 puts("Unknown");
Kumar Galae222ed32011-07-25 09:28:39 -0500164 break;
wdenk3f3262b2005-03-15 22:56:53 +0000165 }
Kumar Gala9f4a6892008-10-23 01:47:38 -0500166
wdenk3f3262b2005-03-15 22:56:53 +0000167 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
168
York Sun908412d2012-10-08 07:44:10 +0000169 if (nr_cores > CONFIG_MAX_CPUS) {
170 panic("\nUnexpected number of cores: %d, max is %d\n",
171 nr_cores, CONFIG_MAX_CPUS);
172 }
173
wdenka445ddf2004-06-09 00:34:46 +0000174 get_sys_info(&sysinfo);
175
vijay raid84fd502014-04-15 11:34:12 +0530176#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
177 if (sysinfo.diff_sysclk == 1)
178 puts("Single Source Clock Configuration\n");
179#endif
180
Kumar Galaf92794c2009-02-04 09:35:57 -0600181 puts("Clock Configuration:");
Timur Tabi47289422011-08-05 16:15:24 -0500182 for_each_cpu(i, core, nr_cores, mask) {
Wolfgang Denk1f79d142009-02-19 00:41:08 +0100183 if (!(i & 3))
184 printf ("\n ");
Timur Tabi47289422011-08-05 16:15:24 -0500185 printf("CPU%d:%-4s MHz, ", core,
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530186 strmhz(buf1, sysinfo.freq_processor[core]));
Kumar Galaf92794c2009-02-04 09:35:57 -0600187 }
Shaveta Leekhadbf0bc82015-01-19 12:46:54 +0530188
189#ifdef CONFIG_HETROGENOUS_CLUSTERS
190 for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
191 if (!(j & 3))
192 printf("\n ");
193 printf("DSP CPU%d:%-4s MHz, ", j,
194 strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
195 }
196#endif
197
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530198 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
199 printf("\n");
Kumar Gala54b68102008-05-29 01:21:24 -0500200
Kumar Galadccd9e32009-03-19 02:46:19 -0500201#ifdef CONFIG_FSL_CORENET
202 if (ddr_sync == 1) {
203 printf(" DDR:%-4s MHz (%s MT/s data rate) "
204 "(Synchronous), ",
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530205 strmhz(buf1, sysinfo.freq_ddrbus/2),
206 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Galadccd9e32009-03-19 02:46:19 -0500207 } else {
208 printf(" DDR:%-4s MHz (%s MT/s data rate) "
209 "(Asynchronous), ",
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530210 strmhz(buf1, sysinfo.freq_ddrbus/2),
211 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Galadccd9e32009-03-19 02:46:19 -0500212 }
213#else
Kumar Gala07db1702007-12-07 04:59:26 -0600214 switch (ddr_ratio) {
215 case 0x0:
Wolfgang Denk20591042008-10-19 02:35:49 +0200216 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530217 strmhz(buf1, sysinfo.freq_ddrbus/2),
218 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Gala07db1702007-12-07 04:59:26 -0600219 break;
220 case 0x7:
Kumar Galadccd9e32009-03-19 02:46:19 -0500221 printf(" DDR:%-4s MHz (%s MT/s data rate) "
222 "(Synchronous), ",
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530223 strmhz(buf1, sysinfo.freq_ddrbus/2),
224 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Gala07db1702007-12-07 04:59:26 -0600225 break;
226 default:
Kumar Galadccd9e32009-03-19 02:46:19 -0500227 printf(" DDR:%-4s MHz (%s MT/s data rate) "
228 "(Asynchronous), ",
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530229 strmhz(buf1, sysinfo.freq_ddrbus/2),
230 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Gala07db1702007-12-07 04:59:26 -0600231 break;
232 }
Kumar Galadccd9e32009-03-19 02:46:19 -0500233#endif
wdenka445ddf2004-06-09 00:34:46 +0000234
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530235#if defined(CONFIG_FSL_LBC)
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530236 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
237 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
Kumar Galadccd9e32009-03-19 02:46:19 -0500238 } else {
Trent Piepho0b691fc2008-12-03 15:16:37 -0800239 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530240 sysinfo.freq_localbus);
Kumar Galadccd9e32009-03-19 02:46:19 -0500241 }
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530242#endif
wdenka445ddf2004-06-09 00:34:46 +0000243
Kumar Gala17ec6fa2012-10-08 07:44:06 +0000244#if defined(CONFIG_FSL_IFC)
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530245 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
Kumar Gala17ec6fa2012-10-08 07:44:06 +0000246#endif
247
Haiying Wang61414682009-05-20 12:30:29 -0400248#ifdef CONFIG_QE
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530249 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
Haiying Wang61414682009-05-20 12:30:29 -0400250#endif
251
Shaveta Leekhadbf0bc82015-01-19 12:46:54 +0530252#if defined(CONFIG_SYS_CPRI)
253 printf(" ");
254 printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
255#endif
256
257#if defined(CONFIG_SYS_MAPLE)
258 printf("\n ");
259 printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
260 printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
261 printf("MAPLE-eTVPE:%-4s MHz\n",
262 strmhz(buf1, sysinfo.freq_maple_etvpe));
263#endif
264
Kumar Galadccd9e32009-03-19 02:46:19 -0500265#ifdef CONFIG_SYS_DPAA_FMAN
Tom Rini0a2bac72022-11-16 13:10:29 -0500266 for (i = 0; i < CFG_SYS_NUM_FMAN; i++) {
Emil Medve3a9ed2f2010-06-17 00:08:29 -0500267 printf(" FMAN%d: %s MHz\n", i + 1,
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530268 strmhz(buf1, sysinfo.freq_fman[i]));
Kumar Galadccd9e32009-03-19 02:46:19 -0500269 }
270#endif
271
Haiying Wang09d0aa92012-10-11 07:13:39 +0000272#ifdef CONFIG_SYS_DPAA_QBMAN
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530273 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
Haiying Wang09d0aa92012-10-11 07:13:39 +0000274#endif
275
Kumar Galadccd9e32009-03-19 02:46:19 -0500276#ifdef CONFIG_SYS_DPAA_PME
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530277 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
Kumar Galadccd9e32009-03-19 02:46:19 -0500278#endif
279
Shruti Kanetkar81159362013-08-15 11:25:38 -0500280 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
wdenk9c53f402003-10-15 23:53:47 +0000281
York Sunc87e81e2013-06-25 11:37:43 -0700282#ifdef CONFIG_FSL_CORENET
283 /* Display the RCW, so that no one gets confused as to what RCW
284 * we're actually using for this boot.
285 */
286 puts("Reset Configuration Word (RCW):");
287 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
288 u32 rcw = in_be32(&gur->rcwsr[i]);
289
290 if ((i % 4) == 0)
291 printf("\n %08x:", i * 4);
292 printf(" %08x", rcw);
293 }
294 puts("\n");
295#endif
296
wdenk9c53f402003-10-15 23:53:47 +0000297 return 0;
298}
299
300
301/* ------------------------------------------------------------------------- */
302
Simon Glassed38aef2020-05-10 11:40:03 -0600303int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
wdenk9c53f402003-10-15 23:53:47 +0000304{
Kumar Galaaff01532009-09-08 13:46:46 -0500305/* Everything after the first generation of PQ3 parts has RSTCR */
Tom Rini0b730a02021-05-14 21:34:21 -0400306#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
Sergei Poselenov25147422008-05-08 14:17:08 +0200307 unsigned long val, msr;
308
wdenk9c53f402003-10-15 23:53:47 +0000309 /*
310 * Initiate hard reset in debug control register DBCR0
Kumar Galaaff01532009-09-08 13:46:46 -0500311 * Make sure MSR[DE] = 1. This only resets the core.
wdenk9c53f402003-10-15 23:53:47 +0000312 */
Sergei Poselenov25147422008-05-08 14:17:08 +0200313 msr = mfmsr ();
314 msr |= MSR_DE;
315 mtmsr (msr);
urwithsughosh@gmail.com06c2fb92007-09-24 13:32:13 -0400316
Sergei Poselenov25147422008-05-08 14:17:08 +0200317 val = mfspr(DBCR0);
318 val |= 0x70000000;
319 mtspr(DBCR0,val);
Kumar Galaaff01532009-09-08 13:46:46 -0500320#else
Tom Rinid5c3bf22022-10-28 20:27:12 -0400321 volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
Ira W. Snydera85994c2011-11-21 13:20:32 -0800322
Pali Rohár779f6522022-08-01 15:31:46 +0200323 /* Call board-specific preparation for reset */
324 board_reset_prepare();
325
Ira W. Snydera85994c2011-11-21 13:20:32 -0800326 /* Attempt board-specific reset */
327 board_reset();
328
329 /* Next try asserting HRESET_REQ */
330 out_be32(&gur->rstcr, 0x2);
Kumar Galaaff01532009-09-08 13:46:46 -0500331 udelay(100);
Pali Rohárc13f4fb2022-08-01 15:31:45 +0200332
333 /* Attempt last-stage board-specific reset */
334 board_reset_last();
Kumar Galaaff01532009-09-08 13:46:46 -0500335#endif
Sergei Poselenov25147422008-05-08 14:17:08 +0200336
wdenk9c53f402003-10-15 23:53:47 +0000337 return 1;
338}
339
340
341/*
342 * Get timebase clock frequency
343 */
Simon Glassa9dc0682019-12-28 10:44:59 -0700344__weak unsigned long get_tbclk(void)
wdenk9c53f402003-10-15 23:53:47 +0000345{
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600346 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
347
348 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
wdenk9c53f402003-10-15 23:53:47 +0000349}
350
351
Pali Rohárf6ac14e2022-04-28 13:31:43 +0200352#ifndef CONFIG_WDT
wdenk9c53f402003-10-15 23:53:47 +0000353#if defined(CONFIG_WATCHDOG)
Boschung, Rainerf63c0dc12014-06-03 09:05:14 +0200354#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
355void
356init_85xx_watchdog(void)
357{
358 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
Tom Rinid1d74ab2022-12-04 10:14:06 -0500359 TCR_WP(CFG_WATCHDOG_PRESC) | TCR_WRC(CFG_WATCHDOG_RC));
Boschung, Rainerf63c0dc12014-06-03 09:05:14 +0200360}
361
wdenk9c53f402003-10-15 23:53:47 +0000362void
wdenk9c53f402003-10-15 23:53:47 +0000363reset_85xx_watchdog(void)
364{
365 /*
366 * Clear TSR(WIS) bit by writing 1
367 */
Mark Marshall10b13c92012-09-09 23:06:03 +0000368 mtspr(SPRN_TSR, TSR_WIS);
wdenk9c53f402003-10-15 23:53:47 +0000369}
Horst Kronstorferf70831e2013-03-13 10:14:05 +0000370
371void
372watchdog_reset(void)
373{
374 int re_enable = disable_interrupts();
375
376 reset_85xx_watchdog();
377 if (re_enable)
378 enable_interrupts();
379}
wdenk9c53f402003-10-15 23:53:47 +0000380#endif /* CONFIG_WATCHDOG */
Pali Rohárf6ac14e2022-04-28 13:31:43 +0200381#endif
wdenk9c53f402003-10-15 23:53:47 +0000382
Sergei Poselenovddc1a472008-06-06 15:42:40 +0200383/*
Andy Fleming6843a6e2008-10-30 16:51:33 -0500384 * Initializes on-chip MMC controllers.
385 * to override, implement board_mmc_init()
386 */
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900387int cpu_mmc_init(struct bd_info *bis)
Andy Fleming6843a6e2008-10-30 16:51:33 -0500388{
389#ifdef CONFIG_FSL_ESDHC
390 return fsl_esdhc_mmc_init(bis);
391#else
392 return 0;
393#endif
394}
Becky Bruceee888da2010-06-17 11:37:25 -0500395
396/*
397 * Print out the state of various machine registers.
Dipen Dudhat00c42942011-01-20 16:29:35 +0530398 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
399 * parameters for IFC and TLBs
Becky Bruceee888da2010-06-17 11:37:25 -0500400 */
Christophe Leroy31f6e932017-07-13 15:09:54 +0200401void print_reginfo(void)
Becky Bruceee888da2010-06-17 11:37:25 -0500402{
403 print_tlbcam();
Bin Mengc39f3402021-02-25 17:22:27 +0800404#ifdef CONFIG_FSL_LAW
Becky Bruceee888da2010-06-17 11:37:25 -0500405 print_laws();
Bin Mengc39f3402021-02-25 17:22:27 +0800406#endif
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530407#if defined(CONFIG_FSL_LBC)
Becky Bruceee888da2010-06-17 11:37:25 -0500408 print_lbc_regs();
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530409#endif
Dipen Dudhat00c42942011-01-20 16:29:35 +0530410#ifdef CONFIG_FSL_IFC
411 print_ifc_regs();
412#endif
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530413
Becky Bruceee888da2010-06-17 11:37:25 -0500414}
York Sunc41b7442010-09-28 15:20:33 -0700415
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600416/* Common ddr init for non-corenet fsl 85xx platforms */
417#ifndef CONFIG_FSL_CORENET
Scott Wood095b7122012-09-20 19:02:18 -0500418#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
Tom Rini6a5dccc2022-11-16 13:10:41 -0500419 !defined(CFG_SYS_INIT_L2_ADDR)
Simon Glassd35f3382017-04-06 12:47:05 -0600420int dram_init(void)
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600421{
Alexander Grafc3468482014-04-11 17:09:45 +0200422#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
York Sun51e91e82016-11-18 12:29:51 -0800423 defined(CONFIG_ARCH_QEMU_E500)
Simon Glass39f90ba2017-03-31 08:40:25 -0600424 gd->ram_size = fsl_ddr_sdram_size();
Zhao Chenhui1a35f3d2011-01-28 17:58:37 +0800425#else
Tom Rinibb4dd962022-11-16 13:10:37 -0500426 gd->ram_size = (phys_size_t)CFG_SYS_SDRAM_SIZE * 1024 * 1024;
Zhao Chenhui1a35f3d2011-01-28 17:58:37 +0800427#endif
Simon Glass39f90ba2017-03-31 08:40:25 -0600428
429 return 0;
Zhao Chenhui1a35f3d2011-01-28 17:58:37 +0800430}
431#else /* CONFIG_SYS_RAMBOOT */
Simon Glassd35f3382017-04-06 12:47:05 -0600432int dram_init(void)
Zhao Chenhui1a35f3d2011-01-28 17:58:37 +0800433{
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600434 phys_size_t dram_size = 0;
435
Becky Bruce4212f232010-12-17 17:17:58 -0600436#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600437 {
Tom Rinid5c3bf22022-10-28 20:27:12 -0400438 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600439 unsigned int x = 10;
440 unsigned int i;
441
442 /*
443 * Work around to stabilize DDR DLL
444 */
445 out_be32(&gur->ddrdllcr, 0x81000000);
446 asm("sync;isync;msync");
447 udelay(200);
448 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
449 setbits_be32(&gur->devdisr, 0x00010000);
450 for (i = 0; i < x; i++)
451 ;
452 clrbits_be32(&gur->devdisr, 0x00010000);
453 x++;
454 }
455 }
456#endif
457
York Sune73cc042011-06-07 09:42:16 +0800458#if defined(CONFIG_SPD_EEPROM) || \
459 defined(CONFIG_DDR_SPD) || \
460 defined(CONFIG_SYS_DDR_RAW_TIMING)
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600461 dram_size = fsl_ddr_sdram();
462#else
463 dram_size = fixed_sdram();
464#endif
465 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
466 dram_size *= 0x100000;
467
468#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
469 /*
470 * Initialize and enable DDR ECC.
471 */
472 ddr_enable_ecc(dram_size);
473#endif
474
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530475#if defined(CONFIG_FSL_LBC)
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600476 /* Some boards also have sdram on the lbc */
Becky Bruceb88d3d02010-12-17 17:17:57 -0600477 lbc_sdram_init();
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530478#endif
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600479
Wolfgang Denkf2bbb532011-07-25 10:13:53 +0200480 debug("DDR: ");
Simon Glass39f90ba2017-03-31 08:40:25 -0600481 gd->ram_size = dram_size;
482
483 return 0;
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600484}
Zhao Chenhui1a35f3d2011-01-28 17:58:37 +0800485#endif /* CONFIG_SYS_RAMBOOT */
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600486#endif
487
Tom Rini8eaa3c72022-11-19 18:45:44 -0500488#if CFG_POST & CFG_SYS_POST_MEMORY
York Sunc41b7442010-09-28 15:20:33 -0700489
490/* Board-specific functions defined in each board's ddr.c */
491void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
York Sun79a779b2014-08-01 15:51:00 -0700492 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
York Sunc41b7442010-09-28 15:20:33 -0700493void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
494 phys_addr_t *rpn);
495unsigned int
496 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
497
Becky Bruce69694472011-07-18 18:49:15 -0500498void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
499
York Sunc41b7442010-09-28 15:20:33 -0700500static void dump_spd_ddr_reg(void)
501{
502 int i, j, k, m;
503 u8 *p_8;
504 u32 *p_32;
York Sunfe845072016-12-28 08:43:45 -0800505 struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
York Sunc41b7442010-09-28 15:20:33 -0700506 generic_spd_eeprom_t
York Sunfe845072016-12-28 08:43:45 -0800507 spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
York Sunc41b7442010-09-28 15:20:33 -0700508
York Sunfe845072016-12-28 08:43:45 -0800509 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
York Sun79a779b2014-08-01 15:51:00 -0700510 fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
York Sunc41b7442010-09-28 15:20:33 -0700511
Robert P. J. Dayc5b1e5d2016-09-07 14:27:59 -0400512 puts("SPD data of all dimms (zero value is omitted)...\n");
York Sunc41b7442010-09-28 15:20:33 -0700513 puts("Byte (hex) ");
514 k = 1;
York Sunfe845072016-12-28 08:43:45 -0800515 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
York Sunc41b7442010-09-28 15:20:33 -0700516 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
517 printf("Dimm%d ", k++);
518 }
519 puts("\n");
520 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
521 m = 0;
522 printf("%3d (0x%02x) ", k, k);
York Sunfe845072016-12-28 08:43:45 -0800523 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
York Sunc41b7442010-09-28 15:20:33 -0700524 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
525 p_8 = (u8 *) &spd[i][j];
526 if (p_8[k]) {
527 printf("0x%02x ", p_8[k]);
528 m++;
529 } else
530 puts(" ");
531 }
532 }
533 if (m)
534 puts("\n");
535 else
536 puts("\r");
537 }
538
York Sunfe845072016-12-28 08:43:45 -0800539 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
York Sunc41b7442010-09-28 15:20:33 -0700540 switch (i) {
541 case 0:
Tom Rini376b88a2022-10-28 20:27:13 -0400542 ddr[i] = (void *)CFG_SYS_FSL_DDR_ADDR;
York Sunc41b7442010-09-28 15:20:33 -0700543 break;
Tom Rini376b88a2022-10-28 20:27:13 -0400544#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
York Sunc41b7442010-09-28 15:20:33 -0700545 case 1:
Tom Rini376b88a2022-10-28 20:27:13 -0400546 ddr[i] = (void *)CFG_SYS_FSL_DDR2_ADDR;
York Sunc41b7442010-09-28 15:20:33 -0700547 break;
548#endif
Tom Rini376b88a2022-10-28 20:27:13 -0400549#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
York Sune8dc17b2012-08-17 08:22:39 +0000550 case 2:
Tom Rini376b88a2022-10-28 20:27:13 -0400551 ddr[i] = (void *)CFG_SYS_FSL_DDR3_ADDR;
York Sune8dc17b2012-08-17 08:22:39 +0000552 break;
553#endif
York Sunfe845072016-12-28 08:43:45 -0800554#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
York Sune8dc17b2012-08-17 08:22:39 +0000555 case 3:
York Sunf0626592013-09-30 09:22:09 -0700556 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
York Sune8dc17b2012-08-17 08:22:39 +0000557 break;
558#endif
York Sunc41b7442010-09-28 15:20:33 -0700559 default:
560 printf("%s unexpected controller number = %u\n",
561 __func__, i);
562 return;
563 }
564 }
565 printf("DDR registers dump for all controllers "
Robert P. J. Dayc5b1e5d2016-09-07 14:27:59 -0400566 "(zero value is omitted)...\n");
York Sunc41b7442010-09-28 15:20:33 -0700567 puts("Offset (hex) ");
York Sunfe845072016-12-28 08:43:45 -0800568 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
York Sunc41b7442010-09-28 15:20:33 -0700569 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
570 puts("\n");
York Suna21803d2013-11-18 10:29:32 -0800571 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
York Sunc41b7442010-09-28 15:20:33 -0700572 m = 0;
573 printf("%6d (0x%04x)", k * 4, k * 4);
York Sunfe845072016-12-28 08:43:45 -0800574 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
York Sunc41b7442010-09-28 15:20:33 -0700575 p_32 = (u32 *) ddr[i];
576 if (p_32[k]) {
577 printf(" 0x%08x", p_32[k]);
578 m++;
579 } else
580 puts(" ");
581 }
582 if (m)
583 puts("\n");
584 else
585 puts("\r");
586 }
587 puts("\n");
588}
589
590/* invalid the TLBs for DDR and setup new ones to cover p_addr */
591static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
592{
Tom Rini6a5dccc2022-11-16 13:10:41 -0500593 u32 vstart = CFG_SYS_DDR_SDRAM_BASE;
York Sunc41b7442010-09-28 15:20:33 -0700594 unsigned long epn;
595 u32 tsize, valid, ptr;
York Sunc41b7442010-09-28 15:20:33 -0700596 int ddr_esel;
597
Becky Bruce69694472011-07-18 18:49:15 -0500598 clear_ddr_tlbs_phys(p_addr, size>>20);
York Sunc41b7442010-09-28 15:20:33 -0700599
600 /* Setup new tlb to cover the physical address */
601 setup_ddr_tlbs_phys(p_addr, size>>20);
602
603 ptr = vstart;
604 ddr_esel = find_tlb_idx((void *)ptr, 1);
605 if (ddr_esel != -1) {
606 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
607 } else {
608 printf("TLB error in function %s\n", __func__);
609 return -1;
610 }
611
612 return 0;
613}
614
615/*
616 * slide the testing window up to test another area
617 * for 32_bit system, the maximum testable memory is limited to
Tom Rinibc9d46b2022-12-04 10:04:50 -0500618 * CFG_MAX_MEM_MAPPED
York Sunc41b7442010-09-28 15:20:33 -0700619 */
620int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
621{
622 phys_addr_t test_cap, p_addr;
Tom Rinibc9d46b2022-12-04 10:04:50 -0500623 phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED);
York Sunc41b7442010-09-28 15:20:33 -0700624
625#if !defined(CONFIG_PHYS_64BIT) || \
Tom Rini6a5dccc2022-11-16 13:10:41 -0500626 !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
627 (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
York Sunc41b7442010-09-28 15:20:33 -0700628 test_cap = p_size;
629#else
630 test_cap = gd->ram_size;
631#endif
632 p_addr = (*vstart) + (*size) + (*phys_offset);
633 if (p_addr < test_cap - 1) {
Tom Rinibc9d46b2022-12-04 10:04:50 -0500634 p_size = min(test_cap - p_addr, CFG_MAX_MEM_MAPPED);
York Sunc41b7442010-09-28 15:20:33 -0700635 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
636 return -1;
Tom Rini6a5dccc2022-11-16 13:10:41 -0500637 *vstart = CFG_SYS_DDR_SDRAM_BASE;
York Sunc41b7442010-09-28 15:20:33 -0700638 *size = (u32) p_size;
639 printf("Testing 0x%08llx - 0x%08llx\n",
640 (u64)(*vstart) + (*phys_offset),
641 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
642 } else
643 return 1;
644
645 return 0;
646}
647
648/* initialization for testing area */
649int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
650{
Tom Rinibc9d46b2022-12-04 10:04:50 -0500651 phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED);
York Sunc41b7442010-09-28 15:20:33 -0700652
Tom Rini6a5dccc2022-11-16 13:10:41 -0500653 *vstart = CFG_SYS_DDR_SDRAM_BASE;
Tom Rinibc9d46b2022-12-04 10:04:50 -0500654 *size = (u32) p_size; /* CFG_MAX_MEM_MAPPED < 4G */
York Sunc41b7442010-09-28 15:20:33 -0700655 *phys_offset = 0;
656
657#if !defined(CONFIG_PHYS_64BIT) || \
Tom Rini6a5dccc2022-11-16 13:10:41 -0500658 !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
659 (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
Tom Rinibc9d46b2022-12-04 10:04:50 -0500660 if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
York Sunc41b7442010-09-28 15:20:33 -0700661 puts("Cannot test more than ");
Tom Rinibc9d46b2022-12-04 10:04:50 -0500662 print_size(CFG_MAX_MEM_MAPPED,
York Sunc41b7442010-09-28 15:20:33 -0700663 " without proper 36BIT support.\n");
664 }
665#endif
666 printf("Testing 0x%08llx - 0x%08llx\n",
667 (u64)(*vstart) + (*phys_offset),
668 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
669
670 return 0;
671}
672
673/* invalid TLBs for DDR and remap as normal after testing */
674int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
675{
676 unsigned long epn;
677 u32 tsize, valid, ptr;
678 phys_addr_t rpn = 0;
679 int ddr_esel;
680
681 /* disable the TLBs for this testing */
682 ptr = *vstart;
683
684 while (ptr < (*vstart) + (*size)) {
685 ddr_esel = find_tlb_idx((void *)ptr, 1);
686 if (ddr_esel != -1) {
687 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
688 disable_tlb(ddr_esel);
689 }
690 ptr += TSIZE_TO_BYTES(tsize);
691 }
692
693 puts("Remap DDR ");
694 setup_ddr_tlbs(gd->ram_size>>20);
695 puts("\n");
696
697 return 0;
698}
699
700void arch_memory_failure_handle(void)
701{
702 dump_spd_ddr_reg();
703}
704#endif