Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 2 | /* |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 3 | * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 4 | * (C) Copyright 2002, 2003 Motorola Inc. |
| 5 | * Xianghua Xiao (X.Xiao@motorola.com) |
| 6 | * |
| 7 | * (C) Copyright 2000 |
| 8 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 9 | */ |
| 10 | |
Andy Fleming | fecff2b | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 11 | #include <config.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 12 | #include <common.h> |
Simon Glass | 970b61e | 2019-11-14 12:57:09 -0700 | [diff] [blame] | 13 | #include <cpu_func.h> |
Simon Glass | f5c208d | 2019-11-14 12:57:20 -0700 | [diff] [blame^] | 14 | #include <vsprintf.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 15 | #include <watchdog.h> |
| 16 | #include <command.h> |
Andy Fleming | 6843a6e | 2008-10-30 16:51:33 -0500 | [diff] [blame] | 17 | #include <fsl_esdhc.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 18 | #include <asm/cache.h> |
Sergei Poselenov | ddc1a47 | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 19 | #include <asm/io.h> |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 20 | #include <asm/mmu.h> |
York Sun | 37562f6 | 2013-10-22 12:39:02 -0700 | [diff] [blame] | 21 | #include <fsl_ifc.h> |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 22 | #include <asm/fsl_law.h> |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 23 | #include <asm/fsl_lbc.h> |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 24 | #include <post.h> |
| 25 | #include <asm/processor.h> |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 26 | #include <fsl_ddr_sdram.h> |
Christophe Leroy | 31f6e93 | 2017-07-13 15:09:54 +0200 | [diff] [blame] | 27 | #include <asm/ppc.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 28 | |
James Yang | 957b191 | 2008-02-08 16:44:53 -0600 | [diff] [blame] | 29 | DECLARE_GLOBAL_DATA_PTR; |
| 30 | |
Ira W. Snyder | a85994c | 2011-11-21 13:20:32 -0800 | [diff] [blame] | 31 | /* |
| 32 | * Default board reset function |
| 33 | */ |
| 34 | static void |
| 35 | __board_reset(void) |
| 36 | { |
| 37 | /* Do nothing */ |
| 38 | } |
| 39 | void board_reset(void) __attribute__((weak, alias("__board_reset"))); |
| 40 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 41 | int checkcpu (void) |
| 42 | { |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 43 | sys_info_t sysinfo; |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 44 | uint pvr, svr; |
| 45 | uint ver; |
| 46 | uint major, minor; |
Kumar Gala | 8ddf00c | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 47 | struct cpu_type *cpu; |
Wolfgang Denk | 2059104 | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 48 | char buf1[32], buf2[32]; |
York Sun | c87e81e | 2013-06-25 11:37:43 -0700 | [diff] [blame] | 49 | #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) |
| 50 | ccsr_gur_t __iomem *gur = |
| 51 | (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 52 | #endif |
York Sun | 3b5179f | 2012-10-08 07:44:31 +0000 | [diff] [blame] | 53 | |
| 54 | /* |
| 55 | * Cornet platforms use ddr sync bit in RCW to indicate sync vs async |
| 56 | * mode. Previous platform use ddr ratio to do the same. This |
| 57 | * information is only for display here. |
| 58 | */ |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 59 | #ifdef CONFIG_FSL_CORENET |
York Sun | 383f6f6 | 2012-10-08 07:44:16 +0000 | [diff] [blame] | 60 | #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 |
York Sun | 3b5179f | 2012-10-08 07:44:31 +0000 | [diff] [blame] | 61 | u32 ddr_sync = 0; /* only async mode is supported */ |
York Sun | 383f6f6 | 2012-10-08 07:44:16 +0000 | [diff] [blame] | 62 | #else |
York Sun | 3b5179f | 2012-10-08 07:44:31 +0000 | [diff] [blame] | 63 | u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) |
Srikanth Srinivasan | f58c2a4 | 2010-02-10 17:32:43 +0800 | [diff] [blame] | 64 | >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; |
York Sun | 383f6f6 | 2012-10-08 07:44:16 +0000 | [diff] [blame] | 65 | #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ |
York Sun | 3b5179f | 2012-10-08 07:44:31 +0000 | [diff] [blame] | 66 | #else /* CONFIG_FSL_CORENET */ |
| 67 | #ifdef CONFIG_DDR_CLK_FREQ |
| 68 | u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) |
| 69 | >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; |
Kumar Gala | 54b6810 | 2008-05-29 01:21:24 -0500 | [diff] [blame] | 70 | #else |
| 71 | u32 ddr_ratio = 0; |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 72 | #endif /* CONFIG_DDR_CLK_FREQ */ |
York Sun | 3b5179f | 2012-10-08 07:44:31 +0000 | [diff] [blame] | 73 | #endif /* CONFIG_FSL_CORENET */ |
| 74 | |
Timur Tabi | 4728942 | 2011-08-05 16:15:24 -0500 | [diff] [blame] | 75 | unsigned int i, core, nr_cores = cpu_numcores(); |
| 76 | u32 mask = cpu_mask(); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 77 | |
Shaveta Leekha | dbf0bc8 | 2015-01-19 12:46:54 +0530 | [diff] [blame] | 78 | #ifdef CONFIG_HETROGENOUS_CLUSTERS |
| 79 | unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores(); |
| 80 | u32 dsp_mask = cpu_dsp_mask(); |
| 81 | #endif |
| 82 | |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 83 | svr = get_svr(); |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 84 | major = SVR_MAJ(svr); |
| 85 | minor = SVR_MIN(svr); |
| 86 | |
Shengzhou Liu | 26ed2d0 | 2014-04-25 16:31:22 +0800 | [diff] [blame] | 87 | #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) |
| 88 | if (SVR_SOC_VER(svr) == SVR_T4080) { |
| 89 | ccsr_rcpm_t *rcpm = |
| 90 | (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); |
| 91 | |
| 92 | setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || |
| 93 | FSL_CORENET_DEVDISR2_DTSEC1_9); |
| 94 | setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); |
| 95 | setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); |
| 96 | |
| 97 | /* It needs SW to disable core4~7 as HW design sake on T4080 */ |
| 98 | for (i = 4; i < 8; i++) |
| 99 | cpu_disable(i); |
| 100 | |
| 101 | /* request core4~7 into PH20 state, prior to entering PCL10 |
| 102 | * state, all cores in cluster should be placed in PH20 state. |
| 103 | */ |
| 104 | setbits_be32(&rcpm->pcph20setr, 0xf0); |
| 105 | |
| 106 | /* put the 2nd cluster into PCL10 state */ |
| 107 | setbits_be32(&rcpm->clpcl10setr, 1 << 1); |
| 108 | } |
| 109 | #endif |
| 110 | |
Poonam Aggrwal | 4baef82 | 2009-07-31 12:08:14 +0530 | [diff] [blame] | 111 | if (cpu_numcores() > 1) { |
Poonam Aggrwal | 36a6843 | 2009-09-03 19:42:40 +0530 | [diff] [blame] | 112 | #ifndef CONFIG_MP |
| 113 | puts("Unicore software on multiprocessor system!!\n" |
| 114 | "To enable mutlticore build define CONFIG_MP\n"); |
| 115 | #endif |
Kim Phillips | 2ecbfeb | 2010-08-09 18:39:57 -0500 | [diff] [blame] | 116 | volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); |
Poonam Aggrwal | 4baef82 | 2009-07-31 12:08:14 +0530 | [diff] [blame] | 117 | printf("CPU%d: ", pic->whoami); |
| 118 | } else { |
| 119 | puts("CPU: "); |
| 120 | } |
Andy Fleming | f574097 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 121 | |
Simon Glass | a8b5739 | 2012-12-13 20:48:48 +0000 | [diff] [blame] | 122 | cpu = gd->arch.cpu; |
Andy Fleming | f574097 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 123 | |
Poonam Aggrwal | da6e1ca | 2009-09-02 13:35:21 +0530 | [diff] [blame] | 124 | puts(cpu->name); |
| 125 | if (IS_E_PROCESSOR(svr)) |
| 126 | puts("E"); |
Andy Fleming | f574097 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 127 | |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 128 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 129 | |
wdenk | 3f3262b | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 130 | pvr = get_pvr(); |
| 131 | ver = PVR_VER(pvr); |
| 132 | major = PVR_MAJ(pvr); |
| 133 | minor = PVR_MIN(pvr); |
| 134 | |
| 135 | printf("Core: "); |
Kumar Gala | e222ed3 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 136 | switch(ver) { |
| 137 | case PVR_VER_E500_V1: |
| 138 | case PVR_VER_E500_V2: |
Fabio Estevam | f4c557c | 2013-04-21 13:11:02 -0300 | [diff] [blame] | 139 | puts("e500"); |
Kumar Gala | e222ed3 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 140 | break; |
| 141 | case PVR_VER_E500MC: |
Fabio Estevam | f4c557c | 2013-04-21 13:11:02 -0300 | [diff] [blame] | 142 | puts("e500mc"); |
Kumar Gala | e222ed3 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 143 | break; |
| 144 | case PVR_VER_E5500: |
Fabio Estevam | f4c557c | 2013-04-21 13:11:02 -0300 | [diff] [blame] | 145 | puts("e5500"); |
Kumar Gala | e222ed3 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 146 | break; |
Kumar Gala | c1abf4a | 2012-08-17 08:20:23 +0000 | [diff] [blame] | 147 | case PVR_VER_E6500: |
Fabio Estevam | f4c557c | 2013-04-21 13:11:02 -0300 | [diff] [blame] | 148 | puts("e6500"); |
Kumar Gala | c1abf4a | 2012-08-17 08:20:23 +0000 | [diff] [blame] | 149 | break; |
Kumar Gala | e222ed3 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 150 | default: |
Kumar Gala | bd2985c | 2009-10-21 13:23:54 -0500 | [diff] [blame] | 151 | puts("Unknown"); |
Kumar Gala | e222ed3 | 2011-07-25 09:28:39 -0500 | [diff] [blame] | 152 | break; |
wdenk | 3f3262b | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 153 | } |
Kumar Gala | 9f4a689 | 2008-10-23 01:47:38 -0500 | [diff] [blame] | 154 | |
wdenk | 3f3262b | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 155 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); |
| 156 | |
York Sun | 908412d | 2012-10-08 07:44:10 +0000 | [diff] [blame] | 157 | if (nr_cores > CONFIG_MAX_CPUS) { |
| 158 | panic("\nUnexpected number of cores: %d, max is %d\n", |
| 159 | nr_cores, CONFIG_MAX_CPUS); |
| 160 | } |
| 161 | |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 162 | get_sys_info(&sysinfo); |
| 163 | |
vijay rai | d84fd50 | 2014-04-15 11:34:12 +0530 | [diff] [blame] | 164 | #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK |
| 165 | if (sysinfo.diff_sysclk == 1) |
| 166 | puts("Single Source Clock Configuration\n"); |
| 167 | #endif |
| 168 | |
Kumar Gala | f92794c | 2009-02-04 09:35:57 -0600 | [diff] [blame] | 169 | puts("Clock Configuration:"); |
Timur Tabi | 4728942 | 2011-08-05 16:15:24 -0500 | [diff] [blame] | 170 | for_each_cpu(i, core, nr_cores, mask) { |
Wolfgang Denk | 1f79d14 | 2009-02-19 00:41:08 +0100 | [diff] [blame] | 171 | if (!(i & 3)) |
| 172 | printf ("\n "); |
Timur Tabi | 4728942 | 2011-08-05 16:15:24 -0500 | [diff] [blame] | 173 | printf("CPU%d:%-4s MHz, ", core, |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 174 | strmhz(buf1, sysinfo.freq_processor[core])); |
Kumar Gala | f92794c | 2009-02-04 09:35:57 -0600 | [diff] [blame] | 175 | } |
Shaveta Leekha | dbf0bc8 | 2015-01-19 12:46:54 +0530 | [diff] [blame] | 176 | |
| 177 | #ifdef CONFIG_HETROGENOUS_CLUSTERS |
| 178 | for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) { |
| 179 | if (!(j & 3)) |
| 180 | printf("\n "); |
| 181 | printf("DSP CPU%d:%-4s MHz, ", j, |
| 182 | strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core])); |
| 183 | } |
| 184 | #endif |
| 185 | |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 186 | printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus)); |
| 187 | printf("\n"); |
Kumar Gala | 54b6810 | 2008-05-29 01:21:24 -0500 | [diff] [blame] | 188 | |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 189 | #ifdef CONFIG_FSL_CORENET |
| 190 | if (ddr_sync == 1) { |
| 191 | printf(" DDR:%-4s MHz (%s MT/s data rate) " |
| 192 | "(Synchronous), ", |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 193 | strmhz(buf1, sysinfo.freq_ddrbus/2), |
| 194 | strmhz(buf2, sysinfo.freq_ddrbus)); |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 195 | } else { |
| 196 | printf(" DDR:%-4s MHz (%s MT/s data rate) " |
| 197 | "(Asynchronous), ", |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 198 | strmhz(buf1, sysinfo.freq_ddrbus/2), |
| 199 | strmhz(buf2, sysinfo.freq_ddrbus)); |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 200 | } |
| 201 | #else |
Kumar Gala | 07db170 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 202 | switch (ddr_ratio) { |
| 203 | case 0x0: |
Wolfgang Denk | 2059104 | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 204 | printf(" DDR:%-4s MHz (%s MT/s data rate), ", |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 205 | strmhz(buf1, sysinfo.freq_ddrbus/2), |
| 206 | strmhz(buf2, sysinfo.freq_ddrbus)); |
Kumar Gala | 07db170 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 207 | break; |
| 208 | case 0x7: |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 209 | printf(" DDR:%-4s MHz (%s MT/s data rate) " |
| 210 | "(Synchronous), ", |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 211 | strmhz(buf1, sysinfo.freq_ddrbus/2), |
| 212 | strmhz(buf2, sysinfo.freq_ddrbus)); |
Kumar Gala | 07db170 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 213 | break; |
| 214 | default: |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 215 | printf(" DDR:%-4s MHz (%s MT/s data rate) " |
| 216 | "(Asynchronous), ", |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 217 | strmhz(buf1, sysinfo.freq_ddrbus/2), |
| 218 | strmhz(buf2, sysinfo.freq_ddrbus)); |
Kumar Gala | 07db170 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 219 | break; |
| 220 | } |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 221 | #endif |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 222 | |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 223 | #if defined(CONFIG_FSL_LBC) |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 224 | if (sysinfo.freq_localbus > LCRR_CLKDIV) { |
| 225 | printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 226 | } else { |
Trent Piepho | 0b691fc | 2008-12-03 15:16:37 -0800 | [diff] [blame] | 227 | printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 228 | sysinfo.freq_localbus); |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 229 | } |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 230 | #endif |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 231 | |
Kumar Gala | 17ec6fa | 2012-10-08 07:44:06 +0000 | [diff] [blame] | 232 | #if defined(CONFIG_FSL_IFC) |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 233 | printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); |
Kumar Gala | 17ec6fa | 2012-10-08 07:44:06 +0000 | [diff] [blame] | 234 | #endif |
| 235 | |
Andy Fleming | f574097 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 236 | #ifdef CONFIG_CPM2 |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 237 | printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus)); |
Andy Fleming | f574097 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 238 | #endif |
wdenk | a445ddf | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 239 | |
Haiying Wang | 6141468 | 2009-05-20 12:30:29 -0400 | [diff] [blame] | 240 | #ifdef CONFIG_QE |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 241 | printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); |
Haiying Wang | 6141468 | 2009-05-20 12:30:29 -0400 | [diff] [blame] | 242 | #endif |
| 243 | |
Shaveta Leekha | dbf0bc8 | 2015-01-19 12:46:54 +0530 | [diff] [blame] | 244 | #if defined(CONFIG_SYS_CPRI) |
| 245 | printf(" "); |
| 246 | printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri)); |
| 247 | #endif |
| 248 | |
| 249 | #if defined(CONFIG_SYS_MAPLE) |
| 250 | printf("\n "); |
| 251 | printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple)); |
| 252 | printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb)); |
| 253 | printf("MAPLE-eTVPE:%-4s MHz\n", |
| 254 | strmhz(buf1, sysinfo.freq_maple_etvpe)); |
| 255 | #endif |
| 256 | |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 257 | #ifdef CONFIG_SYS_DPAA_FMAN |
| 258 | for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { |
Emil Medve | 3a9ed2f | 2010-06-17 00:08:29 -0500 | [diff] [blame] | 259 | printf(" FMAN%d: %s MHz\n", i + 1, |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 260 | strmhz(buf1, sysinfo.freq_fman[i])); |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 261 | } |
| 262 | #endif |
| 263 | |
Haiying Wang | 09d0aa9 | 2012-10-11 07:13:39 +0000 | [diff] [blame] | 264 | #ifdef CONFIG_SYS_DPAA_QBMAN |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 265 | printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman)); |
Haiying Wang | 09d0aa9 | 2012-10-11 07:13:39 +0000 | [diff] [blame] | 266 | #endif |
| 267 | |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 268 | #ifdef CONFIG_SYS_DPAA_PME |
Prabhakar Kushwaha | d169808 | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 269 | printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme)); |
Kumar Gala | dccd9e3 | 2009-03-19 02:46:19 -0500 | [diff] [blame] | 270 | #endif |
| 271 | |
Shruti Kanetkar | 8115936 | 2013-08-15 11:25:38 -0500 | [diff] [blame] | 272 | puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n"); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 273 | |
York Sun | c87e81e | 2013-06-25 11:37:43 -0700 | [diff] [blame] | 274 | #ifdef CONFIG_FSL_CORENET |
| 275 | /* Display the RCW, so that no one gets confused as to what RCW |
| 276 | * we're actually using for this boot. |
| 277 | */ |
| 278 | puts("Reset Configuration Word (RCW):"); |
| 279 | for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { |
| 280 | u32 rcw = in_be32(&gur->rcwsr[i]); |
| 281 | |
| 282 | if ((i % 4) == 0) |
| 283 | printf("\n %08x:", i * 4); |
| 284 | printf(" %08x", rcw); |
| 285 | } |
| 286 | puts("\n"); |
| 287 | #endif |
| 288 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 289 | return 0; |
| 290 | } |
| 291 | |
| 292 | |
| 293 | /* ------------------------------------------------------------------------- */ |
| 294 | |
Mike Frysinger | 6d1f698 | 2010-10-20 03:41:17 -0400 | [diff] [blame] | 295 | int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 296 | { |
Kumar Gala | aff0153 | 2009-09-08 13:46:46 -0500 | [diff] [blame] | 297 | /* Everything after the first generation of PQ3 parts has RSTCR */ |
York Sun | bf820c0 | 2016-11-16 11:18:31 -0800 | [diff] [blame] | 298 | #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \ |
York Sun | b4046f4 | 2016-11-16 11:26:45 -0800 | [diff] [blame] | 299 | defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560) |
Sergei Poselenov | 2514742 | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 300 | unsigned long val, msr; |
| 301 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 302 | /* |
| 303 | * Initiate hard reset in debug control register DBCR0 |
Kumar Gala | aff0153 | 2009-09-08 13:46:46 -0500 | [diff] [blame] | 304 | * Make sure MSR[DE] = 1. This only resets the core. |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 305 | */ |
Sergei Poselenov | 2514742 | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 306 | msr = mfmsr (); |
| 307 | msr |= MSR_DE; |
| 308 | mtmsr (msr); |
urwithsughosh@gmail.com | 06c2fb9 | 2007-09-24 13:32:13 -0400 | [diff] [blame] | 309 | |
Sergei Poselenov | 2514742 | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 310 | val = mfspr(DBCR0); |
| 311 | val |= 0x70000000; |
| 312 | mtspr(DBCR0,val); |
Kumar Gala | aff0153 | 2009-09-08 13:46:46 -0500 | [diff] [blame] | 313 | #else |
| 314 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
Ira W. Snyder | a85994c | 2011-11-21 13:20:32 -0800 | [diff] [blame] | 315 | |
| 316 | /* Attempt board-specific reset */ |
| 317 | board_reset(); |
| 318 | |
| 319 | /* Next try asserting HRESET_REQ */ |
| 320 | out_be32(&gur->rstcr, 0x2); |
Kumar Gala | aff0153 | 2009-09-08 13:46:46 -0500 | [diff] [blame] | 321 | udelay(100); |
| 322 | #endif |
Sergei Poselenov | 2514742 | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 323 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 324 | return 1; |
| 325 | } |
| 326 | |
| 327 | |
| 328 | /* |
| 329 | * Get timebase clock frequency |
| 330 | */ |
Kumar Gala | f4fb90f | 2011-02-18 05:40:54 -0600 | [diff] [blame] | 331 | #ifndef CONFIG_SYS_FSL_TBCLK_DIV |
| 332 | #define CONFIG_SYS_FSL_TBCLK_DIV 8 |
| 333 | #endif |
Alexander Graf | c346848 | 2014-04-11 17:09:45 +0200 | [diff] [blame] | 334 | __weak unsigned long get_tbclk (void) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 335 | { |
Kumar Gala | f4fb90f | 2011-02-18 05:40:54 -0600 | [diff] [blame] | 336 | unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; |
| 337 | |
| 338 | return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 339 | } |
| 340 | |
| 341 | |
| 342 | #if defined(CONFIG_WATCHDOG) |
Boschung, Rainer | f63c0dc1 | 2014-06-03 09:05:14 +0200 | [diff] [blame] | 343 | #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE) |
| 344 | void |
| 345 | init_85xx_watchdog(void) |
| 346 | { |
| 347 | mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) | |
| 348 | TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC)); |
| 349 | } |
| 350 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 351 | void |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 352 | reset_85xx_watchdog(void) |
| 353 | { |
| 354 | /* |
| 355 | * Clear TSR(WIS) bit by writing 1 |
| 356 | */ |
Mark Marshall | 10b13c9 | 2012-09-09 23:06:03 +0000 | [diff] [blame] | 357 | mtspr(SPRN_TSR, TSR_WIS); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 358 | } |
Horst Kronstorfer | f70831e | 2013-03-13 10:14:05 +0000 | [diff] [blame] | 359 | |
| 360 | void |
| 361 | watchdog_reset(void) |
| 362 | { |
| 363 | int re_enable = disable_interrupts(); |
| 364 | |
| 365 | reset_85xx_watchdog(); |
| 366 | if (re_enable) |
| 367 | enable_interrupts(); |
| 368 | } |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 369 | #endif /* CONFIG_WATCHDOG */ |
| 370 | |
Sergei Poselenov | ddc1a47 | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 371 | /* |
Andy Fleming | 6843a6e | 2008-10-30 16:51:33 -0500 | [diff] [blame] | 372 | * Initializes on-chip MMC controllers. |
| 373 | * to override, implement board_mmc_init() |
| 374 | */ |
| 375 | int cpu_mmc_init(bd_t *bis) |
| 376 | { |
| 377 | #ifdef CONFIG_FSL_ESDHC |
| 378 | return fsl_esdhc_mmc_init(bis); |
| 379 | #else |
| 380 | return 0; |
| 381 | #endif |
| 382 | } |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 383 | |
| 384 | /* |
| 385 | * Print out the state of various machine registers. |
Dipen Dudhat | 00c4294 | 2011-01-20 16:29:35 +0530 | [diff] [blame] | 386 | * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing |
| 387 | * parameters for IFC and TLBs |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 388 | */ |
Christophe Leroy | 31f6e93 | 2017-07-13 15:09:54 +0200 | [diff] [blame] | 389 | void print_reginfo(void) |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 390 | { |
| 391 | print_tlbcam(); |
| 392 | print_laws(); |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 393 | #if defined(CONFIG_FSL_LBC) |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 394 | print_lbc_regs(); |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 395 | #endif |
Dipen Dudhat | 00c4294 | 2011-01-20 16:29:35 +0530 | [diff] [blame] | 396 | #ifdef CONFIG_FSL_IFC |
| 397 | print_ifc_regs(); |
| 398 | #endif |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 399 | |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 400 | } |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 401 | |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 402 | /* Common ddr init for non-corenet fsl 85xx platforms */ |
| 403 | #ifndef CONFIG_FSL_CORENET |
Scott Wood | 095b712 | 2012-09-20 19:02:18 -0500 | [diff] [blame] | 404 | #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \ |
| 405 | !defined(CONFIG_SYS_INIT_L2_ADDR) |
Simon Glass | d35f338 | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 406 | int dram_init(void) |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 407 | { |
Alexander Graf | c346848 | 2014-04-11 17:09:45 +0200 | [diff] [blame] | 408 | #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \ |
York Sun | 51e91e8 | 2016-11-18 12:29:51 -0800 | [diff] [blame] | 409 | defined(CONFIG_ARCH_QEMU_E500) |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 410 | gd->ram_size = fsl_ddr_sdram_size(); |
Zhao Chenhui | 1a35f3d | 2011-01-28 17:58:37 +0800 | [diff] [blame] | 411 | #else |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 412 | gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
Zhao Chenhui | 1a35f3d | 2011-01-28 17:58:37 +0800 | [diff] [blame] | 413 | #endif |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 414 | |
| 415 | return 0; |
Zhao Chenhui | 1a35f3d | 2011-01-28 17:58:37 +0800 | [diff] [blame] | 416 | } |
| 417 | #else /* CONFIG_SYS_RAMBOOT */ |
Simon Glass | d35f338 | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 418 | int dram_init(void) |
Zhao Chenhui | 1a35f3d | 2011-01-28 17:58:37 +0800 | [diff] [blame] | 419 | { |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 420 | phys_size_t dram_size = 0; |
| 421 | |
Becky Bruce | 4212f23 | 2010-12-17 17:17:58 -0600 | [diff] [blame] | 422 | #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 423 | { |
| 424 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 425 | unsigned int x = 10; |
| 426 | unsigned int i; |
| 427 | |
| 428 | /* |
| 429 | * Work around to stabilize DDR DLL |
| 430 | */ |
| 431 | out_be32(&gur->ddrdllcr, 0x81000000); |
| 432 | asm("sync;isync;msync"); |
| 433 | udelay(200); |
| 434 | while (in_be32(&gur->ddrdllcr) != 0x81000100) { |
| 435 | setbits_be32(&gur->devdisr, 0x00010000); |
| 436 | for (i = 0; i < x; i++) |
| 437 | ; |
| 438 | clrbits_be32(&gur->devdisr, 0x00010000); |
| 439 | x++; |
| 440 | } |
| 441 | } |
| 442 | #endif |
| 443 | |
York Sun | e73cc04 | 2011-06-07 09:42:16 +0800 | [diff] [blame] | 444 | #if defined(CONFIG_SPD_EEPROM) || \ |
| 445 | defined(CONFIG_DDR_SPD) || \ |
| 446 | defined(CONFIG_SYS_DDR_RAW_TIMING) |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 447 | dram_size = fsl_ddr_sdram(); |
| 448 | #else |
| 449 | dram_size = fixed_sdram(); |
| 450 | #endif |
| 451 | dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
| 452 | dram_size *= 0x100000; |
| 453 | |
| 454 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 455 | /* |
| 456 | * Initialize and enable DDR ECC. |
| 457 | */ |
| 458 | ddr_enable_ecc(dram_size); |
| 459 | #endif |
| 460 | |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 461 | #if defined(CONFIG_FSL_LBC) |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 462 | /* Some boards also have sdram on the lbc */ |
Becky Bruce | b88d3d0 | 2010-12-17 17:17:57 -0600 | [diff] [blame] | 463 | lbc_sdram_init(); |
Dipen Dudhat | 5d51bf9 | 2011-01-19 12:46:27 +0530 | [diff] [blame] | 464 | #endif |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 465 | |
Wolfgang Denk | f2bbb53 | 2011-07-25 10:13:53 +0200 | [diff] [blame] | 466 | debug("DDR: "); |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 467 | gd->ram_size = dram_size; |
| 468 | |
| 469 | return 0; |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 470 | } |
Zhao Chenhui | 1a35f3d | 2011-01-28 17:58:37 +0800 | [diff] [blame] | 471 | #endif /* CONFIG_SYS_RAMBOOT */ |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 472 | #endif |
| 473 | |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 474 | #if CONFIG_POST & CONFIG_SYS_POST_MEMORY |
| 475 | |
| 476 | /* Board-specific functions defined in each board's ddr.c */ |
| 477 | void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
York Sun | 79a779b | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 478 | unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl); |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 479 | void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, |
| 480 | phys_addr_t *rpn); |
| 481 | unsigned int |
| 482 | setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); |
| 483 | |
Becky Bruce | 6969447 | 2011-07-18 18:49:15 -0500 | [diff] [blame] | 484 | void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); |
| 485 | |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 486 | static void dump_spd_ddr_reg(void) |
| 487 | { |
| 488 | int i, j, k, m; |
| 489 | u8 *p_8; |
| 490 | u32 *p_32; |
York Sun | fe84507 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 491 | struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS]; |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 492 | generic_spd_eeprom_t |
York Sun | fe84507 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 493 | spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR]; |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 494 | |
York Sun | fe84507 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 495 | for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) |
York Sun | 79a779b | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 496 | fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR); |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 497 | |
Robert P. J. Day | c5b1e5d | 2016-09-07 14:27:59 -0400 | [diff] [blame] | 498 | puts("SPD data of all dimms (zero value is omitted)...\n"); |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 499 | puts("Byte (hex) "); |
| 500 | k = 1; |
York Sun | fe84507 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 501 | for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 502 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) |
| 503 | printf("Dimm%d ", k++); |
| 504 | } |
| 505 | puts("\n"); |
| 506 | for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { |
| 507 | m = 0; |
| 508 | printf("%3d (0x%02x) ", k, k); |
York Sun | fe84507 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 509 | for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 510 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
| 511 | p_8 = (u8 *) &spd[i][j]; |
| 512 | if (p_8[k]) { |
| 513 | printf("0x%02x ", p_8[k]); |
| 514 | m++; |
| 515 | } else |
| 516 | puts(" "); |
| 517 | } |
| 518 | } |
| 519 | if (m) |
| 520 | puts("\n"); |
| 521 | else |
| 522 | puts("\r"); |
| 523 | } |
| 524 | |
York Sun | fe84507 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 525 | for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 526 | switch (i) { |
| 527 | case 0: |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 528 | ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR; |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 529 | break; |
York Sun | fe84507 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 530 | #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 531 | case 1: |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 532 | ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR; |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 533 | break; |
| 534 | #endif |
York Sun | fe84507 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 535 | #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 536 | case 2: |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 537 | ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR; |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 538 | break; |
| 539 | #endif |
York Sun | fe84507 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 540 | #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 541 | case 3: |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 542 | ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR; |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 543 | break; |
| 544 | #endif |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 545 | default: |
| 546 | printf("%s unexpected controller number = %u\n", |
| 547 | __func__, i); |
| 548 | return; |
| 549 | } |
| 550 | } |
| 551 | printf("DDR registers dump for all controllers " |
Robert P. J. Day | c5b1e5d | 2016-09-07 14:27:59 -0400 | [diff] [blame] | 552 | "(zero value is omitted)...\n"); |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 553 | puts("Offset (hex) "); |
York Sun | fe84507 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 554 | for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 555 | printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); |
| 556 | puts("\n"); |
York Sun | a21803d | 2013-11-18 10:29:32 -0800 | [diff] [blame] | 557 | for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) { |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 558 | m = 0; |
| 559 | printf("%6d (0x%04x)", k * 4, k * 4); |
York Sun | fe84507 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 560 | for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 561 | p_32 = (u32 *) ddr[i]; |
| 562 | if (p_32[k]) { |
| 563 | printf(" 0x%08x", p_32[k]); |
| 564 | m++; |
| 565 | } else |
| 566 | puts(" "); |
| 567 | } |
| 568 | if (m) |
| 569 | puts("\n"); |
| 570 | else |
| 571 | puts("\r"); |
| 572 | } |
| 573 | puts("\n"); |
| 574 | } |
| 575 | |
| 576 | /* invalid the TLBs for DDR and setup new ones to cover p_addr */ |
| 577 | static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) |
| 578 | { |
| 579 | u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; |
| 580 | unsigned long epn; |
| 581 | u32 tsize, valid, ptr; |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 582 | int ddr_esel; |
| 583 | |
Becky Bruce | 6969447 | 2011-07-18 18:49:15 -0500 | [diff] [blame] | 584 | clear_ddr_tlbs_phys(p_addr, size>>20); |
York Sun | c41b744 | 2010-09-28 15:20:33 -0700 | [diff] [blame] | 585 | |
| 586 | /* Setup new tlb to cover the physical address */ |
| 587 | setup_ddr_tlbs_phys(p_addr, size>>20); |
| 588 | |
| 589 | ptr = vstart; |
| 590 | ddr_esel = find_tlb_idx((void *)ptr, 1); |
| 591 | if (ddr_esel != -1) { |
| 592 | read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); |
| 593 | } else { |
| 594 | printf("TLB error in function %s\n", __func__); |
| 595 | return -1; |
| 596 | } |
| 597 | |
| 598 | return 0; |
| 599 | } |
| 600 | |
| 601 | /* |
| 602 | * slide the testing window up to test another area |
| 603 | * for 32_bit system, the maximum testable memory is limited to |
| 604 | * CONFIG_MAX_MEM_MAPPED |
| 605 | */ |
| 606 | int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) |
| 607 | { |
| 608 | phys_addr_t test_cap, p_addr; |
| 609 | phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); |
| 610 | |
| 611 | #if !defined(CONFIG_PHYS_64BIT) || \ |
| 612 | !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ |
| 613 | (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) |
| 614 | test_cap = p_size; |
| 615 | #else |
| 616 | test_cap = gd->ram_size; |
| 617 | #endif |
| 618 | p_addr = (*vstart) + (*size) + (*phys_offset); |
| 619 | if (p_addr < test_cap - 1) { |
| 620 | p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); |
| 621 | if (reset_tlb(p_addr, p_size, phys_offset) == -1) |
| 622 | return -1; |
| 623 | *vstart = CONFIG_SYS_DDR_SDRAM_BASE; |
| 624 | *size = (u32) p_size; |
| 625 | printf("Testing 0x%08llx - 0x%08llx\n", |
| 626 | (u64)(*vstart) + (*phys_offset), |
| 627 | (u64)(*vstart) + (*phys_offset) + (*size) - 1); |
| 628 | } else |
| 629 | return 1; |
| 630 | |
| 631 | return 0; |
| 632 | } |
| 633 | |
| 634 | /* initialization for testing area */ |
| 635 | int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) |
| 636 | { |
| 637 | phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); |
| 638 | |
| 639 | *vstart = CONFIG_SYS_DDR_SDRAM_BASE; |
| 640 | *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ |
| 641 | *phys_offset = 0; |
| 642 | |
| 643 | #if !defined(CONFIG_PHYS_64BIT) || \ |
| 644 | !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ |
| 645 | (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) |
| 646 | if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { |
| 647 | puts("Cannot test more than "); |
| 648 | print_size(CONFIG_MAX_MEM_MAPPED, |
| 649 | " without proper 36BIT support.\n"); |
| 650 | } |
| 651 | #endif |
| 652 | printf("Testing 0x%08llx - 0x%08llx\n", |
| 653 | (u64)(*vstart) + (*phys_offset), |
| 654 | (u64)(*vstart) + (*phys_offset) + (*size) - 1); |
| 655 | |
| 656 | return 0; |
| 657 | } |
| 658 | |
| 659 | /* invalid TLBs for DDR and remap as normal after testing */ |
| 660 | int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) |
| 661 | { |
| 662 | unsigned long epn; |
| 663 | u32 tsize, valid, ptr; |
| 664 | phys_addr_t rpn = 0; |
| 665 | int ddr_esel; |
| 666 | |
| 667 | /* disable the TLBs for this testing */ |
| 668 | ptr = *vstart; |
| 669 | |
| 670 | while (ptr < (*vstart) + (*size)) { |
| 671 | ddr_esel = find_tlb_idx((void *)ptr, 1); |
| 672 | if (ddr_esel != -1) { |
| 673 | read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); |
| 674 | disable_tlb(ddr_esel); |
| 675 | } |
| 676 | ptr += TSIZE_TO_BYTES(tsize); |
| 677 | } |
| 678 | |
| 679 | puts("Remap DDR "); |
| 680 | setup_ddr_tlbs(gd->ram_size>>20); |
| 681 | puts("\n"); |
| 682 | |
| 683 | return 0; |
| 684 | } |
| 685 | |
| 686 | void arch_memory_failure_handle(void) |
| 687 | { |
| 688 | dump_spd_ddr_reg(); |
| 689 | } |
| 690 | #endif |