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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk9c53f402003-10-15 23:53:47 +00002/*
Dipen Dudhat5d51bf92011-01-19 12:46:27 +05303 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
wdenk9c53f402003-10-15 23:53:47 +00004 * (C) Copyright 2002, 2003 Motorola Inc.
5 * Xianghua Xiao (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk9c53f402003-10-15 23:53:47 +00009 */
10
Andy Flemingfecff2b2008-08-31 16:33:26 -050011#include <config.h>
wdenk9c53f402003-10-15 23:53:47 +000012#include <common.h>
Simon Glass970b61e2019-11-14 12:57:09 -070013#include <cpu_func.h>
Simon Glassf5c208d2019-11-14 12:57:20 -070014#include <vsprintf.h>
wdenk9c53f402003-10-15 23:53:47 +000015#include <watchdog.h>
16#include <command.h>
Andy Fleming6843a6e2008-10-30 16:51:33 -050017#include <fsl_esdhc.h>
wdenk9c53f402003-10-15 23:53:47 +000018#include <asm/cache.h>
Sergei Poselenovddc1a472008-06-06 15:42:40 +020019#include <asm/io.h>
Becky Bruceee888da2010-06-17 11:37:25 -050020#include <asm/mmu.h>
York Sun37562f62013-10-22 12:39:02 -070021#include <fsl_ifc.h>
Becky Bruceee888da2010-06-17 11:37:25 -050022#include <asm/fsl_law.h>
Becky Bruce5e35d8a2010-12-17 17:17:56 -060023#include <asm/fsl_lbc.h>
York Sunc41b7442010-09-28 15:20:33 -070024#include <post.h>
25#include <asm/processor.h>
York Sunf0626592013-09-30 09:22:09 -070026#include <fsl_ddr_sdram.h>
Christophe Leroy31f6e932017-07-13 15:09:54 +020027#include <asm/ppc.h>
wdenk9c53f402003-10-15 23:53:47 +000028
James Yang957b1912008-02-08 16:44:53 -060029DECLARE_GLOBAL_DATA_PTR;
30
Ira W. Snydera85994c2011-11-21 13:20:32 -080031/*
32 * Default board reset function
33 */
34static void
35__board_reset(void)
36{
37 /* Do nothing */
38}
39void board_reset(void) __attribute__((weak, alias("__board_reset")));
40
wdenk9c53f402003-10-15 23:53:47 +000041int checkcpu (void)
42{
wdenka445ddf2004-06-09 00:34:46 +000043 sys_info_t sysinfo;
wdenka445ddf2004-06-09 00:34:46 +000044 uint pvr, svr;
45 uint ver;
46 uint major, minor;
Kumar Gala8ddf00c2008-06-10 16:53:46 -050047 struct cpu_type *cpu;
Wolfgang Denk20591042008-10-19 02:35:49 +020048 char buf1[32], buf2[32];
York Sunc87e81e2013-06-25 11:37:43 -070049#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
50 ccsr_gur_t __iomem *gur =
51 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
52#endif
York Sun3b5179f2012-10-08 07:44:31 +000053
54 /*
55 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
56 * mode. Previous platform use ddr ratio to do the same. This
57 * information is only for display here.
58 */
Kumar Galadccd9e32009-03-19 02:46:19 -050059#ifdef CONFIG_FSL_CORENET
York Sun383f6f62012-10-08 07:44:16 +000060#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
York Sun3b5179f2012-10-08 07:44:31 +000061 u32 ddr_sync = 0; /* only async mode is supported */
York Sun383f6f62012-10-08 07:44:16 +000062#else
York Sun3b5179f2012-10-08 07:44:31 +000063 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
Srikanth Srinivasanf58c2a42010-02-10 17:32:43 +080064 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
York Sun383f6f62012-10-08 07:44:16 +000065#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
York Sun3b5179f2012-10-08 07:44:31 +000066#else /* CONFIG_FSL_CORENET */
67#ifdef CONFIG_DDR_CLK_FREQ
68 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
69 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
Kumar Gala54b68102008-05-29 01:21:24 -050070#else
71 u32 ddr_ratio = 0;
Kumar Galadccd9e32009-03-19 02:46:19 -050072#endif /* CONFIG_DDR_CLK_FREQ */
York Sun3b5179f2012-10-08 07:44:31 +000073#endif /* CONFIG_FSL_CORENET */
74
Timur Tabi47289422011-08-05 16:15:24 -050075 unsigned int i, core, nr_cores = cpu_numcores();
76 u32 mask = cpu_mask();
wdenk9c53f402003-10-15 23:53:47 +000077
Shaveta Leekhadbf0bc82015-01-19 12:46:54 +053078#ifdef CONFIG_HETROGENOUS_CLUSTERS
79 unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
80 u32 dsp_mask = cpu_dsp_mask();
81#endif
82
wdenka445ddf2004-06-09 00:34:46 +000083 svr = get_svr();
wdenka445ddf2004-06-09 00:34:46 +000084 major = SVR_MAJ(svr);
85 minor = SVR_MIN(svr);
86
Shengzhou Liu26ed2d02014-04-25 16:31:22 +080087#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
88 if (SVR_SOC_VER(svr) == SVR_T4080) {
89 ccsr_rcpm_t *rcpm =
90 (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
91
92 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
93 FSL_CORENET_DEVDISR2_DTSEC1_9);
94 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
95 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
96
97 /* It needs SW to disable core4~7 as HW design sake on T4080 */
98 for (i = 4; i < 8; i++)
99 cpu_disable(i);
100
101 /* request core4~7 into PH20 state, prior to entering PCL10
102 * state, all cores in cluster should be placed in PH20 state.
103 */
104 setbits_be32(&rcpm->pcph20setr, 0xf0);
105
106 /* put the 2nd cluster into PCL10 state */
107 setbits_be32(&rcpm->clpcl10setr, 1 << 1);
108 }
109#endif
110
Poonam Aggrwal4baef822009-07-31 12:08:14 +0530111 if (cpu_numcores() > 1) {
Poonam Aggrwal36a68432009-09-03 19:42:40 +0530112#ifndef CONFIG_MP
113 puts("Unicore software on multiprocessor system!!\n"
114 "To enable mutlticore build define CONFIG_MP\n");
115#endif
Kim Phillips2ecbfeb2010-08-09 18:39:57 -0500116 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
Poonam Aggrwal4baef822009-07-31 12:08:14 +0530117 printf("CPU%d: ", pic->whoami);
118 } else {
119 puts("CPU: ");
120 }
Andy Flemingf5740972008-02-06 01:19:40 -0600121
Simon Glassa8b57392012-12-13 20:48:48 +0000122 cpu = gd->arch.cpu;
Andy Flemingf5740972008-02-06 01:19:40 -0600123
Poonam Aggrwalda6e1ca2009-09-02 13:35:21 +0530124 puts(cpu->name);
125 if (IS_E_PROCESSOR(svr))
126 puts("E");
Andy Flemingf5740972008-02-06 01:19:40 -0600127
wdenka445ddf2004-06-09 00:34:46 +0000128 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
wdenk9c53f402003-10-15 23:53:47 +0000129
wdenk3f3262b2005-03-15 22:56:53 +0000130 pvr = get_pvr();
131 ver = PVR_VER(pvr);
132 major = PVR_MAJ(pvr);
133 minor = PVR_MIN(pvr);
134
135 printf("Core: ");
Kumar Galae222ed32011-07-25 09:28:39 -0500136 switch(ver) {
137 case PVR_VER_E500_V1:
138 case PVR_VER_E500_V2:
Fabio Estevamf4c557c2013-04-21 13:11:02 -0300139 puts("e500");
Kumar Galae222ed32011-07-25 09:28:39 -0500140 break;
141 case PVR_VER_E500MC:
Fabio Estevamf4c557c2013-04-21 13:11:02 -0300142 puts("e500mc");
Kumar Galae222ed32011-07-25 09:28:39 -0500143 break;
144 case PVR_VER_E5500:
Fabio Estevamf4c557c2013-04-21 13:11:02 -0300145 puts("e5500");
Kumar Galae222ed32011-07-25 09:28:39 -0500146 break;
Kumar Galac1abf4a2012-08-17 08:20:23 +0000147 case PVR_VER_E6500:
Fabio Estevamf4c557c2013-04-21 13:11:02 -0300148 puts("e6500");
Kumar Galac1abf4a2012-08-17 08:20:23 +0000149 break;
Kumar Galae222ed32011-07-25 09:28:39 -0500150 default:
Kumar Galabd2985c2009-10-21 13:23:54 -0500151 puts("Unknown");
Kumar Galae222ed32011-07-25 09:28:39 -0500152 break;
wdenk3f3262b2005-03-15 22:56:53 +0000153 }
Kumar Gala9f4a6892008-10-23 01:47:38 -0500154
wdenk3f3262b2005-03-15 22:56:53 +0000155 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
156
York Sun908412d2012-10-08 07:44:10 +0000157 if (nr_cores > CONFIG_MAX_CPUS) {
158 panic("\nUnexpected number of cores: %d, max is %d\n",
159 nr_cores, CONFIG_MAX_CPUS);
160 }
161
wdenka445ddf2004-06-09 00:34:46 +0000162 get_sys_info(&sysinfo);
163
vijay raid84fd502014-04-15 11:34:12 +0530164#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
165 if (sysinfo.diff_sysclk == 1)
166 puts("Single Source Clock Configuration\n");
167#endif
168
Kumar Galaf92794c2009-02-04 09:35:57 -0600169 puts("Clock Configuration:");
Timur Tabi47289422011-08-05 16:15:24 -0500170 for_each_cpu(i, core, nr_cores, mask) {
Wolfgang Denk1f79d142009-02-19 00:41:08 +0100171 if (!(i & 3))
172 printf ("\n ");
Timur Tabi47289422011-08-05 16:15:24 -0500173 printf("CPU%d:%-4s MHz, ", core,
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530174 strmhz(buf1, sysinfo.freq_processor[core]));
Kumar Galaf92794c2009-02-04 09:35:57 -0600175 }
Shaveta Leekhadbf0bc82015-01-19 12:46:54 +0530176
177#ifdef CONFIG_HETROGENOUS_CLUSTERS
178 for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
179 if (!(j & 3))
180 printf("\n ");
181 printf("DSP CPU%d:%-4s MHz, ", j,
182 strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
183 }
184#endif
185
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530186 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
187 printf("\n");
Kumar Gala54b68102008-05-29 01:21:24 -0500188
Kumar Galadccd9e32009-03-19 02:46:19 -0500189#ifdef CONFIG_FSL_CORENET
190 if (ddr_sync == 1) {
191 printf(" DDR:%-4s MHz (%s MT/s data rate) "
192 "(Synchronous), ",
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530193 strmhz(buf1, sysinfo.freq_ddrbus/2),
194 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Galadccd9e32009-03-19 02:46:19 -0500195 } else {
196 printf(" DDR:%-4s MHz (%s MT/s data rate) "
197 "(Asynchronous), ",
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530198 strmhz(buf1, sysinfo.freq_ddrbus/2),
199 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Galadccd9e32009-03-19 02:46:19 -0500200 }
201#else
Kumar Gala07db1702007-12-07 04:59:26 -0600202 switch (ddr_ratio) {
203 case 0x0:
Wolfgang Denk20591042008-10-19 02:35:49 +0200204 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530205 strmhz(buf1, sysinfo.freq_ddrbus/2),
206 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Gala07db1702007-12-07 04:59:26 -0600207 break;
208 case 0x7:
Kumar Galadccd9e32009-03-19 02:46:19 -0500209 printf(" DDR:%-4s MHz (%s MT/s data rate) "
210 "(Synchronous), ",
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530211 strmhz(buf1, sysinfo.freq_ddrbus/2),
212 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Gala07db1702007-12-07 04:59:26 -0600213 break;
214 default:
Kumar Galadccd9e32009-03-19 02:46:19 -0500215 printf(" DDR:%-4s MHz (%s MT/s data rate) "
216 "(Asynchronous), ",
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530217 strmhz(buf1, sysinfo.freq_ddrbus/2),
218 strmhz(buf2, sysinfo.freq_ddrbus));
Kumar Gala07db1702007-12-07 04:59:26 -0600219 break;
220 }
Kumar Galadccd9e32009-03-19 02:46:19 -0500221#endif
wdenka445ddf2004-06-09 00:34:46 +0000222
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530223#if defined(CONFIG_FSL_LBC)
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530224 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
225 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
Kumar Galadccd9e32009-03-19 02:46:19 -0500226 } else {
Trent Piepho0b691fc2008-12-03 15:16:37 -0800227 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530228 sysinfo.freq_localbus);
Kumar Galadccd9e32009-03-19 02:46:19 -0500229 }
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530230#endif
wdenka445ddf2004-06-09 00:34:46 +0000231
Kumar Gala17ec6fa2012-10-08 07:44:06 +0000232#if defined(CONFIG_FSL_IFC)
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530233 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
Kumar Gala17ec6fa2012-10-08 07:44:06 +0000234#endif
235
Andy Flemingf5740972008-02-06 01:19:40 -0600236#ifdef CONFIG_CPM2
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530237 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
Andy Flemingf5740972008-02-06 01:19:40 -0600238#endif
wdenka445ddf2004-06-09 00:34:46 +0000239
Haiying Wang61414682009-05-20 12:30:29 -0400240#ifdef CONFIG_QE
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530241 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
Haiying Wang61414682009-05-20 12:30:29 -0400242#endif
243
Shaveta Leekhadbf0bc82015-01-19 12:46:54 +0530244#if defined(CONFIG_SYS_CPRI)
245 printf(" ");
246 printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
247#endif
248
249#if defined(CONFIG_SYS_MAPLE)
250 printf("\n ");
251 printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
252 printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
253 printf("MAPLE-eTVPE:%-4s MHz\n",
254 strmhz(buf1, sysinfo.freq_maple_etvpe));
255#endif
256
Kumar Galadccd9e32009-03-19 02:46:19 -0500257#ifdef CONFIG_SYS_DPAA_FMAN
258 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
Emil Medve3a9ed2f2010-06-17 00:08:29 -0500259 printf(" FMAN%d: %s MHz\n", i + 1,
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530260 strmhz(buf1, sysinfo.freq_fman[i]));
Kumar Galadccd9e32009-03-19 02:46:19 -0500261 }
262#endif
263
Haiying Wang09d0aa92012-10-11 07:13:39 +0000264#ifdef CONFIG_SYS_DPAA_QBMAN
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530265 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
Haiying Wang09d0aa92012-10-11 07:13:39 +0000266#endif
267
Kumar Galadccd9e32009-03-19 02:46:19 -0500268#ifdef CONFIG_SYS_DPAA_PME
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530269 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
Kumar Galadccd9e32009-03-19 02:46:19 -0500270#endif
271
Shruti Kanetkar81159362013-08-15 11:25:38 -0500272 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
wdenk9c53f402003-10-15 23:53:47 +0000273
York Sunc87e81e2013-06-25 11:37:43 -0700274#ifdef CONFIG_FSL_CORENET
275 /* Display the RCW, so that no one gets confused as to what RCW
276 * we're actually using for this boot.
277 */
278 puts("Reset Configuration Word (RCW):");
279 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
280 u32 rcw = in_be32(&gur->rcwsr[i]);
281
282 if ((i % 4) == 0)
283 printf("\n %08x:", i * 4);
284 printf(" %08x", rcw);
285 }
286 puts("\n");
287#endif
288
wdenk9c53f402003-10-15 23:53:47 +0000289 return 0;
290}
291
292
293/* ------------------------------------------------------------------------- */
294
Mike Frysinger6d1f6982010-10-20 03:41:17 -0400295int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
wdenk9c53f402003-10-15 23:53:47 +0000296{
Kumar Galaaff01532009-09-08 13:46:46 -0500297/* Everything after the first generation of PQ3 parts has RSTCR */
York Sunbf820c02016-11-16 11:18:31 -0800298#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
York Sunb4046f42016-11-16 11:26:45 -0800299 defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
Sergei Poselenov25147422008-05-08 14:17:08 +0200300 unsigned long val, msr;
301
wdenk9c53f402003-10-15 23:53:47 +0000302 /*
303 * Initiate hard reset in debug control register DBCR0
Kumar Galaaff01532009-09-08 13:46:46 -0500304 * Make sure MSR[DE] = 1. This only resets the core.
wdenk9c53f402003-10-15 23:53:47 +0000305 */
Sergei Poselenov25147422008-05-08 14:17:08 +0200306 msr = mfmsr ();
307 msr |= MSR_DE;
308 mtmsr (msr);
urwithsughosh@gmail.com06c2fb92007-09-24 13:32:13 -0400309
Sergei Poselenov25147422008-05-08 14:17:08 +0200310 val = mfspr(DBCR0);
311 val |= 0x70000000;
312 mtspr(DBCR0,val);
Kumar Galaaff01532009-09-08 13:46:46 -0500313#else
314 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Ira W. Snydera85994c2011-11-21 13:20:32 -0800315
316 /* Attempt board-specific reset */
317 board_reset();
318
319 /* Next try asserting HRESET_REQ */
320 out_be32(&gur->rstcr, 0x2);
Kumar Galaaff01532009-09-08 13:46:46 -0500321 udelay(100);
322#endif
Sergei Poselenov25147422008-05-08 14:17:08 +0200323
wdenk9c53f402003-10-15 23:53:47 +0000324 return 1;
325}
326
327
328/*
329 * Get timebase clock frequency
330 */
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600331#ifndef CONFIG_SYS_FSL_TBCLK_DIV
332#define CONFIG_SYS_FSL_TBCLK_DIV 8
333#endif
Alexander Grafc3468482014-04-11 17:09:45 +0200334__weak unsigned long get_tbclk (void)
wdenk9c53f402003-10-15 23:53:47 +0000335{
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600336 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
337
338 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
wdenk9c53f402003-10-15 23:53:47 +0000339}
340
341
342#if defined(CONFIG_WATCHDOG)
Boschung, Rainerf63c0dc12014-06-03 09:05:14 +0200343#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
344void
345init_85xx_watchdog(void)
346{
347 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
348 TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
349}
350
wdenk9c53f402003-10-15 23:53:47 +0000351void
wdenk9c53f402003-10-15 23:53:47 +0000352reset_85xx_watchdog(void)
353{
354 /*
355 * Clear TSR(WIS) bit by writing 1
356 */
Mark Marshall10b13c92012-09-09 23:06:03 +0000357 mtspr(SPRN_TSR, TSR_WIS);
wdenk9c53f402003-10-15 23:53:47 +0000358}
Horst Kronstorferf70831e2013-03-13 10:14:05 +0000359
360void
361watchdog_reset(void)
362{
363 int re_enable = disable_interrupts();
364
365 reset_85xx_watchdog();
366 if (re_enable)
367 enable_interrupts();
368}
wdenk9c53f402003-10-15 23:53:47 +0000369#endif /* CONFIG_WATCHDOG */
370
Sergei Poselenovddc1a472008-06-06 15:42:40 +0200371/*
Andy Fleming6843a6e2008-10-30 16:51:33 -0500372 * Initializes on-chip MMC controllers.
373 * to override, implement board_mmc_init()
374 */
375int cpu_mmc_init(bd_t *bis)
376{
377#ifdef CONFIG_FSL_ESDHC
378 return fsl_esdhc_mmc_init(bis);
379#else
380 return 0;
381#endif
382}
Becky Bruceee888da2010-06-17 11:37:25 -0500383
384/*
385 * Print out the state of various machine registers.
Dipen Dudhat00c42942011-01-20 16:29:35 +0530386 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
387 * parameters for IFC and TLBs
Becky Bruceee888da2010-06-17 11:37:25 -0500388 */
Christophe Leroy31f6e932017-07-13 15:09:54 +0200389void print_reginfo(void)
Becky Bruceee888da2010-06-17 11:37:25 -0500390{
391 print_tlbcam();
392 print_laws();
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530393#if defined(CONFIG_FSL_LBC)
Becky Bruceee888da2010-06-17 11:37:25 -0500394 print_lbc_regs();
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530395#endif
Dipen Dudhat00c42942011-01-20 16:29:35 +0530396#ifdef CONFIG_FSL_IFC
397 print_ifc_regs();
398#endif
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530399
Becky Bruceee888da2010-06-17 11:37:25 -0500400}
York Sunc41b7442010-09-28 15:20:33 -0700401
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600402/* Common ddr init for non-corenet fsl 85xx platforms */
403#ifndef CONFIG_FSL_CORENET
Scott Wood095b7122012-09-20 19:02:18 -0500404#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
405 !defined(CONFIG_SYS_INIT_L2_ADDR)
Simon Glassd35f3382017-04-06 12:47:05 -0600406int dram_init(void)
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600407{
Alexander Grafc3468482014-04-11 17:09:45 +0200408#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
York Sun51e91e82016-11-18 12:29:51 -0800409 defined(CONFIG_ARCH_QEMU_E500)
Simon Glass39f90ba2017-03-31 08:40:25 -0600410 gd->ram_size = fsl_ddr_sdram_size();
Zhao Chenhui1a35f3d2011-01-28 17:58:37 +0800411#else
Simon Glass39f90ba2017-03-31 08:40:25 -0600412 gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Zhao Chenhui1a35f3d2011-01-28 17:58:37 +0800413#endif
Simon Glass39f90ba2017-03-31 08:40:25 -0600414
415 return 0;
Zhao Chenhui1a35f3d2011-01-28 17:58:37 +0800416}
417#else /* CONFIG_SYS_RAMBOOT */
Simon Glassd35f3382017-04-06 12:47:05 -0600418int dram_init(void)
Zhao Chenhui1a35f3d2011-01-28 17:58:37 +0800419{
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600420 phys_size_t dram_size = 0;
421
Becky Bruce4212f232010-12-17 17:17:58 -0600422#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600423 {
424 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
425 unsigned int x = 10;
426 unsigned int i;
427
428 /*
429 * Work around to stabilize DDR DLL
430 */
431 out_be32(&gur->ddrdllcr, 0x81000000);
432 asm("sync;isync;msync");
433 udelay(200);
434 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
435 setbits_be32(&gur->devdisr, 0x00010000);
436 for (i = 0; i < x; i++)
437 ;
438 clrbits_be32(&gur->devdisr, 0x00010000);
439 x++;
440 }
441 }
442#endif
443
York Sune73cc042011-06-07 09:42:16 +0800444#if defined(CONFIG_SPD_EEPROM) || \
445 defined(CONFIG_DDR_SPD) || \
446 defined(CONFIG_SYS_DDR_RAW_TIMING)
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600447 dram_size = fsl_ddr_sdram();
448#else
449 dram_size = fixed_sdram();
450#endif
451 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
452 dram_size *= 0x100000;
453
454#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
455 /*
456 * Initialize and enable DDR ECC.
457 */
458 ddr_enable_ecc(dram_size);
459#endif
460
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530461#if defined(CONFIG_FSL_LBC)
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600462 /* Some boards also have sdram on the lbc */
Becky Bruceb88d3d02010-12-17 17:17:57 -0600463 lbc_sdram_init();
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530464#endif
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600465
Wolfgang Denkf2bbb532011-07-25 10:13:53 +0200466 debug("DDR: ");
Simon Glass39f90ba2017-03-31 08:40:25 -0600467 gd->ram_size = dram_size;
468
469 return 0;
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600470}
Zhao Chenhui1a35f3d2011-01-28 17:58:37 +0800471#endif /* CONFIG_SYS_RAMBOOT */
Becky Bruce5e35d8a2010-12-17 17:17:56 -0600472#endif
473
York Sunc41b7442010-09-28 15:20:33 -0700474#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
475
476/* Board-specific functions defined in each board's ddr.c */
477void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
York Sun79a779b2014-08-01 15:51:00 -0700478 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
York Sunc41b7442010-09-28 15:20:33 -0700479void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
480 phys_addr_t *rpn);
481unsigned int
482 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
483
Becky Bruce69694472011-07-18 18:49:15 -0500484void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
485
York Sunc41b7442010-09-28 15:20:33 -0700486static void dump_spd_ddr_reg(void)
487{
488 int i, j, k, m;
489 u8 *p_8;
490 u32 *p_32;
York Sunfe845072016-12-28 08:43:45 -0800491 struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
York Sunc41b7442010-09-28 15:20:33 -0700492 generic_spd_eeprom_t
York Sunfe845072016-12-28 08:43:45 -0800493 spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
York Sunc41b7442010-09-28 15:20:33 -0700494
York Sunfe845072016-12-28 08:43:45 -0800495 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
York Sun79a779b2014-08-01 15:51:00 -0700496 fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
York Sunc41b7442010-09-28 15:20:33 -0700497
Robert P. J. Dayc5b1e5d2016-09-07 14:27:59 -0400498 puts("SPD data of all dimms (zero value is omitted)...\n");
York Sunc41b7442010-09-28 15:20:33 -0700499 puts("Byte (hex) ");
500 k = 1;
York Sunfe845072016-12-28 08:43:45 -0800501 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
York Sunc41b7442010-09-28 15:20:33 -0700502 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
503 printf("Dimm%d ", k++);
504 }
505 puts("\n");
506 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
507 m = 0;
508 printf("%3d (0x%02x) ", k, k);
York Sunfe845072016-12-28 08:43:45 -0800509 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
York Sunc41b7442010-09-28 15:20:33 -0700510 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
511 p_8 = (u8 *) &spd[i][j];
512 if (p_8[k]) {
513 printf("0x%02x ", p_8[k]);
514 m++;
515 } else
516 puts(" ");
517 }
518 }
519 if (m)
520 puts("\n");
521 else
522 puts("\r");
523 }
524
York Sunfe845072016-12-28 08:43:45 -0800525 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
York Sunc41b7442010-09-28 15:20:33 -0700526 switch (i) {
527 case 0:
York Sunf0626592013-09-30 09:22:09 -0700528 ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
York Sunc41b7442010-09-28 15:20:33 -0700529 break;
York Sunfe845072016-12-28 08:43:45 -0800530#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
York Sunc41b7442010-09-28 15:20:33 -0700531 case 1:
York Sunf0626592013-09-30 09:22:09 -0700532 ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
York Sunc41b7442010-09-28 15:20:33 -0700533 break;
534#endif
York Sunfe845072016-12-28 08:43:45 -0800535#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
York Sune8dc17b2012-08-17 08:22:39 +0000536 case 2:
York Sunf0626592013-09-30 09:22:09 -0700537 ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
York Sune8dc17b2012-08-17 08:22:39 +0000538 break;
539#endif
York Sunfe845072016-12-28 08:43:45 -0800540#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
York Sune8dc17b2012-08-17 08:22:39 +0000541 case 3:
York Sunf0626592013-09-30 09:22:09 -0700542 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
York Sune8dc17b2012-08-17 08:22:39 +0000543 break;
544#endif
York Sunc41b7442010-09-28 15:20:33 -0700545 default:
546 printf("%s unexpected controller number = %u\n",
547 __func__, i);
548 return;
549 }
550 }
551 printf("DDR registers dump for all controllers "
Robert P. J. Dayc5b1e5d2016-09-07 14:27:59 -0400552 "(zero value is omitted)...\n");
York Sunc41b7442010-09-28 15:20:33 -0700553 puts("Offset (hex) ");
York Sunfe845072016-12-28 08:43:45 -0800554 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
York Sunc41b7442010-09-28 15:20:33 -0700555 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
556 puts("\n");
York Suna21803d2013-11-18 10:29:32 -0800557 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
York Sunc41b7442010-09-28 15:20:33 -0700558 m = 0;
559 printf("%6d (0x%04x)", k * 4, k * 4);
York Sunfe845072016-12-28 08:43:45 -0800560 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
York Sunc41b7442010-09-28 15:20:33 -0700561 p_32 = (u32 *) ddr[i];
562 if (p_32[k]) {
563 printf(" 0x%08x", p_32[k]);
564 m++;
565 } else
566 puts(" ");
567 }
568 if (m)
569 puts("\n");
570 else
571 puts("\r");
572 }
573 puts("\n");
574}
575
576/* invalid the TLBs for DDR and setup new ones to cover p_addr */
577static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
578{
579 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
580 unsigned long epn;
581 u32 tsize, valid, ptr;
York Sunc41b7442010-09-28 15:20:33 -0700582 int ddr_esel;
583
Becky Bruce69694472011-07-18 18:49:15 -0500584 clear_ddr_tlbs_phys(p_addr, size>>20);
York Sunc41b7442010-09-28 15:20:33 -0700585
586 /* Setup new tlb to cover the physical address */
587 setup_ddr_tlbs_phys(p_addr, size>>20);
588
589 ptr = vstart;
590 ddr_esel = find_tlb_idx((void *)ptr, 1);
591 if (ddr_esel != -1) {
592 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
593 } else {
594 printf("TLB error in function %s\n", __func__);
595 return -1;
596 }
597
598 return 0;
599}
600
601/*
602 * slide the testing window up to test another area
603 * for 32_bit system, the maximum testable memory is limited to
604 * CONFIG_MAX_MEM_MAPPED
605 */
606int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
607{
608 phys_addr_t test_cap, p_addr;
609 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
610
611#if !defined(CONFIG_PHYS_64BIT) || \
612 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
613 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
614 test_cap = p_size;
615#else
616 test_cap = gd->ram_size;
617#endif
618 p_addr = (*vstart) + (*size) + (*phys_offset);
619 if (p_addr < test_cap - 1) {
620 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
621 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
622 return -1;
623 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
624 *size = (u32) p_size;
625 printf("Testing 0x%08llx - 0x%08llx\n",
626 (u64)(*vstart) + (*phys_offset),
627 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
628 } else
629 return 1;
630
631 return 0;
632}
633
634/* initialization for testing area */
635int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
636{
637 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
638
639 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
640 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
641 *phys_offset = 0;
642
643#if !defined(CONFIG_PHYS_64BIT) || \
644 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
645 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
646 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
647 puts("Cannot test more than ");
648 print_size(CONFIG_MAX_MEM_MAPPED,
649 " without proper 36BIT support.\n");
650 }
651#endif
652 printf("Testing 0x%08llx - 0x%08llx\n",
653 (u64)(*vstart) + (*phys_offset),
654 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
655
656 return 0;
657}
658
659/* invalid TLBs for DDR and remap as normal after testing */
660int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
661{
662 unsigned long epn;
663 u32 tsize, valid, ptr;
664 phys_addr_t rpn = 0;
665 int ddr_esel;
666
667 /* disable the TLBs for this testing */
668 ptr = *vstart;
669
670 while (ptr < (*vstart) + (*size)) {
671 ddr_esel = find_tlb_idx((void *)ptr, 1);
672 if (ddr_esel != -1) {
673 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
674 disable_tlb(ddr_esel);
675 }
676 ptr += TSIZE_TO_BYTES(tsize);
677 }
678
679 puts("Remap DDR ");
680 setup_ddr_tlbs(gd->ram_size>>20);
681 puts("\n");
682
683 return 0;
684}
685
686void arch_memory_failure_handle(void)
687{
688 dump_spd_ddr_reg();
689}
690#endif