Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 1 | menu "MediaTek MIPS platforms" |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 2 | depends on ARCH_MTMIPS |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 3 | |
Guillaume La Roque | a24e1cf | 2021-09-10 10:21:06 +0200 | [diff] [blame] | 4 | config SYS_VENDOR |
| 5 | default "mediatek" if BOARD_MT7628_RFB || BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB |
| 6 | |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 7 | config SYS_MALLOC_F_LEN |
| 8 | default 0x1000 |
| 9 | |
| 10 | config SYS_SOC |
developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 11 | default "mt7620" if SOC_MT7620 |
developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 12 | default "mt7621" if SOC_MT7621 |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 13 | default "mt7628" if SOC_MT7628 |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 14 | |
developer | 26f763e | 2020-04-21 09:28:26 +0200 | [diff] [blame] | 15 | config SYS_DCACHE_SIZE |
| 16 | default 32768 |
| 17 | |
| 18 | config SYS_DCACHE_LINE_SIZE |
| 19 | default 32 |
| 20 | |
| 21 | config SYS_ICACHE_SIZE |
developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 22 | default 65536 if SOC_MT7620 || SOC_MT7628 |
| 23 | default 32768 if SOC_MT7621 |
developer | 26f763e | 2020-04-21 09:28:26 +0200 | [diff] [blame] | 24 | |
| 25 | config SYS_ICACHE_LINE_SIZE |
| 26 | default 32 |
| 27 | |
developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 28 | config SYS_SCACHE_LINE_SIZE |
| 29 | default 32 if SOC_MT7621 |
| 30 | |
Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 31 | config TEXT_BASE |
developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 32 | default 0x9c000000 if !SPL && !SOC_MT7621 |
| 33 | default 0x80200000 if SPL || SOC_MT7621 |
developer | 19d572e | 2020-04-21 09:28:47 +0200 | [diff] [blame] | 34 | |
| 35 | config SPL_TEXT_BASE |
developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 36 | default 0x9c000000 if !SOC_MT7621 |
| 37 | default 0x80100000 if SOC_MT7621 |
| 38 | |
| 39 | config SPL_SIZE_LIMIT |
| 40 | default 0x30000 if SOC_MT7621 |
| 41 | |
| 42 | config TPL_TEXT_BASE |
| 43 | default 0xbfc00000 if SOC_MT7621 |
| 44 | |
| 45 | config TPL_MAX_SIZE |
| 46 | default 4096 if SOC_MT7621 |
developer | 29b37c5 | 2020-04-21 09:28:34 +0200 | [diff] [blame] | 47 | |
developer | 19d572e | 2020-04-21 09:28:47 +0200 | [diff] [blame] | 48 | config SPL_PAYLOAD |
| 49 | default "u-boot-lzma.img" if SPL_LZMA |
| 50 | |
| 51 | config BUILD_TARGET |
developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 52 | default "u-boot-with-spl.bin" if SPL && !SOC_MT7621 |
| 53 | default "u-boot-lzma.img" if SOC_MT7621 |
developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 54 | default "u-boot.bin" |
developer | 19d572e | 2020-04-21 09:28:47 +0200 | [diff] [blame] | 55 | |
developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 56 | config MAX_MEM_SIZE |
| 57 | int |
| 58 | default 256 if SOC_MT7620 || SOC_MT7628 |
| 59 | default 512 if SOC_MT7621 |
| 60 | |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 61 | choice |
| 62 | prompt "MediaTek MIPS SoC select" |
| 63 | |
developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 64 | config SOC_MT7620 |
| 65 | bool "MT7620" |
Tom Rini | 3ef67ae | 2021-08-26 11:47:59 -0400 | [diff] [blame] | 66 | select SYS_CACHE_SHIFT_5 |
developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 67 | select SYS_MIPS_CACHE_INIT_RAM_LOAD |
| 68 | select PINCTRL_MT7620 |
| 69 | select MT7620_SERIAL |
| 70 | select MISC |
| 71 | select SPL_SEPARATE_BSS if SPL |
| 72 | select SPL_LOADER_SUPPORT if SPL |
| 73 | select SPL_OF_CONTROL if SPL_DM |
| 74 | select SPL_OF_PLATDATA if SPL_DM |
| 75 | select SPL_DM_SERIAL if SPL_DM |
| 76 | help |
| 77 | This supports MediaTek MT7620. |
| 78 | |
developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 79 | config SOC_MT7621 |
| 80 | bool "MT7621" |
| 81 | select MIPS_CM |
| 82 | select MIPS_L2_CACHE |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame^] | 83 | select MMC_SUPPORTS_TUNING |
developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 84 | select SYS_CACHE_SHIFT_5 |
| 85 | select SYS_MIPS_CACHE_INIT_RAM_LOAD |
| 86 | select PINCTRL_MT7621 |
| 87 | select MTK_SERIAL |
| 88 | select REGMAP |
| 89 | select SYSCON |
| 90 | select BINMAN |
| 91 | select SUPPORT_TPL |
| 92 | select SPL_LOADER_SUPPORT if SPL |
| 93 | select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL |
| 94 | help |
| 95 | This supports MediaTek MT7621. |
| 96 | |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 97 | config SOC_MT7628 |
| 98 | bool "MT7628" |
Tom Rini | 3ef67ae | 2021-08-26 11:47:59 -0400 | [diff] [blame] | 99 | select SYS_CACHE_SHIFT_5 |
developer | 29b37c5 | 2020-04-21 09:28:34 +0200 | [diff] [blame] | 100 | select MIPS_INIT_STACK_IN_SRAM |
| 101 | select MIPS_SRAM_INIT |
| 102 | select SYS_MIPS_CACHE_INIT_RAM_LOAD |
developer | 591826e | 2019-09-25 17:45:43 +0800 | [diff] [blame] | 103 | select PINCTRL_MT7628 |
| 104 | select MTK_SERIAL |
developer | 93f7400 | 2020-11-12 16:35:28 +0800 | [diff] [blame] | 105 | select SYSRESET |
developer | 3b3015f | 2020-04-21 09:28:30 +0200 | [diff] [blame] | 106 | select SYSRESET_RESETCTL |
developer | 19d572e | 2020-04-21 09:28:47 +0200 | [diff] [blame] | 107 | select SPL_SEPARATE_BSS if SPL |
| 108 | select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL |
| 109 | select SPL_LOADER_SUPPORT if SPL |
| 110 | select SPL_OF_CONTROL if SPL_DM |
| 111 | select SPL_SIMPLE_BUS if SPL_DM |
| 112 | select SPL_DM_SERIAL if SPL_DM |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 113 | select SPL_CLK if SPL_DM && SPL_SERIAL |
developer | 19d572e | 2020-04-21 09:28:47 +0200 | [diff] [blame] | 114 | select SPL_SYSRESET if SPL_DM |
| 115 | select SPL_OF_LIBFDT if SPL_OF_CONTROL |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 116 | help |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 117 | This supports MediaTek MT7628/MT7688. |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 118 | |
| 119 | endchoice |
| 120 | |
developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 121 | source "arch/mips/mach-mtmips/mt7620/Kconfig" |
developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 122 | source "arch/mips/mach-mtmips/mt7621/Kconfig" |
developer | 37e34ba | 2020-11-12 16:35:23 +0800 | [diff] [blame] | 123 | source "arch/mips/mach-mtmips/mt7628/Kconfig" |
Stefan Roese | 2052a93 | 2018-08-16 15:27:30 +0200 | [diff] [blame] | 124 | |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 125 | endmenu |