| Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 1 | menu "MediaTek MIPS platforms" |
| 2 | depends on ARCH_MT7620 |
| 3 | |
| 4 | config SYS_MALLOC_F_LEN |
| 5 | default 0x1000 |
| 6 | |
| 7 | config SYS_SOC |
| 8 | default "mt7620" if SOC_MT7620 |
| 9 | |
| 10 | choice |
| 11 | prompt "MediaTek MIPS SoC select" |
| 12 | |
| 13 | config SOC_MT7620 |
| 14 | bool "MT7620/8" |
| 15 | select MIPS_L1_CACHE_SHIFT_5 |
| 16 | help |
| 17 | This supports MediaTek MIPS MT7620 family. |
| 18 | |
| 19 | endchoice |
| 20 | |
| 21 | choice |
| 22 | prompt "Board select" |
| 23 | |
| Stefan Roese | 2052a93 | 2018-08-16 15:27:30 +0200 | [diff] [blame^] | 24 | config BOARD_LINKIT_SMART_7688 |
| 25 | bool "LinkIt Smart 7688" |
| 26 | depends on SOC_MT7620 |
| 27 | select SUPPORTS_BOOT_RAM |
| 28 | help |
| 29 | Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM |
| 30 | and 32 MiB of flash (SPI). |
| 31 | Between its different peripherals there's an integrated switch with 4 |
| 32 | ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and |
| 33 | a MT7688 (PCIe). |
| 34 | |
| Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 35 | endchoice |
| 36 | |
| 37 | choice |
| 38 | prompt "Boot mode" |
| 39 | |
| 40 | config BOOT_RAM |
| 41 | bool "RAM boot" |
| 42 | depends on SUPPORTS_BOOT_RAM |
| 43 | help |
| 44 | This builds an image that is linked to a RAM address. It can be used |
| 45 | for booting from CFE via TFTP using an ELF image, but it can also be |
| 46 | booted from RAM by other bootloaders using a BIN image. |
| 47 | |
| 48 | config BOOT_ROM |
| 49 | bool "ROM boot" |
| 50 | depends on SUPPORTS_BOOT_RAM |
| 51 | help |
| 52 | This builds an image that is linked to a ROM address. It can be |
| 53 | used as main bootloader image which is programmed onto the onboard |
| 54 | flash storage (SPI NOR). |
| 55 | |
| 56 | endchoice |
| 57 | |
| 58 | choice |
| 59 | prompt "DDR2 size" |
| 60 | |
| 61 | config ONBOARD_DDR2_SIZE_256MBIT |
| 62 | bool "256MBit (32MByte) total size" |
| 63 | depends on BOOT_ROM |
| 64 | help |
| 65 | Use 256MBit (32MByte) of DDR total size |
| 66 | |
| 67 | config ONBOARD_DDR2_SIZE_512MBIT |
| 68 | bool "512MBit (64MByte) total size" |
| 69 | depends on BOOT_ROM |
| 70 | help |
| 71 | Use 512MBit (64MByte) of DDR total size |
| 72 | |
| 73 | config ONBOARD_DDR2_SIZE_1024MBIT |
| 74 | bool "1024MBit (128MByte) total size" |
| 75 | depends on BOOT_ROM |
| 76 | help |
| 77 | Use 1024MBit (128MByte) of DDR total size |
| 78 | |
| 79 | config ONBOARD_DDR2_SIZE_2048MBIT |
| 80 | bool "2048MBit (256MByte) total size" |
| 81 | depends on BOOT_ROM |
| 82 | help |
| 83 | Use 2048MBit (256MByte) of DDR total size |
| 84 | |
| 85 | endchoice |
| 86 | |
| 87 | choice |
| 88 | prompt "DDR2 chip width" |
| 89 | |
| 90 | config ONBOARD_DDR2_CHIP_WIDTH_8BIT |
| 91 | bool "8bit DDR chip width" |
| 92 | depends on BOOT_ROM |
| 93 | help |
| 94 | Use DDR chips with 8bit width |
| 95 | |
| 96 | config ONBOARD_DDR2_CHIP_WIDTH_16BIT |
| 97 | bool "16bit DDR chip width" |
| 98 | depends on BOOT_ROM |
| 99 | help |
| 100 | Use DDR chips with 16bit width |
| 101 | |
| 102 | endchoice |
| 103 | |
| 104 | choice |
| 105 | prompt "DDR2 bus width" |
| 106 | |
| 107 | config ONBOARD_DDR2_BUS_WIDTH_16BIT |
| 108 | bool "16bit DDR bus width" |
| 109 | depends on BOOT_ROM |
| 110 | help |
| 111 | Use 16bit DDR bus width |
| 112 | |
| 113 | config ONBOARD_DDR2_BUS_WIDTH_32BIT |
| 114 | bool "32bit DDR bus width" |
| 115 | depends on BOOT_ROM |
| 116 | help |
| 117 | Use 32bit DDR bus width |
| 118 | |
| 119 | endchoice |
| 120 | |
| 121 | config SUPPORTS_BOOT_RAM |
| 122 | bool |
| 123 | |
| Stefan Roese | 2052a93 | 2018-08-16 15:27:30 +0200 | [diff] [blame^] | 124 | source "board/seeed/linkit-smart-7688/Kconfig" |
| 125 | |
| Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 126 | endmenu |