Blame - arch/mips/mach-mtmips/Kconfig - filogic/uboot

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Stefan Roese	65da15e	2018-09-05 15:12:35 +0200	[diff] [blame]	1	menu "MediaTek MIPS platforms"
developer	89f051b	2019-04-30 11:13:58 +0800	[diff] [blame]	2	depends on ARCH_MTMIPS
Stefan Roese	65da15e	2018-09-05 15:12:35 +0200	[diff] [blame]	3
				4	config SYS_MALLOC_F_LEN
				5	default 0x1000
				6
				7	config SYS_SOC
developer	89f051b	2019-04-30 11:13:58 +0800	[diff] [blame]	8	default "mt7628" if SOC_MT7628
Stefan Roese	65da15e	2018-09-05 15:12:35 +0200	[diff] [blame]	9
developer	26f763e	2020-04-21 09:28:26 +0200	[diff] [blame]	10	config SYS_DCACHE_SIZE
				11	default 32768
				12
				13	config SYS_DCACHE_LINE_SIZE
				14	default 32
				15
				16	config SYS_ICACHE_SIZE
				17	default 65536
				18
				19	config SYS_ICACHE_LINE_SIZE
				20	default 32
				21
developer	29b37c5	2020-04-21 09:28:34 +0200	[diff] [blame]	22	config SYS_TEXT_BASE
developer	19d572e	2020-04-21 09:28:47 +0200	[diff] [blame^]	23	default 0x9c000000 if !SPL
				24	default 0x80200000 if SPL
				25
				26	config SPL_TEXT_BASE
developer	29b37c5	2020-04-21 09:28:34 +0200	[diff] [blame]	27	default 0x9c000000
				28
developer	19d572e	2020-04-21 09:28:47 +0200	[diff] [blame^]	29	config SPL_PAYLOAD
				30	default "u-boot-lzma.img" if SPL_LZMA
				31
				32	config BUILD_TARGET
				33	default "u-boot-with-spl.bin" if SPL
				34
Stefan Roese	65da15e	2018-09-05 15:12:35 +0200	[diff] [blame]	35	choice
				36	prompt "MediaTek MIPS SoC select"
				37
developer	89f051b	2019-04-30 11:13:58 +0800	[diff] [blame]	38	config SOC_MT7628
				39	bool "MT7628"
Stefan Roese	65da15e	2018-09-05 15:12:35 +0200	[diff] [blame]	40	select MIPS_L1_CACHE_SHIFT_5
developer	29b37c5	2020-04-21 09:28:34 +0200	[diff] [blame]	41	select MIPS_INIT_STACK_IN_SRAM
				42	select MIPS_SRAM_INIT
				43	select SYS_MIPS_CACHE_INIT_RAM_LOAD
developer	591826e	2019-09-25 17:45:43 +0800	[diff] [blame]	44	select PINCTRL_MT7628
				45	select MTK_SERIAL
developer	3b3015f	2020-04-21 09:28:30 +0200	[diff] [blame]	46	select SYSRESET_RESETCTL
developer	19d572e	2020-04-21 09:28:47 +0200	[diff] [blame^]	47	select SPL_SEPARATE_BSS if SPL
				48	select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL
				49	select SPL_LOADER_SUPPORT if SPL
				50	select SPL_OF_CONTROL if SPL_DM
				51	select SPL_SIMPLE_BUS if SPL_DM
				52	select SPL_DM_SERIAL if SPL_DM
				53	select SPL_CLK if SPL_DM && SPL_SERIAL_SUPPORT
				54	select SPL_SYSRESET if SPL_DM
				55	select SPL_OF_LIBFDT if SPL_OF_CONTROL
Stefan Roese	65da15e	2018-09-05 15:12:35 +0200	[diff] [blame]	56	help
developer	89f051b	2019-04-30 11:13:58 +0800	[diff] [blame]	57	This supports MediaTek MT7628/MT7688.
Stefan Roese	65da15e	2018-09-05 15:12:35 +0200	[diff] [blame]	58
				59	endchoice
				60
				61	choice
				62	prompt "Board select"
				63
Stefan Roese	115802d	2018-08-16 15:27:31 +0200	[diff] [blame]	64	config BOARD_GARDENA_SMART_GATEWAY_MT7688
Stefan Roese	f08cc08	2019-03-15 09:09:34 +0100	[diff] [blame]	65	bool "GARDENA smart Gateway"
developer	89f051b	2019-04-30 11:13:58 +0800	[diff] [blame]	66	depends on SOC_MT7628
Stefan Roese	d0fdd67	2018-10-09 08:59:13 +0200	[diff] [blame]	67	select BOARD_LATE_INIT
Stefan Roese	115802d	2018-08-16 15:27:31 +0200	[diff] [blame]	68	select SUPPORTS_BOOT_RAM
				69	help
Stefan Roese	f08cc08	2019-03-15 09:09:34 +0100	[diff] [blame]	70	GARDENA smart Gateway boards have a MT7688 SoC with 128 MiB of RAM
Stefan Roese	115802d	2018-08-16 15:27:31 +0200	[diff] [blame]	71	and 8 MiB of flash (SPI NOR) and additional SPI NAND storage.
				72
Stefan Roese	2052a93	2018-08-16 15:27:30 +0200	[diff] [blame]	73	config BOARD_LINKIT_SMART_7688
				74	bool "LinkIt Smart 7688"
developer	89f051b	2019-04-30 11:13:58 +0800	[diff] [blame]	75	depends on SOC_MT7628
Stefan Roese	2052a93	2018-08-16 15:27:30 +0200	[diff] [blame]	76	select SUPPORTS_BOOT_RAM
				77	help
				78	Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM
				79	and 32 MiB of flash (SPI).
				80	Between its different peripherals there's an integrated switch with 4
				81	ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
				82	a MT7688 (PCIe).
				83
Stefan Roese	65da15e	2018-09-05 15:12:35 +0200	[diff] [blame]	84	endchoice
				85
				86	choice
				87	prompt "Boot mode"
				88
				89	config BOOT_RAM
				90	bool "RAM boot"
				91	depends on SUPPORTS_BOOT_RAM
				92	help
				93	This builds an image that is linked to a RAM address. It can be used
				94	for booting from CFE via TFTP using an ELF image, but it can also be
				95	booted from RAM by other bootloaders using a BIN image.
				96
				97	config BOOT_ROM
				98	bool "ROM boot"
				99	depends on SUPPORTS_BOOT_RAM
				100	help
				101	This builds an image that is linked to a ROM address. It can be
				102	used as main bootloader image which is programmed onto the onboard
				103	flash storage (SPI NOR).
				104
				105	endchoice
				106
Stefan Roese	65da15e	2018-09-05 15:12:35 +0200	[diff] [blame]	107	config SUPPORTS_BOOT_RAM
				108	bool
				109
developer	19d572e	2020-04-21 09:28:47 +0200	[diff] [blame^]	110	config SPL_UART2_SPIS_PINMUX
				111	bool "Use alternative pinmux for UART2 in SPL stage"
				112	depends on SPL_SERIAL_SUPPORT
				113	default n
				114	help
				115	Select this if the UART2 of your board is connected to GPIO 16/17
				116	(shared with SPIS) rather than the usual GPIO 20/21.
				117
Stefan Roese	115802d	2018-08-16 15:27:31 +0200	[diff] [blame]	118	source "board/gardena/smart-gateway-mt7688/Kconfig"
Stefan Roese	2052a93	2018-08-16 15:27:30 +0200	[diff] [blame]	119	source "board/seeed/linkit-smart-7688/Kconfig"
				120
Stefan Roese	65da15e	2018-09-05 15:12:35 +0200	[diff] [blame]	121	endmenu